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Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / xgifb / vb_init.c
CommitLineData
949eb0ae 1#include <linux/delay.h>
02a81dd9 2#include <linux/vmalloc.h>
6048d761 3
d7636e0b 4#include "XGIfb.h"
d7636e0b 5#include "vb_def.h"
d7636e0b 6#include "vb_util.h"
7#include "vb_setmode.h"
e054102b 8#include "vb_init.h"
d6461e49
PH		 9static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
10 { 16, 0x45},
11 { 8, 0x35},
12 { 4, 0x31},
13 { 2, 0x21} };
14
15static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
16 { 128, 0x5D},
17 { 64, 0x59},
18 { 64, 0x4D},
19 { 32, 0x55},
20 { 32, 0x49},
21 { 32, 0x3D},
22 { 16, 0x51},
23 { 16, 0x45},
24 { 16, 0x39},
25 { 8, 0x41},
26 { 8, 0x35},
27 { 4, 0x31} };
d7636e0b 28
02a81dd9
AK		 29#define XGIFB_ROM_SIZE 65536
30
bf32fcb9
KT		 31static unsigned char
32XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
d7636e0b 34{
b9ebf5e5 35 unsigned char data, temp;
d7636e0b 36
b9ebf5e5 37 if (HwDeviceExtension->jChipType < XG20) {
6d12dae4
PH		 38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
39 if (data == 0)
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
41 0x02) >> 1;
42 return data;
b9ebf5e5 43 } else if (HwDeviceExtension->jChipType == XG27) {
58839b01 44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
bf32fcb9 45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
6490311f 46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
b9ebf5e5
AK		 47 data = 0; /* DDR */
48 else
49 data = 1; /* DDRII */
50 return data;
51 } else if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
c45715bb 54 udelay(800);
b9bf6e4e 55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
bf32fcb9
KT		 56 /* GPIOF 0:DVI 1:DVO */
57 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5 58 /* HOTPLUG_SUPPORT */
bf32fcb9
KT		 59 /* for current XG20 & XG21, GPIOH is floating, driver will
60 * fix DDR temporarily */
b9ebf5e5
AK		 61 if (temp & 0x01) /* DVI read GPIOH */
62 data = 1; /* DDRII */
63 else
64 data = 0; /* DDR */
65 /* ~HOTPLUG_SUPPORT */
b9bf6e4e 66 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
b9ebf5e5
AK		 67 return data;
68 } else {
58839b01 69 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
d7636e0b 70
b9ebf5e5
AK		 71 if (data == 1)
72 data++;
d7636e0b 73
b9ebf5e5
AK		 74 return data;
75 }
76}
d7636e0b 77
bf32fcb9
KT		 78static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
79 struct vb_device_info *pVBInfo)
b9ebf5e5 80{
8104e329
AK		 81 xgifb_reg_set(P3c4, 0x18, 0x01);
82 xgifb_reg_set(P3c4, 0x19, 0x20);
83 xgifb_reg_set(P3c4, 0x16, 0x00);
84 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 85
6d12dae4
PH		 86 mdelay(3);
87 xgifb_reg_set(P3c4, 0x18, 0x00);
88 xgifb_reg_set(P3c4, 0x19, 0x20);
89 xgifb_reg_set(P3c4, 0x16, 0x00);
90 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 91
c45715bb 92 udelay(60);
2af1a29d
AK		 93 xgifb_reg_set(P3c4,
94 0x18,
95 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 96 xgifb_reg_set(P3c4, 0x19, 0x01);
97 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
98 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
c83c620a 99 mdelay(1);
8104e329 100 xgifb_reg_set(P3c4, 0x1B, 0x03);
c45715bb 101 udelay(500);
2af1a29d
AK		 102 xgifb_reg_set(P3c4,
103 0x18,
104 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 105 xgifb_reg_set(P3c4, 0x19, 0x00);
106 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
107 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
108 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 109}
d7636e0b 110
b9ebf5e5
AK		 111static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
112 struct vb_device_info *pVBInfo)
113{
d7636e0b 114
bf32fcb9
KT		 115 xgifb_reg_set(pVBInfo->P3c4,
116 0x28,
2af1a29d 117 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
bf32fcb9
KT		 118 xgifb_reg_set(pVBInfo->P3c4,
119 0x29,
2af1a29d 120 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
bf32fcb9
KT		 121 xgifb_reg_set(pVBInfo->P3c4,
122 0x2A,
2af1a29d 123 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
bf32fcb9
KT		 124
125 xgifb_reg_set(pVBInfo->P3c4,
126 0x2E,
2af1a29d 127 pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
bf32fcb9
KT		 128 xgifb_reg_set(pVBInfo->P3c4,
129 0x2F,
2af1a29d 130 pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
bf32fcb9
KT		 131 xgifb_reg_set(pVBInfo->P3c4,
132 0x30,
2af1a29d 133 pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
bf32fcb9 134
949eb0ae
MG		 135 /* When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
136 /* Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
bf32fcb9 137 * Set SR32 D[1:0] = 10b */
b9ebf5e5 138 if (HwDeviceExtension->jChipType == XG42) {
2af1a29d
AK		 139 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
140 (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
141 (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
142 (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
143 ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
144 (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
bf32fcb9
KT		 145 xgifb_reg_set(pVBInfo->P3c4,
146 0x32,
147 ((unsigned char) xgifb_reg_get(
148 pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
b9ebf5e5
AK		 149 }
150}
d7636e0b 151
b9ebf5e5
AK		 152static void XGINew_DDRII_Bootup_XG27(
153 struct xgi_hw_device_info *HwDeviceExtension,
154 unsigned long P3c4, struct vb_device_info *pVBInfo)
155{
156 unsigned long P3d4 = P3c4 + 0x10;
2af1a29d 157 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b9ebf5e5 158 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
d7636e0b 159
b9ebf5e5 160 /* Set Double Frequency */
6d12dae4 161 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
d7636e0b 162
c45715bb 163 udelay(200);
d7636e0b 164
8104e329
AK		 165 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
166 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
167 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 168 udelay(15);
8104e329 169 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 170 udelay(15);
d7636e0b 171
8104e329
AK		 172 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
173 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
174 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 175 udelay(15);
8104e329 176 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 177 udelay(15);
d7636e0b 178
8104e329
AK		 179 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
180 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
181 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 182 udelay(30);
8104e329 183 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 184 udelay(15);
d7636e0b 185
8104e329
AK		 186 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
187 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
188 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
c45715bb 189 udelay(30);
8104e329
AK		 190 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
191 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
d7636e0b 192
8104e329 193 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
c45715bb 194 udelay(60);
8104e329 195 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
d7636e0b 196
8104e329
AK		 197 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
198 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
199 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d7636e0b 200
c45715bb 201 udelay(30);
8104e329 202 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
c45715bb 203 udelay(15);
d7636e0b 204
8104e329
AK		 205 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
206 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
207 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 208 udelay(30);
8104e329 209 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 210 udelay(15);
d7636e0b 211
8104e329
AK		 212 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
213 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
214 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 215 udelay(30);
8104e329 216 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 217 udelay(15);
d7636e0b 218
bf32fcb9
KT		 219 /* Set SR1B refresh control 000:close; 010:open */
220 xgifb_reg_set(P3c4, 0x1B, 0x04);
c45715bb 221 udelay(200);
d7636e0b 222
b9ebf5e5 223}
d7636e0b 224
b9ebf5e5
AK		 225static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
226 unsigned long P3c4, struct vb_device_info *pVBInfo)
227{
228 unsigned long P3d4 = P3c4 + 0x10;
d7636e0b 229
2af1a29d 230 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b9ebf5e5 231 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
d7636e0b 232
8104e329 233 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
d7636e0b 234
c45715bb 235 udelay(200);
8104e329
AK		 236 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
237 xgifb_reg_set(P3c4, 0x19, 0x80);
238 xgifb_reg_set(P3c4, 0x16, 0x05);
239 xgifb_reg_set(P3c4, 0x16, 0x85);
240
241 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
242 xgifb_reg_set(P3c4, 0x19, 0xC0);
243 xgifb_reg_set(P3c4, 0x16, 0x05);
244 xgifb_reg_set(P3c4, 0x16, 0x85);
245
246 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
247 xgifb_reg_set(P3c4, 0x19, 0x40);
248 xgifb_reg_set(P3c4, 0x16, 0x05);
249 xgifb_reg_set(P3c4, 0x16, 0x85);
250
8104e329
AK		 251 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
252 xgifb_reg_set(P3c4, 0x19, 0x02);
253 xgifb_reg_set(P3c4, 0x16, 0x05);
254 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 255
c45715bb 256 udelay(15);
8104e329 257 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
c45715bb 258 udelay(30);
8104e329 259 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
c45715bb 260 udelay(100);
a24d60f4 261
8104e329
AK		 262 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
263 xgifb_reg_set(P3c4, 0x19, 0x00);
264 xgifb_reg_set(P3c4, 0x16, 0x05);
265 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 266
c45715bb 267 udelay(200);
b9ebf5e5 268}
a24d60f4 269
bf32fcb9
KT		 270static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
271 struct vb_device_info *pVBInfo)
b9ebf5e5 272{
8104e329
AK		 273 xgifb_reg_set(P3c4, 0x18, 0x01);
274 xgifb_reg_set(P3c4, 0x19, 0x40);
275 xgifb_reg_set(P3c4, 0x16, 0x00);
276 xgifb_reg_set(P3c4, 0x16, 0x80);
c45715bb 277 udelay(60);
a24d60f4 278
8104e329
AK		 279 xgifb_reg_set(P3c4, 0x18, 0x00);
280 xgifb_reg_set(P3c4, 0x19, 0x40);
281 xgifb_reg_set(P3c4, 0x16, 0x00);
282 xgifb_reg_set(P3c4, 0x16, 0x80);
c45715bb 283 udelay(60);
2af1a29d
AK		 284 xgifb_reg_set(P3c4,
285 0x18,
286 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 287 xgifb_reg_set(P3c4, 0x19, 0x01);
288 xgifb_reg_set(P3c4, 0x16, 0x03);
289 xgifb_reg_set(P3c4, 0x16, 0x83);
c83c620a 290 mdelay(1);
8104e329 291 xgifb_reg_set(P3c4, 0x1B, 0x03);
c45715bb 292 udelay(500);
2af1a29d
AK		 293 xgifb_reg_set(P3c4,
294 0x18,
295 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 296 xgifb_reg_set(P3c4, 0x19, 0x00);
297 xgifb_reg_set(P3c4, 0x16, 0x03);
298 xgifb_reg_set(P3c4, 0x16, 0x83);
299 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 300}
a24d60f4 301
b9ebf5e5
AK		 302static void XGINew_DDR1x_DefaultRegister(
303 struct xgi_hw_device_info *HwDeviceExtension,
304 unsigned long Port, struct vb_device_info *pVBInfo)
305{
306 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 307
b9ebf5e5
AK		 308 if (HwDeviceExtension->jChipType >= XG20) {
309 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
bf32fcb9
KT		 310 xgifb_reg_set(P3d4,
311 0x82,
2af1a29d 312 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
bf32fcb9
KT		 313 xgifb_reg_set(P3d4,
314 0x85,
2af1a29d 315 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
bf32fcb9
KT		 316 xgifb_reg_set(P3d4,
317 0x86,
2af1a29d 318 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
a24d60f4 319
8104e329
AK		 320 xgifb_reg_set(P3d4, 0x98, 0x01);
321 xgifb_reg_set(P3d4, 0x9A, 0x02);
a24d60f4 322
b9ebf5e5
AK		 323 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
324 } else {
325 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
a24d60f4 326
b9ebf5e5 327 switch (HwDeviceExtension->jChipType) {
b9ebf5e5 328 case XG42:
bf32fcb9
KT		 329 /* CR82 */
330 xgifb_reg_set(P3d4,
331 0x82,
2af1a29d 332 pVBInfo->CR40[11][pVBInfo->ram_type]);
bf32fcb9
KT		 333 /* CR85 */
334 xgifb_reg_set(P3d4,
335 0x85,
2af1a29d 336 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 337 /* CR86 */
338 xgifb_reg_set(P3d4,
339 0x86,
2af1a29d 340 pVBInfo->CR40[13][pVBInfo->ram_type]);
b9ebf5e5
AK		 341 break;
342 default:
8104e329
AK		 343 xgifb_reg_set(P3d4, 0x82, 0x88);
344 xgifb_reg_set(P3d4, 0x86, 0x00);
bf32fcb9
KT		 345 /* Insert read command for delay */
346 xgifb_reg_get(P3d4, 0x86);
8104e329 347 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 348 xgifb_reg_get(P3d4, 0x86);
bf32fcb9
KT		 349 xgifb_reg_set(P3d4,
350 0x86,
2af1a29d 351 pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 352 xgifb_reg_set(P3d4, 0x82, 0x77);
353 xgifb_reg_set(P3d4, 0x85, 0x00);
bf32fcb9
KT		 354
355 /* Insert read command for delay */
356 xgifb_reg_get(P3d4, 0x85);
8104e329 357 xgifb_reg_set(P3d4, 0x85, 0x88);
bf32fcb9
KT		 358
359 /* Insert read command for delay */
360 xgifb_reg_get(P3d4, 0x85);
361 /* CR85 */
362 xgifb_reg_set(P3d4,
363 0x85,
2af1a29d 364 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 365 /* CR82 */
366 xgifb_reg_set(P3d4,
367 0x82,
2af1a29d 368 pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 369 break;
a24d60f4 370 }
a24d60f4 371
8104e329
AK		 372 xgifb_reg_set(P3d4, 0x97, 0x00);
373 xgifb_reg_set(P3d4, 0x98, 0x01);
374 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 375 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
376 }
377}
a24d60f4 378
b9ebf5e5
AK		 379static void XGINew_DDR2_DefaultRegister(
380 struct xgi_hw_device_info *HwDeviceExtension,
381 unsigned long Port, struct vb_device_info *pVBInfo)
382{
383 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 384
bf32fcb9
KT		 385 /* keep following setting sequence, each setting in
386 * the same reg insert idle */
8104e329
AK		 387 xgifb_reg_set(P3d4, 0x82, 0x77);
388 xgifb_reg_set(P3d4, 0x86, 0x00);
58839b01 389 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
8104e329 390 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 391 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
bf32fcb9 392 /* CR86 */
2af1a29d 393 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 394 xgifb_reg_set(P3d4, 0x82, 0x77);
395 xgifb_reg_set(P3d4, 0x85, 0x00);
58839b01 396 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
8104e329 397 xgifb_reg_set(P3d4, 0x85, 0x88);
58839b01 398 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
2af1a29d
AK		 399 xgifb_reg_set(P3d4,
400 0x85,
401 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
b9ebf5e5 402 if (HwDeviceExtension->jChipType == XG27)
bf32fcb9 403 /* CR82 */
2af1a29d 404 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 405 else
8104e329 406 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
a24d60f4 407
8104e329
AK		 408 xgifb_reg_set(P3d4, 0x98, 0x01);
409 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 410 if (HwDeviceExtension->jChipType == XG27)
411 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
412 else
413 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
414}
a24d60f4 415
b9ebf5e5
AK		 416static void XGINew_SetDRAMDefaultRegister340(
417 struct xgi_hw_device_info *HwDeviceExtension,
418 unsigned long Port, struct vb_device_info *pVBInfo)
419{
420 unsigned char temp, temp1, temp2, temp3, i, j, k;
a24d60f4 421
b9ebf5e5 422 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 423
2af1a29d
AK		 424 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
425 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
426 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
427 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
a24d60f4 428
b9ebf5e5
AK		 429 temp2 = 0;
430 for (i = 0; i < 4; i++) {
bf32fcb9 431 /* CR6B DQS fine tune delay */
2af1a29d 432 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
b9ebf5e5
AK		 433 for (j = 0; j < 4; j++) {
434 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
435 temp2 |= temp1;
8104e329 436 xgifb_reg_set(P3d4, 0x6B, temp2);
bf32fcb9
KT		 437 /* Insert read command for delay */
438 xgifb_reg_get(P3d4, 0x6B);
b9ebf5e5
AK		 439 temp2 &= 0xF0;
440 temp2 += 0x10;
441 }
a24d60f4 442 }
a24d60f4 443
b9ebf5e5
AK		 444 temp2 = 0;
445 for (i = 0; i < 4; i++) {
bf32fcb9 446 /* CR6E DQM fine tune delay */
2af1a29d 447 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
b9ebf5e5
AK		 448 for (j = 0; j < 4; j++) {
449 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
450 temp2 |= temp1;
8104e329 451 xgifb_reg_set(P3d4, 0x6E, temp2);
bf32fcb9
KT		 452 /* Insert read command for delay */
453 xgifb_reg_get(P3d4, 0x6E);
b9ebf5e5
AK		 454 temp2 &= 0xF0;
455 temp2 += 0x10;
a24d60f4 456 }
b9ebf5e5 457 }
a24d60f4 458
b9ebf5e5
AK		 459 temp3 = 0;
460 for (k = 0; k < 4; k++) {
bf32fcb9
KT		 461 /* CR6E_D[1:0] select channel */
462 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
b9ebf5e5
AK		 463 temp2 = 0;
464 for (i = 0; i < 8; i++) {
bf32fcb9 465 /* CR6F DQ fine tune delay */
2af1a29d 466 temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
b9ebf5e5
AK		 467 for (j = 0; j < 4; j++) {
468 temp1 = (temp >> (2 * j)) & 0x03;
469 temp2 |= temp1;
8104e329 470 xgifb_reg_set(P3d4, 0x6F, temp2);
bf32fcb9
KT		 471 /* Insert read command for delay */
472 xgifb_reg_get(P3d4, 0x6F);
b9ebf5e5
AK		 473 temp2 &= 0xF8;
474 temp2 += 0x08;
475 }
476 }
477 temp3 += 0x01;
478 }
a24d60f4 479
2af1a29d
AK		 480 xgifb_reg_set(P3d4,
481 0x80,
482 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
483 xgifb_reg_set(P3d4,
484 0x81,
485 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
a24d60f4 486
b9ebf5e5 487 temp2 = 0x80;
bf32fcb9 488 /* CR89 terminator type select */
2af1a29d 489 temp = pVBInfo->CR89[pVBInfo->ram_type][0];
b9ebf5e5
AK		 490 for (j = 0; j < 4; j++) {
491 temp1 = (temp >> (2 * j)) & 0x03;
492 temp2 |= temp1;
8104e329 493 xgifb_reg_set(P3d4, 0x89, temp2);
58839b01 494 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
b9ebf5e5
AK		 495 temp2 &= 0xF0;
496 temp2 += 0x10;
600a710b 497 }
a24d60f4 498
2af1a29d 499 temp = pVBInfo->CR89[pVBInfo->ram_type][1];
b9ebf5e5
AK		 500 temp1 = temp & 0x03;
501 temp2 |= temp1;
8104e329 502 xgifb_reg_set(P3d4, 0x89, temp2);
a24d60f4 503
2af1a29d 504 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
b9ebf5e5
AK		 505 temp1 = temp & 0x0F;
506 temp2 = (temp >> 4) & 0x07;
507 temp3 = temp & 0x80;
8104e329
AK		 508 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
509 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
b9bf6e4e 510 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
2af1a29d
AK		 511 xgifb_reg_set(P3d4,
512 0x41,
513 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
a24d60f4 514
b9ebf5e5 515 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 516 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
a24d60f4 517
bf32fcb9 518 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
8104e329 519 xgifb_reg_set(P3d4, (0x90 + j),
2af1a29d 520 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
a24d60f4 521
bf32fcb9 522 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
8104e329 523 xgifb_reg_set(P3d4, (0xC3 + j),
2af1a29d 524 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
a24d60f4 525
bf32fcb9 526 for (j = 0; j < 2; j++) /* CR8A - CR8B */
8104e329 527 xgifb_reg_set(P3d4, (0x8A + j),
2af1a29d 528 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
a24d60f4 529
18408da0 530 if (HwDeviceExtension->jChipType == XG42)
8104e329 531 xgifb_reg_set(P3d4, 0x8C, 0x87);
a24d60f4 532
2af1a29d
AK		 533 xgifb_reg_set(P3d4,
534 0x59,
535 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
a24d60f4 536
8104e329
AK		 537 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
538 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
6d12dae4 539 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
2af1a29d 540 if (pVBInfo->ram_type) {
8104e329 541 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
b9ebf5e5 542 if (HwDeviceExtension->jChipType == XG27)
8104e329 543 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
a24d60f4 544
b9ebf5e5 545 } else {
8104e329 546 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
b9ebf5e5 547 }
8104e329 548 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
a24d60f4 549
b9ebf5e5
AK		 550 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
551 if (temp == 0) {
552 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
553 } else {
8104e329 554 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
b9ebf5e5
AK		 555 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
556 }
2af1a29d
AK		 557 xgifb_reg_set(P3c4,
558 0x1B,
559 pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
b9ebf5e5 560}
a24d60f4 561
a24d60f4 562
d6461e49
PH		 563static unsigned short XGINew_SetDRAMSize20Reg(
564 unsigned short dram_size,
b9ebf5e5 565 struct vb_device_info *pVBInfo)
d7636e0b 566{
b9ebf5e5
AK		 567 unsigned short data = 0, memsize = 0;
568 int RankSize;
569 unsigned char ChannelNo;
d7636e0b 570
d6461e49 571 RankSize = dram_size * pVBInfo->ram_bus / 8;
58839b01 572 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
b9ebf5e5 573 data &= 0x80;
d7636e0b 574
b9ebf5e5
AK		 575 if (data == 0x80)
576 RankSize *= 2;
a24d60f4 577
b9ebf5e5 578 data = 0;
a24d60f4 579
ee055a48 580 if (pVBInfo->ram_channel == 3)
b9ebf5e5
AK		 581 ChannelNo = 4;
582 else
ee055a48 583 ChannelNo = pVBInfo->ram_channel;
a24d60f4 584
b9ebf5e5
AK		 585 if (ChannelNo * RankSize <= 256) {
586 while ((RankSize >>= 1) > 0)
587 data += 0x10;
a24d60f4 588
b9ebf5e5 589 memsize = data >> 4;
a24d60f4 590
949eb0ae 591 /* Fix DRAM Sizing Error */
bf32fcb9
KT		 592 xgifb_reg_set(pVBInfo->P3c4,
593 0x14,
594 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
595 (data & 0xF0));
c45715bb 596 udelay(15);
b9ebf5e5
AK		 597 }
598 return memsize;
599}
a24d60f4 600
b9ebf5e5
AK		 601static int XGINew_ReadWriteRest(unsigned short StopAddr,
602 unsigned short StartAddr, struct vb_device_info *pVBInfo)
603{
604 int i;
605 unsigned long Position = 0;
c44fa627 606 void __iomem *fbaddr = pVBInfo->FBAddr;
a24d60f4 607
c44fa627 608 writel(Position, fbaddr + Position);
a24d60f4 609
b9ebf5e5
AK		 610 for (i = StartAddr; i <= StopAddr; i++) {
611 Position = 1 << i;
c44fa627 612 writel(Position, fbaddr + Position);
b9ebf5e5 613 }
a24d60f4 614
949eb0ae 615 udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
a24d60f4 616
b9ebf5e5
AK		 617 Position = 0;
618
c44fa627 619 if (readl(fbaddr + Position) != Position)
b9ebf5e5 620 return 0;
d7636e0b 621
b9ebf5e5
AK		 622 for (i = StartAddr; i <= StopAddr; i++) {
623 Position = 1 << i;
c44fa627 624 if (readl(fbaddr + Position) != Position)
b9ebf5e5
AK		 625 return 0;
626 }
627 return 1;
d7636e0b 628}
a24d60f4 629
b9ebf5e5 630static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
d7636e0b 631{
b9ebf5e5 632 unsigned char data;
a24d60f4 633
58839b01 634 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
a24d60f4 635
b9ebf5e5 636 if ((data & 0x10) == 0) {
58839b01 637 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
b9ebf5e5
AK		 638 data = (data & 0x02) >> 1;
639 return data;
640 } else {
641 return data & 0x01;
642 }
643}
a24d60f4 644
b9ebf5e5
AK		 645static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
646 struct vb_device_info *pVBInfo)
647{
648 unsigned char data;
a24d60f4 649
b9ebf5e5
AK		 650 switch (HwDeviceExtension->jChipType) {
651 case XG20:
652 case XG21:
58839b01 653 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
b9ebf5e5 654 data = data & 0x01;
ee055a48 655 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
a24d60f4 656
b9ebf5e5 657 if (data == 0) { /* Single_32_16 */
a24d60f4 658
b9ebf5e5
AK		 659 if ((HwDeviceExtension->ulVideoMemorySize - 1)
660 > 0x1000000) {
a24d60f4 661
2f0f395e 662 pVBInfo->ram_bus = 32; /* 32 bits */
bf32fcb9
KT		 663 /* 22bit + 2 rank + 32bit */
664 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 665 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
c45715bb 666 udelay(15);
a24d60f4 667
b9ebf5e5
AK		 668 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
669 return;
d7636e0b 670
bf32fcb9
KT		 671 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
672 0x800000) {
673 /* 22bit + 1 rank + 32bit */
674 xgifb_reg_set(pVBInfo->P3c4,
675 0x13,
676 0x31);
677 xgifb_reg_set(pVBInfo->P3c4,
678 0x14,
679 0x42);
c45715bb 680 udelay(15);
a24d60f4 681
bf32fcb9
KT		 682 if (XGINew_ReadWriteRest(23,
683 23,
684 pVBInfo) == 1)
b9ebf5e5
AK		 685 return;
686 }
687 }
a24d60f4 688
bf32fcb9
KT		 689 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
690 0x800000) {
2f0f395e 691 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 692 /* 22bit + 2 rank + 16bit */
693 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 694 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
c45715bb 695 udelay(15);
a24d60f4 696
b9ebf5e5
AK		 697 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
698 return;
699 else
bf32fcb9
KT		 700 xgifb_reg_set(pVBInfo->P3c4,
701 0x13,
702 0x31);
c45715bb 703 udelay(15);
b9ebf5e5 704 }
a24d60f4 705
b9ebf5e5 706 } else { /* Dual_16_8 */
bf32fcb9
KT		 707 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
708 0x800000) {
2f0f395e 709 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 710 /* (0x31:12x8x2) 22bit + 2 rank */
711 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
712 /* 0x41:16Mx16 bit*/
713 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
c45715bb 714 udelay(15);
a24d60f4 715
b9ebf5e5
AK		 716 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
717 return;
a24d60f4 718
bf32fcb9
KT		 719 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
720 0x400000) {
721 /* (0x31:12x8x2) 22bit + 1 rank */
722 xgifb_reg_set(pVBInfo->P3c4,
723 0x13,
724 0x31);
725 /* 0x31:8Mx16 bit*/
726 xgifb_reg_set(pVBInfo->P3c4,
727 0x14,
728 0x31);
c45715bb 729 udelay(15);
a24d60f4 730
bf32fcb9
KT		 731 if (XGINew_ReadWriteRest(22,
732 22,
733 pVBInfo) == 1)
b9ebf5e5
AK		 734 return;
735 }
736 }
a24d60f4 737
bf32fcb9
KT		 738 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
739 0x400000) {
2f0f395e 740 pVBInfo->ram_bus = 8; /* 8 bits */
bf32fcb9
KT		 741 /* (0x31:12x8x2) 22bit + 2 rank */
742 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
743 /* 0x30:8Mx8 bit*/
744 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
c45715bb 745 udelay(15);
d7636e0b 746
b9ebf5e5
AK		 747 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
748 return;
bf32fcb9
KT		 749 else /* (0x31:12x8x2) 22bit + 1 rank */
750 xgifb_reg_set(pVBInfo->P3c4,
751 0x13,
752 0x31);
c45715bb 753 udelay(15);
a24d60f4
PS		 754 }
755 }
b9ebf5e5 756 break;
a24d60f4 757
b9ebf5e5 758 case XG27:
2f0f395e 759 pVBInfo->ram_bus = 16; /* 16 bits */
ee055a48 760 pVBInfo->ram_channel = 1; /* Single channel */
8104e329 761 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
b9ebf5e5 762 break;
b9ebf5e5
AK		 763 case XG42:
764 /*
765 XG42 SR14 D[3] Reserve
766 D[2] = 1, Dual Channel
767 = 0, Single Channel
a24d60f4 768
b9ebf5e5
AK		 769 It's Different from Other XG40 Series.
770 */
771 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
2f0f395e 772 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 773 pVBInfo->ram_channel = 2; /* 2 Channel */
8104e329
AK		 774 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
775 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
a24d60f4 776
b9ebf5e5
AK		 777 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
778 return;
a24d60f4 779
8104e329
AK		 780 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
781 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
b9ebf5e5
AK		 782 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
783 return;
a24d60f4 784
ee055a48 785 pVBInfo->ram_channel = 1; /* Single Channel */
8104e329
AK		 786 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
787 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
d7636e0b 788
b9ebf5e5
AK		 789 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
790 return;
791 else {
8104e329
AK		 792 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
793 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
b9ebf5e5
AK		 794 }
795 } else { /* DDR */
2f0f395e 796 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 797 pVBInfo->ram_channel = 1; /* 1 channels */
8104e329
AK		 798 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
799 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d7636e0b 800
b9ebf5e5
AK		 801 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
802 return;
803 else {
8104e329
AK		 804 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
805 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
b9ebf5e5
AK		 806 }
807 }
d7636e0b 808
b9ebf5e5 809 break;
d7636e0b 810
b9ebf5e5 811 default: /* XG40 */
d7636e0b 812
b9ebf5e5 813 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
2f0f395e 814 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 815 pVBInfo->ram_channel = 3;
8104e329
AK		 816 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
817 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
d7636e0b 818
b9ebf5e5
AK		 819 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
820 return;
d7636e0b 821
ee055a48 822 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 823 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
a24d60f4 824
b9ebf5e5
AK		 825 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
826 return;
d7636e0b 827
8104e329
AK		 828 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
829 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
d7636e0b 830
b9ebf5e5 831 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
ee055a48 832 pVBInfo->ram_channel = 3; /* 4 channels */
b9ebf5e5 833 } else {
ee055a48 834 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 835 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
b9ebf5e5
AK		 836 }
837 } else { /* DDR */
2f0f395e 838 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 839 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329
AK		 840 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
841 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
d7636e0b 842
b9ebf5e5
AK		 843 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
844 return;
845 } else {
8104e329
AK		 846 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
847 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
b9ebf5e5
AK		 848 }
849 }
850 break;
a24d60f4 851 }
d7636e0b 852}
853
b9ebf5e5
AK		 854static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
855 struct vb_device_info *pVBInfo)
d7636e0b 856{
672f5ee2
PH		 857 u8 i, size;
858 unsigned short memsize, start_addr;
d6461e49 859 const unsigned short (*dram_table)[2];
d7636e0b 860
8104e329
AK		 861 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
862 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
b9ebf5e5 863 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
d7636e0b 864
b9ebf5e5 865 if (HwDeviceExtension->jChipType >= XG20) {
672f5ee2
PH		 866 dram_table = XGINew_DDRDRAM_TYPE20;
867 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
868 start_addr = 5;
b9ebf5e5 869 } else {
672f5ee2
PH		 870 dram_table = XGINew_DDRDRAM_TYPE340;
871 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
872 start_addr = 9;
873 }
874
875 for (i = 0; i < size; i++) {
4e55d0b3 876 /* SetDRAMSizingType */
d6461e49 877 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
4e55d0b3
PH		 878 udelay(15); /* should delay 50 ns */
879
d6461e49 880 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
672f5ee2
PH		 881
882 if (memsize == 0)
883 continue;
884
885 memsize += (pVBInfo->ram_channel - 2) + 20;
886 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
887 (unsigned long) (1 << memsize))
888 continue;
889
890 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
891 return 1;
a24d60f4 892 }
b9ebf5e5 893 return 0;
a24d60f4 894}
d7636e0b 895
fab04b97
AK		 896static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
897 struct xgi_hw_device_info *HwDeviceExtension,
a24d60f4 898 struct vb_device_info *pVBInfo)
d7636e0b 899{
b9ebf5e5 900 unsigned short data;
a24d60f4 901
b9ebf5e5 902 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 903
fab04b97 904 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
a24d60f4 905
58839b01 906 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9
KT		 907 /* disable read cache */
908 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
fab04b97 909 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
a24d60f4 910
b9ebf5e5 911 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
58839b01 912 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9
KT		 913 /* enable read cache */
914 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
b9ebf5e5 915}
a24d60f4 916
08ce239c 917static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
02a81dd9
AK		 918{
919 void __iomem *rom_address;
82986dd9 920 u8 *rom_copy;
02a81dd9 921
08ce239c 922 rom_address = pci_map_rom(dev, rom_size);
02a81dd9
AK		 923 if (rom_address == NULL)
924 return NULL;
925
926 rom_copy = vzalloc(XGIFB_ROM_SIZE);
927 if (rom_copy == NULL)
928 goto done;
929
08ce239c
AK		 930 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
931 memcpy_fromio(rom_copy, rom_address, *rom_size);
02a81dd9
AK		 932
933done:
934 pci_unmap_rom(dev, rom_address);
935 return rom_copy;
936}
937
4e6f403a 938static void xgifb_read_vbios(struct pci_dev *pdev,
bf32fcb9 939 struct vb_device_info *pVBInfo)
b9ebf5e5 940{
02a81dd9 941 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
82986dd9 942 u8 *vbios;
b9ebf5e5 943 unsigned long i;
d1805b38 944 unsigned char j;
97f4532d 945 struct XGI21_LVDSCapStruct *lvds;
08ce239c 946 size_t vbios_size;
d1805b38 947 int entry;
a24d60f4 948
02a81dd9 949 if (xgifb_info->chip != XG21)
bd761274
AK		 950 return;
951 pVBInfo->IF_DEF_LVDS = 0;
08ce239c 952 vbios = xgifb_copy_rom(pdev, &vbios_size);
02a81dd9 953 if (vbios == NULL) {
be25aef0 954 dev_err(&pdev->dev, "Video BIOS not available\n");
bd761274 955 return;
02a81dd9 956 }
08ce239c
AK		 957 if (vbios_size <= 0x65)
958 goto error;
25aa75f1
AK		 959 /*
960 * The user can ignore the LVDS bit in the BIOS and force the display
961 * type.
962 */
963 if (!(vbios[0x65] & 0x1) &&
964 (!xgifb_info->display2_force ||
965 xgifb_info->display2 != XGIFB_DISP_LCD)) {
02a81dd9
AK		 966 vfree(vbios);
967 return;
968 }
08ce239c
AK		 969 if (vbios_size <= 0x317)
970 goto error;
4b21d990 971 i = vbios[0x316] | (vbios[0x317] << 8);
08ce239c
AK		 972 if (vbios_size <= i - 1)
973 goto error;
4b21d990 974 j = vbios[i - 1];
08ce239c
AK		 975 if (j == 0)
976 goto error;
bd761274
AK		 977 if (j == 0xff)
978 j = 1;
d1805b38
AK		 979 /*
980 * Read the LVDS table index scratch register set by the BIOS.
981 */
982 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
983 if (entry >= j)
984 entry = 0;
985 i += entry * 25;
fab04b97 986 lvds = &xgifb_info->lvds_data;
d1805b38
AK		 987 if (vbios_size <= i + 24)
988 goto error;
989 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
990 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
991 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
992 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
993 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
994 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
995 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
996 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
997 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
998 lvds->VCLKData1 = vbios[i + 18];
999 lvds->VCLKData2 = vbios[i + 19];
1000 lvds->PSC_S1 = vbios[i + 20];
1001 lvds->PSC_S2 = vbios[i + 21];
1002 lvds->PSC_S3 = vbios[i + 22];
1003 lvds->PSC_S4 = vbios[i + 23];
1004 lvds->PSC_S5 = vbios[i + 24];
02a81dd9 1005 vfree(vbios);
08ce239c
AK		 1006 pVBInfo->IF_DEF_LVDS = 1;
1007 return;
1008error:
be25aef0 1009 dev_err(&pdev->dev, "Video BIOS corrupted\n");
08ce239c 1010 vfree(vbios);
b9ebf5e5 1011}
a24d60f4 1012
b9ebf5e5
AK		 1013static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1014 struct vb_device_info *pVBInfo)
1015{
1016 unsigned short tempbx = 0, temp, tempcx, CR3CData;
a24d60f4 1017
58839b01 1018 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
a24d60f4 1019
b9ebf5e5
AK		 1020 if (temp & Monitor1Sense)
1021 tempbx |= ActiveCRT1;
1022 if (temp & LCDSense)
1023 tempbx |= ActiveLCD;
1024 if (temp & Monitor2Sense)
1025 tempbx |= ActiveCRT2;
1026 if (temp & TVSense) {
1027 tempbx |= ActiveTV;
1028 if (temp & AVIDEOSense)
1029 tempbx |= (ActiveAVideo << 8);
1030 if (temp & SVIDEOSense)
1031 tempbx |= (ActiveSVideo << 8);
1032 if (temp & SCARTSense)
1033 tempbx |= (ActiveSCART << 8);
1034 if (temp & HiTVSense)
1035 tempbx |= (ActiveHiTV << 8);
1036 if (temp & YPbPrSense)
1037 tempbx |= (ActiveYPbPr << 8);
1038 }
a24d60f4 1039
58839b01
AK		 1040 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1041 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
a24d60f4 1042
b9ebf5e5 1043 if (tempbx & tempcx) {
58839b01 1044 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
3bcc2460 1045 if (!(CR3CData & DisplayDeviceFromCMOS))
b9ebf5e5 1046 tempcx = 0x1FF0;
b9ebf5e5
AK		 1047 } else {
1048 tempcx = 0x1FF0;
b9ebf5e5 1049 }
a24d60f4 1050
b9ebf5e5 1051 tempbx &= tempcx;
8104e329
AK		 1052 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1053 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
b9ebf5e5 1054}
d7636e0b 1055
b9ebf5e5
AK		 1056static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1057 struct vb_device_info *pVBInfo)
1058{
1059 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
d7636e0b 1060
58839b01
AK		 1061 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1062 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1063 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
d7636e0b 1064
b9ebf5e5
AK		 1065 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1066 if (temp & ActiveCRT2)
1067 tempcl = SetCRT2ToRAMDAC;
1068 }
d7636e0b 1069
b9ebf5e5
AK		 1070 if (temp & ActiveLCD) {
1071 tempcl |= SetCRT2ToLCD;
1072 if (temp & DriverMode) {
1073 if (temp & ActiveTV) {
1074 tempch = SetToLCDA | EnableDualEdge;
1075 temp ^= SetCRT2ToLCD;
d7636e0b 1076
b9ebf5e5
AK		 1077 if ((temp >> 8) & ActiveAVideo)
1078 tempcl |= SetCRT2ToAVIDEO;
1079 if ((temp >> 8) & ActiveSVideo)
1080 tempcl |= SetCRT2ToSVIDEO;
1081 if ((temp >> 8) & ActiveSCART)
1082 tempcl |= SetCRT2ToSCART;
a24d60f4 1083
b9ebf5e5
AK		 1084 if (pVBInfo->IF_DEF_HiVision == 1) {
1085 if ((temp >> 8) & ActiveHiTV)
599801f9 1086 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1087 }
a24d60f4 1088
b9ebf5e5
AK		 1089 if (pVBInfo->IF_DEF_YPbPr == 1) {
1090 if ((temp >> 8) & ActiveYPbPr)
1091 tempch |= SetYPbPr;
1092 }
1093 }
1094 }
1095 } else {
1096 if ((temp >> 8) & ActiveAVideo)
1097 tempcl |= SetCRT2ToAVIDEO;
1098 if ((temp >> 8) & ActiveSVideo)
1099 tempcl |= SetCRT2ToSVIDEO;
1100 if ((temp >> 8) & ActiveSCART)
1101 tempcl |= SetCRT2ToSCART;
a24d60f4 1102
b9ebf5e5
AK		 1103 if (pVBInfo->IF_DEF_HiVision == 1) {
1104 if ((temp >> 8) & ActiveHiTV)
599801f9 1105 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1106 }
a24d60f4 1107
b9ebf5e5
AK		 1108 if (pVBInfo->IF_DEF_YPbPr == 1) {
1109 if ((temp >> 8) & ActiveYPbPr)
1110 tempch |= SetYPbPr;
1111 }
1112 }
d7636e0b 1113
b9ebf5e5
AK		 1114 tempcl |= SetSimuScanMode;
1115 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1116 || (temp & ActiveCRT2)))
6896b94e 1117 tempcl ^= (SetSimuScanMode | SwitchCRT2);
b9ebf5e5 1118 if ((temp & ActiveLCD) && (temp & ActiveTV))
6896b94e 1119 tempcl ^= (SetSimuScanMode | SwitchCRT2);
8104e329 1120 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
d7636e0b 1121
58839b01 1122 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
b9ebf5e5
AK		 1123 CR31Data &= ~(SetNotSimuMode >> 8);
1124 if (!(temp & ActiveCRT1))
1125 CR31Data |= (SetNotSimuMode >> 8);
1126 CR31Data &= ~(DisableCRT2Display >> 8);
1127 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1128 CR31Data |= (DisableCRT2Display >> 8);
8104e329 1129 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
d7636e0b 1130
58839b01 1131 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1132 CR38Data &= ~SetYPbPr;
1133 CR38Data |= tempch;
8104e329 1134 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
d7636e0b 1135
b9ebf5e5 1136}
a24d60f4 1137
40544b04
AK		 1138static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1139 *HwDeviceExtension,
1140 struct vb_device_info *pVBInfo)
1141{
1142 unsigned short temp;
1143
1144 /* add lcd sense */
1145 if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1146 return 0;
1147 } else {
1148 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1149 switch (HwDeviceExtension->ulCRT2LCDType) {
1150 case LCD_INVALID:
1151 case LCD_800x600:
1152 case LCD_1024x768:
1153 case LCD_1280x1024:
1154 break;
1155
1156 case LCD_640x480:
1157 case LCD_1024x600:
1158 case LCD_1152x864:
1159 case LCD_1280x960:
1160 case LCD_1152x768:
1161 temp = 0;
1162 break;
1163
1164 case LCD_1400x1050:
1165 case LCD_1280x768:
1166 case LCD_1600x1200:
1167 break;
1168
1169 case LCD_1920x1440:
1170 case LCD_2048x1536:
1171 temp = 0;
1172 break;
1173
1174 default:
1175 break;
1176 }
1177 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1178 return 1;
1179 }
1180}
1181
b9ebf5e5
AK		 1182static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1183 struct vb_device_info *pVBInfo)
1184{
1185 unsigned char Temp;
a24d60f4 1186
c4ffaa44 1187 if (pVBInfo->IF_DEF_LVDS) { /* For XG21 LVDS */
b9bf6e4e 1188 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1189 /* LVDS on chip */
1190 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
b9ebf5e5 1191 } else {
bf32fcb9
KT		 1192 /* Enable GPIOA/B read */
1193 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1194 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
b9ebf5e5
AK		 1195 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1196 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
b9bf6e4e 1197 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1198 /* Enable read GPIOF */
1199 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
58839b01 1200 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
b9ebf5e5 1201 if (!Temp)
bf32fcb9
KT		 1202 xgifb_reg_and_or(pVBInfo->P3d4,
1203 0x38,
1204 ~0xE0,
1205 0x80); /* TMDS on chip */
a24d60f4 1206 else
bf32fcb9
KT		 1207 xgifb_reg_and_or(pVBInfo->P3d4,
1208 0x38,
1209 ~0xE0,
1210 0xA0); /* Only DVO on chip */
1211 /* Disable read GPIOF */
1212 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
a24d60f4 1213 }
b9ebf5e5 1214 }
b9ebf5e5 1215}
a24d60f4 1216
b9ebf5e5
AK		 1217static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1218 struct vb_device_info *pVBInfo)
1219{
1220 unsigned char Temp, bCR4A;
a24d60f4 1221
b9ebf5e5 1222 pVBInfo->IF_DEF_LVDS = 0;
58839b01 1223 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1224 /* Enable GPIOA/B/C read */
1225 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
58839b01 1226 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
8104e329 1227 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
a24d60f4 1228
b9ebf5e5 1229 if (Temp <= 0x02) {
bf32fcb9
KT		 1230 /* LVDS setting */
1231 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
8104e329 1232 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
b9ebf5e5 1233 } else {
bf32fcb9
KT		 1234 /* TMDS/DVO setting */
1235 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
b9ebf5e5 1236 }
b9bf6e4e 1237 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
a24d60f4 1238
b9ebf5e5 1239}
a24d60f4 1240
b9ebf5e5
AK		 1241static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1242{
1243 unsigned char CR38, CR4A, temp;
a24d60f4 1244
58839b01 1245 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1246 /* enable GPIOE read */
1247 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
58839b01 1248 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1249 temp = 0;
1250 if ((CR38 & 0xE0) > 0x80) {
58839b01 1251 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1252 temp &= 0x08;
1253 temp >>= 3;
1254 }
a24d60f4 1255
8104e329 1256 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1257
b9ebf5e5
AK		 1258 return temp;
1259}
a24d60f4 1260
b9ebf5e5
AK		 1261static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1262{
1263 unsigned char CR4A, temp;
a24d60f4 1264
58839b01 1265 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1266 /* enable GPIOA/B/C read */
1267 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1268 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1269 if (temp <= 2)
1270 temp &= 0x03;
1271 else
2f123cbc 1272 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
a24d60f4 1273
8104e329 1274 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1275
b9ebf5e5
AK		 1276 return temp;
1277}
a24d60f4 1278
6048d761 1279unsigned char XGIInitNew(struct pci_dev *pdev)
b9ebf5e5 1280{
ab886ff8 1281 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
6048d761 1282 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
b9ebf5e5
AK		 1283 struct vb_device_info VBINF;
1284 struct vb_device_info *pVBInfo = &VBINF;
1285 unsigned char i, temp = 0, temp1;
a24d60f4 1286
b9ebf5e5 1287 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 1288
9a801f25 1289 pVBInfo->BaseAddr = xgifb_info->vga_base;
a24d60f4 1290
b9ebf5e5 1291 if (pVBInfo->FBAddr == NULL) {
19185703 1292 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
b9ebf5e5
AK		 1293 return 0;
1294 }
b9ebf5e5 1295 if (pVBInfo->BaseAddr == 0) {
19185703 1296 dev_dbg(&pdev->dev, "pVBInfo->BaseAddr == 0\n");
b9ebf5e5
AK		 1297 return 0;
1298 }
a24d60f4 1299
efdf4ee7 1300 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
a24d60f4 1301
b9ebf5e5
AK		 1302 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1303 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1304 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1305 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1306 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1307 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1308 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1309 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1310 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1311 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1312 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1313 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
6896b94e
PH		 1314 pVBInfo->Part1Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_04;
1315 pVBInfo->Part2Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_10;
1316 pVBInfo->Part3Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_12;
1317 pVBInfo->Part4Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_14;
1318 pVBInfo->Part5Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_14 + 2;
d7636e0b 1319
949eb0ae 1320 if (HwDeviceExtension->jChipType < XG20)
bf32fcb9
KT		 1321 /* Run XGI_GetVBType before InitTo330Pointer */
1322 XGI_GetVBType(pVBInfo);
a24d60f4 1323
b9ebf5e5
AK		 1324 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1325
4e6f403a 1326 xgifb_read_vbios(pdev, pVBInfo);
b9ebf5e5 1327
949eb0ae 1328 /* Openkey */
8104e329 1329 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
b9ebf5e5
AK		 1330
1331 /* GetXG21Sense (GPIO) */
1332 if (HwDeviceExtension->jChipType == XG21)
1333 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1334
1335 if (HwDeviceExtension->jChipType == XG27)
1336 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1337
949eb0ae 1338 /* Reset Extended register */
b9ebf5e5
AK		 1339
1340 for (i = 0x06; i < 0x20; i++)
8104e329 1341 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5
AK		 1342
1343 for (i = 0x21; i <= 0x27; i++)
8104e329 1344 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5 1345
06587335 1346 for (i = 0x31; i <= 0x3B; i++)
8104e329 1347 xgifb_reg_set(pVBInfo->P3c4, i, 0);
d7636e0b 1348
949eb0ae 1349 /* Auto over driver for XG42 */
bf32fcb9 1350 if (HwDeviceExtension->jChipType == XG42)
8104e329 1351 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
d7636e0b 1352
b9ebf5e5 1353 for (i = 0x79; i <= 0x7C; i++)
949eb0ae 1354 xgifb_reg_set(pVBInfo->P3d4, i, 0);
d7636e0b 1355
b9ebf5e5 1356 if (HwDeviceExtension->jChipType >= XG20)
6d12dae4 1357 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
a24d60f4 1358
949eb0ae 1359 /* SetDefExt1Regs begin */
6d12dae4 1360 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
b9ebf5e5 1361 if (HwDeviceExtension->jChipType == XG27) {
6d12dae4
PH		 1362 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1363 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
a24d60f4 1364 }
8104e329 1365 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
6d12dae4 1366 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
949eb0ae 1367 /* Frame buffer can read/write SR20 */
bf32fcb9 1368 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
949eb0ae 1369 /* H/W request for slow corner chip */
bf32fcb9 1370 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
949eb0ae 1371 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 1372 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
a24d60f4 1373
949eb0ae 1374 if (HwDeviceExtension->jChipType < XG20) {
6048d761
AK		 1375 u32 Temp;
1376
06587335
AK		 1377 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1378 for (i = 0x47; i <= 0x4C; i++)
bf32fcb9
KT		 1379 xgifb_reg_set(pVBInfo->P3d4,
1380 i,
1381 pVBInfo->AGPReg[i - 0x47]);
06587335
AK		 1382
1383 for (i = 0x70; i <= 0x71; i++)
bf32fcb9
KT		 1384 xgifb_reg_set(pVBInfo->P3d4,
1385 i,
1386 pVBInfo->AGPReg[6 + i - 0x70]);
06587335
AK		 1387
1388 for (i = 0x74; i <= 0x77; i++)
bf32fcb9
KT		 1389 xgifb_reg_set(pVBInfo->P3d4,
1390 i,
1391 pVBInfo->AGPReg[8 + i - 0x74]);
06587335 1392
6048d761 1393 pci_read_config_dword(pdev, 0x50, &Temp);
06587335
AK		 1394 Temp >>= 20;
1395 Temp &= 0xF;
1396
1397 if (Temp == 1)
8104e329 1398 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
b9ebf5e5 1399 } /* != XG20 */
a24d60f4 1400
b9ebf5e5 1401 /* Set PCI */
6d12dae4
PH		 1402 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1403 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1404 xgifb_reg_set(pVBInfo->P3c4, 0x25, XGI330_SR25);
a24d60f4 1405
949eb0ae 1406 if (HwDeviceExtension->jChipType < XG20) {
b9ebf5e5
AK		 1407 /* Set VB */
1408 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
949eb0ae 1409 /* disable VideoCapture */
bf32fcb9 1410 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
8104e329 1411 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
bf32fcb9
KT		 1412 /* chk if BCLK>=100MHz */
1413 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
b9ebf5e5 1414 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
a24d60f4 1415
bf32fcb9 1416 xgifb_reg_set(pVBInfo->Part1Port,
6d12dae4 1417 0x02, XGI330_CRT2Data_1_2);
a24d60f4 1418
8104e329 1419 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
b9ebf5e5 1420 } /* != XG20 */
a24d60f4 1421
8104e329 1422 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
b9ebf5e5 1423
bf32fcb9
KT		 1424 if ((HwDeviceExtension->jChipType == XG42) &&
1425 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1426 /* Not DDR */
1427 xgifb_reg_set(pVBInfo->P3c4,
1428 0x31,
6d12dae4 1429 (XGI330_SR31 & 0x3F) | 0x40);
bf32fcb9
KT		 1430 xgifb_reg_set(pVBInfo->P3c4,
1431 0x32,
6d12dae4 1432 (XGI330_SR32 & 0xFC) | 0x01);
a24d60f4 1433 } else {
6d12dae4
PH		 1434 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1435 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
b9ebf5e5 1436 }
6d12dae4 1437 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
a24d60f4 1438
949eb0ae 1439 if (HwDeviceExtension->jChipType < XG20) {
b9ebf5e5
AK		 1440 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1441 if (pVBInfo->IF_DEF_LVDS == 0) {
8104e329 1442 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
bf32fcb9 1443 xgifb_reg_set(pVBInfo->Part4Port,
6d12dae4 1444 0x0D, XGI330_CRT2Data_4_D);
bf32fcb9 1445 xgifb_reg_set(pVBInfo->Part4Port,
6d12dae4 1446 0x0E, XGI330_CRT2Data_4_E);
bf32fcb9 1447 xgifb_reg_set(pVBInfo->Part4Port,
6d12dae4 1448 0x10, XGI330_CRT2Data_4_10);
8104e329 1449 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
b9ebf5e5
AK		 1450 }
1451
1452 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
a24d60f4 1453 }
b9ebf5e5 1454 } /* != XG20 */
a24d60f4 1455
b9ebf5e5 1456 XGI_SenseCRT1(pVBInfo);
d7636e0b 1457
b9ebf5e5 1458 if (HwDeviceExtension->jChipType == XG21) {
d7636e0b 1459
bf32fcb9
KT		 1460 xgifb_reg_and_or(pVBInfo->P3d4,
1461 0x32,
1462 ~Monitor1Sense,
1463 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1464 temp = GetXG21FPBits(pVBInfo);
ec9e5d3e 1465 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
d7636e0b 1466
a24d60f4 1467 }
b9ebf5e5 1468 if (HwDeviceExtension->jChipType == XG27) {
bf32fcb9
KT		 1469 xgifb_reg_and_or(pVBInfo->P3d4,
1470 0x32,
1471 ~Monitor1Sense,
1472 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1473 temp = GetXG27FPBits(pVBInfo);
ec9e5d3e 1474 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
b9ebf5e5 1475 }
d7636e0b 1476
2af1a29d 1477 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
d7636e0b 1478
bf32fcb9
KT		 1479 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1480 pVBInfo->P3d4,
1481 pVBInfo);
a24d60f4 1482
fab04b97 1483 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
d7636e0b 1484
bf32fcb9
KT		 1485 xgifb_reg_set(pVBInfo->P3c4,
1486 0x22,
6d12dae4 1487 (unsigned char) ((pVBInfo->SR22) & 0xFE));
d7636e0b 1488
6d12dae4 1489 xgifb_reg_set(pVBInfo->P3c4, 0x21, pVBInfo->SR21);
d7636e0b 1490
b9ebf5e5
AK		 1491 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1492 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
a24d60f4 1493
8104e329 1494 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
d7636e0b 1495
b9ebf5e5
AK		 1496 return 1;
1497} /* end of init */
kernel source for telekom puls (alcatel/mediatek)