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80aba536 PE |
1 | #ifndef __WINBOND_WBHAL_S_H |
2 | #define __WINBOND_WBHAL_S_H | |
3 | ||
4 | #include <linux/types.h> | |
bd37b7fd | 5 | #include <linux/if_ether.h> /* for ETH_ALEN */ |
80aba536 | 6 | |
5a7df3c4 LL |
7 | #define HAL_LED_SET_MASK 0x001c |
8 | #define HAL_LED_SET_SHIFT 2 | |
66101de1 | 9 | |
5a7df3c4 | 10 | /* supported RF type */ |
66101de1 PM |
11 | #define RF_MAXIM_2825 0 |
12 | #define RF_MAXIM_2827 1 | |
13 | #define RF_MAXIM_2828 2 | |
14 | #define RF_MAXIM_2829 3 | |
5a7df3c4 | 15 | #define RF_MAXIM_V1 15 |
66101de1 PM |
16 | #define RF_AIROHA_2230 16 |
17 | #define RF_AIROHA_7230 17 | |
5a7df3c4 LL |
18 | #define RF_AIROHA_2230S 18 |
19 | #define RF_WB_242 33 | |
20 | #define RF_WB_242_1 34 | |
66101de1 PM |
21 | #define RF_DECIDE_BY_INF 255 |
22 | ||
5a7df3c4 LL |
23 | /* |
24 | * ---------------------------------------------------------------- | |
25 | * The follow define connect to upper layer | |
26 | * User must modify for connection between HAL and upper layer | |
27 | * ---------------------------------------------------------------- | |
28 | */ | |
29 | ||
30 | /* | |
31 | * ============================== | |
32 | * Common define | |
33 | * ============================== | |
34 | */ | |
35 | /* Bit 5 */ | |
36 | #define HAL_USB_MODE_BURST(_H) (_H->SoftwareSet & 0x20) | |
37 | ||
38 | /* Scan interval */ | |
39 | #define SCAN_MAX_CHNL_TIME (50) | |
40 | ||
41 | /* For TxL2 Frame typr recognise */ | |
66101de1 PM |
42 | #define FRAME_TYPE_802_3_DATA 0 |
43 | #define FRAME_TYPE_802_11_MANAGEMENT 1 | |
5a7df3c4 | 44 | #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2 |
66101de1 PM |
45 | #define FRAME_TYPE_802_11_CONTROL 3 |
46 | #define FRAME_TYPE_802_11_DATA 4 | |
47 | #define FRAME_TYPE_PROMISCUOUS 5 | |
48 | ||
5a7df3c4 LL |
49 | /* The follow definition is used for convert the frame------------ */ |
50 | #define DOT_11_SEQUENCE_OFFSET 22 /* Sequence control offset */ | |
66101de1 | 51 | #define DOT_3_TYPE_OFFSET 12 |
5a7df3c4 | 52 | #define DOT_11_MAC_HEADER_SIZE 24 |
66101de1 | 53 | #define DOT_11_SNAP_SIZE 6 |
5a7df3c4 | 54 | #define DOT_11_TYPE_OFFSET 30 /* The start offset of 802.11 Frame. Type encapsulation. */ |
66101de1 | 55 | #define DEFAULT_SIFSTIME 10 |
5a7df3c4 | 56 | #define DEFAULT_FRAGMENT_THRESHOLD 2346 /* No fragment */ |
66101de1 PM |
57 | #define DEFAULT_MSDU_LIFE_TIME 0xffff |
58 | ||
5a7df3c4 LL |
59 | #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144 + 48) |
60 | #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72 + 24) | |
61 | #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16 + 4 + 6) | |
62 | #define Tsym 4 | |
66101de1 | 63 | |
5a7df3c4 | 64 | /* Frame Type of Bits (2, 3)----------------------------------- */ |
66101de1 PM |
65 | #define MAC_TYPE_MANAGEMENT 0x00 |
66 | #define MAC_TYPE_CONTROL 0x04 | |
67 | #define MAC_TYPE_DATA 0x08 | |
5a7df3c4 LL |
68 | #define MASK_FRAGMENT_NUMBER 0x000F |
69 | #define SEQUENCE_NUMBER_SHIFT 4 | |
66101de1 PM |
70 | |
71 | #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01 | |
72 | #define HAL_WOL_TYPE_MAGIC_PACKET 0x02 | |
73 | ||
5a7df3c4 LL |
74 | #define HAL_KEYTYPE_WEP40 0 |
75 | #define HAL_KEYTYPE_WEP104 1 | |
76 | #define HAL_KEYTYPE_TKIP 2 /* 128 bit key */ | |
77 | #define HAL_KEYTYPE_AES_CCMP 3 /* 128 bit key */ | |
66101de1 | 78 | |
5a7df3c4 | 79 | /* For VM state */ |
66101de1 PM |
80 | enum { |
81 | VM_STOP = 0, | |
82 | VM_RUNNING, | |
83 | VM_COMPLETED | |
84 | }; | |
85 | ||
5a7df3c4 LL |
86 | /* |
87 | * ================================ | |
88 | * Normal Key table format | |
89 | * ================================ | |
90 | */ | |
91 | ||
92 | /* The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX */ | |
93 | #define MAX_KEY_TABLE 24 /* 24 entry for storing key data */ | |
66101de1 PM |
94 | #define GROUP_KEY_START_INDEX 4 |
95 | #define MAPPING_KEY_START_INDEX 8 | |
66101de1 | 96 | |
5a7df3c4 LL |
97 | /* |
98 | * ========================================= | |
99 | * Descriptor | |
100 | * ========================================= | |
101 | */ | |
102 | #define MAX_DESCRIPTOR_BUFFER_INDEX 8 /* Have to multiple of 2 */ | |
103 | #define FLAG_ERROR_TX_MASK 0x000000bf | |
104 | #define FLAG_ERROR_RX_MASK 0x0000083f | |
105 | ||
106 | #define FLAG_BAND_RX_MASK 0x10000000 /* Bit 28 */ | |
107 | ||
108 | typedef struct _R00_DESCRIPTOR { | |
109 | union { | |
66101de1 | 110 | u32 value; |
5a7df3c4 LL |
111 | #ifdef _BIG_ENDIAN_ |
112 | struct { | |
66101de1 PM |
113 | u32 R00_packet_or_buffer_status:1; |
114 | u32 R00_packet_in_fifo:1; | |
115 | u32 R00_RESERVED:2; | |
116 | u32 R00_receive_byte_count:12; | |
117 | u32 R00_receive_time_index:16; | |
118 | }; | |
5a7df3c4 LL |
119 | #else |
120 | struct { | |
66101de1 PM |
121 | u32 R00_receive_time_index:16; |
122 | u32 R00_receive_byte_count:12; | |
123 | u32 R00_RESERVED:2; | |
124 | u32 R00_packet_in_fifo:1; | |
125 | u32 R00_packet_or_buffer_status:1; | |
126 | }; | |
5a7df3c4 | 127 | #endif |
66101de1 PM |
128 | }; |
129 | } R00_DESCRIPTOR, *PR00_DESCRIPTOR; | |
130 | ||
5a7df3c4 LL |
131 | typedef struct _T00_DESCRIPTOR { |
132 | union { | |
66101de1 | 133 | u32 value; |
5a7df3c4 LL |
134 | #ifdef _BIG_ENDIAN_ |
135 | struct { | |
136 | u32 T00_first_mpdu:1; /* for hardware use */ | |
137 | u32 T00_last_mpdu:1; /* for hardware use */ | |
138 | u32 T00_IsLastMpdu:1;/* 0:not 1:Yes for software used */ | |
139 | u32 T00_IgnoreResult:1;/* The same mechanism with T00 setting. */ | |
140 | u32 T00_RESERVED_ID:2;/* 3 bit ID reserved */ | |
141 | u32 T00_tx_packet_id:4; | |
66101de1 PM |
142 | u32 T00_RESERVED:4; |
143 | u32 T00_header_length:6; | |
144 | u32 T00_frame_length:12; | |
145 | }; | |
5a7df3c4 LL |
146 | #else |
147 | struct { | |
66101de1 PM |
148 | u32 T00_frame_length:12; |
149 | u32 T00_header_length:6; | |
150 | u32 T00_RESERVED:4; | |
5a7df3c4 LL |
151 | u32 T00_tx_packet_id:4; |
152 | u32 T00_RESERVED_ID:2; /* 3 bit ID reserved */ | |
153 | u32 T00_IgnoreResult:1; /* The same mechanism with T00 setting. */ | |
154 | u32 T00_IsLastMpdu:1; /* 0:not 1:Yes for software used */ | |
155 | u32 T00_last_mpdu:1; /* for hardware use */ | |
156 | u32 T00_first_mpdu:1; /* for hardware use */ | |
66101de1 | 157 | }; |
5a7df3c4 | 158 | #endif |
66101de1 PM |
159 | }; |
160 | } T00_DESCRIPTOR, *PT00_DESCRIPTOR; | |
161 | ||
5a7df3c4 LL |
162 | typedef struct _R01_DESCRIPTOR { |
163 | union { | |
66101de1 | 164 | u32 value; |
5a7df3c4 LL |
165 | #ifdef _BIG_ENDIAN_ |
166 | struct { | |
66101de1 PM |
167 | u32 R01_RESERVED:3; |
168 | u32 R01_mod_type:1; | |
169 | u32 R01_pre_type:1; | |
170 | u32 R01_data_rate:3; | |
171 | u32 R01_AGC_state:8; | |
172 | u32 R01_LNA_state:2; | |
173 | u32 R01_decryption_method:2; | |
174 | u32 R01_mic_error:1; | |
175 | u32 R01_replay:1; | |
176 | u32 R01_broadcast_frame:1; | |
177 | u32 R01_multicast_frame:1; | |
178 | u32 R01_directed_frame:1; | |
179 | u32 R01_receive_frame_antenna_selection:1; | |
180 | u32 R01_frame_receive_during_atim_window:1; | |
181 | u32 R01_protocol_version_error:1; | |
182 | u32 R01_authentication_frame_icv_error:1; | |
183 | u32 R01_null_key_to_authentication_frame:1; | |
184 | u32 R01_icv_error:1; | |
185 | u32 R01_crc_error:1; | |
186 | }; | |
5a7df3c4 LL |
187 | #else |
188 | struct { | |
66101de1 PM |
189 | u32 R01_crc_error:1; |
190 | u32 R01_icv_error:1; | |
191 | u32 R01_null_key_to_authentication_frame:1; | |
192 | u32 R01_authentication_frame_icv_error:1; | |
193 | u32 R01_protocol_version_error:1; | |
194 | u32 R01_frame_receive_during_atim_window:1; | |
195 | u32 R01_receive_frame_antenna_selection:1; | |
196 | u32 R01_directed_frame:1; | |
197 | u32 R01_multicast_frame:1; | |
198 | u32 R01_broadcast_frame:1; | |
199 | u32 R01_replay:1; | |
200 | u32 R01_mic_error:1; | |
201 | u32 R01_decryption_method:2; | |
202 | u32 R01_LNA_state:2; | |
203 | u32 R01_AGC_state:8; | |
204 | u32 R01_data_rate:3; | |
205 | u32 R01_pre_type:1; | |
206 | u32 R01_mod_type:1; | |
207 | u32 R01_RESERVED:3; | |
208 | }; | |
5a7df3c4 | 209 | #endif |
66101de1 PM |
210 | }; |
211 | } R01_DESCRIPTOR, *PR01_DESCRIPTOR; | |
212 | ||
5a7df3c4 LL |
213 | typedef struct _T01_DESCRIPTOR { |
214 | union { | |
66101de1 | 215 | u32 value; |
5a7df3c4 LL |
216 | #ifdef _BIG_ENDIAN_ |
217 | struct { | |
66101de1 PM |
218 | u32 T01_rts_cts_duration:16; |
219 | u32 T01_fall_back_rate:3; | |
220 | u32 T01_add_rts:1; | |
221 | u32 T01_add_cts:1; | |
222 | u32 T01_modulation_type:1; | |
223 | u32 T01_plcp_header_length:1; | |
224 | u32 T01_transmit_rate:3; | |
225 | u32 T01_wep_id:2; | |
226 | u32 T01_add_challenge_text:1; | |
227 | u32 T01_inhibit_crc:1; | |
228 | u32 T01_loop_back_wep_mode:1; | |
229 | u32 T01_retry_abort_ebable:1; | |
230 | }; | |
5a7df3c4 LL |
231 | #else |
232 | struct { | |
66101de1 PM |
233 | u32 T01_retry_abort_ebable:1; |
234 | u32 T01_loop_back_wep_mode:1; | |
235 | u32 T01_inhibit_crc:1; | |
236 | u32 T01_add_challenge_text:1; | |
237 | u32 T01_wep_id:2; | |
238 | u32 T01_transmit_rate:3; | |
239 | u32 T01_plcp_header_length:1; | |
240 | u32 T01_modulation_type:1; | |
241 | u32 T01_add_cts:1; | |
242 | u32 T01_add_rts:1; | |
243 | u32 T01_fall_back_rate:3; | |
244 | u32 T01_rts_cts_duration:16; | |
245 | }; | |
5a7df3c4 | 246 | #endif |
66101de1 PM |
247 | }; |
248 | } T01_DESCRIPTOR, *PT01_DESCRIPTOR; | |
249 | ||
5a7df3c4 LL |
250 | typedef struct _T02_DESCRIPTOR { |
251 | union { | |
66101de1 | 252 | u32 value; |
5a7df3c4 LL |
253 | #ifdef _BIG_ENDIAN_ |
254 | struct { | |
255 | u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */ | |
256 | u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */ | |
257 | u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */ | |
66101de1 PM |
258 | u32 T02_Tx_PktID:4; |
259 | u32 T02_MPDU_Cnt:4; | |
260 | u32 T02_RTS_Cnt:4; | |
261 | u32 T02_RESERVED:7; | |
262 | u32 T02_transmit_complete:1; | |
263 | u32 T02_transmit_abort_due_to_TBTT:1; | |
264 | u32 T02_effective_transmission_rate:1; | |
265 | u32 T02_transmit_without_encryption_due_to_wep_on_false:1; | |
266 | u32 T02_discard_due_to_null_wep_key:1; | |
267 | u32 T02_RESERVED_1:1; | |
268 | u32 T02_out_of_MaxTxMSDULiftTime:1; | |
269 | u32 T02_transmit_abort:1; | |
270 | u32 T02_transmit_fail:1; | |
271 | }; | |
5a7df3c4 LL |
272 | #else |
273 | struct { | |
66101de1 PM |
274 | u32 T02_transmit_fail:1; |
275 | u32 T02_transmit_abort:1; | |
276 | u32 T02_out_of_MaxTxMSDULiftTime:1; | |
277 | u32 T02_RESERVED_1:1; | |
278 | u32 T02_discard_due_to_null_wep_key:1; | |
279 | u32 T02_transmit_without_encryption_due_to_wep_on_false:1; | |
280 | u32 T02_effective_transmission_rate:1; | |
281 | u32 T02_transmit_abort_due_to_TBTT:1; | |
282 | u32 T02_transmit_complete:1; | |
283 | u32 T02_RESERVED:7; | |
284 | u32 T02_RTS_Cnt:4; | |
285 | u32 T02_MPDU_Cnt:4; | |
286 | u32 T02_Tx_PktID:4; | |
5a7df3c4 LL |
287 | u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */ |
288 | u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */ | |
289 | u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */ | |
66101de1 | 290 | }; |
5a7df3c4 | 291 | #endif |
66101de1 PM |
292 | }; |
293 | } T02_DESCRIPTOR, *PT02_DESCRIPTOR; | |
294 | ||
5a7df3c4 LL |
295 | struct wb35_descriptor { /* Skip length = 8 DWORD */ |
296 | /* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */ | |
66101de1 | 297 | u8 Descriptor_ID; |
5a7df3c4 | 298 | /* ----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ */ |
66101de1 PM |
299 | u8 RESERVED[3]; |
300 | ||
301 | u16 FragmentThreshold; | |
5a7df3c4 LL |
302 | u8 InternalUsed; /* Only can be used by operation of descriptor definition */ |
303 | u8 Type; /* 0: 802.3 1:802.11 data frame 2:802.11 management frame */ | |
66101de1 | 304 | |
5a7df3c4 | 305 | u8 PreambleMode;/* 0: short 1:long */ |
66101de1 PM |
306 | u8 TxRate; |
307 | u8 FragmentCount; | |
5a7df3c4 | 308 | u8 EapFix; /* For speed up key install */ |
66101de1 | 309 | |
5a7df3c4 LL |
310 | /* For R00 and T00 ------------------------------ */ |
311 | union { | |
66101de1 PM |
312 | R00_DESCRIPTOR R00; |
313 | T00_DESCRIPTOR T00; | |
314 | }; | |
315 | ||
5a7df3c4 LL |
316 | /* For R01 and T01 ------------------------------ */ |
317 | union { | |
66101de1 PM |
318 | R01_DESCRIPTOR R01; |
319 | T01_DESCRIPTOR T01; | |
320 | }; | |
321 | ||
5a7df3c4 LL |
322 | /* For R02 and T02 ------------------------------ */ |
323 | union { | |
324 | u32 R02; | |
66101de1 PM |
325 | T02_DESCRIPTOR T02; |
326 | }; | |
327 | ||
5a7df3c4 LL |
328 | /* For R03 and T03 ------------------------------ */ |
329 | /* For software used */ | |
330 | union { | |
66101de1 PM |
331 | u32 R03; |
332 | u32 T03; | |
5a7df3c4 | 333 | struct { |
66101de1 PM |
334 | u8 buffer_number; |
335 | u8 buffer_start_index; | |
336 | u16 buffer_total_size; | |
337 | }; | |
338 | }; | |
339 | ||
5a7df3c4 LL |
340 | /* For storing the buffer */ |
341 | u16 buffer_size[MAX_DESCRIPTOR_BUFFER_INDEX]; | |
342 | void *buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX]; | |
27d46421 | 343 | }; |
66101de1 PM |
344 | |
345 | ||
5a7df3c4 | 346 | #define DEFAULT_NULL_PACKET_COUNT 180000 /* 180 seconds */ |
66101de1 | 347 | |
5a7df3c4 LL |
348 | #define MAX_TXVGA_EEPROM 9 /* How many word(u16) of EEPROM will be used for TxVGA */ |
349 | #define MAX_RF_PARAMETER 32 | |
66101de1 PM |
350 | |
351 | typedef struct _TXVGA_FOR_50 { | |
5a7df3c4 LL |
352 | u8 ChanNo; |
353 | u8 TxVgaValue; | |
66101de1 PM |
354 | } TXVGA_FOR_50; |
355 | ||
356 | ||
5a7df3c4 LL |
357 | /* |
358 | * ============================================== | |
359 | * Device related include | |
360 | * ============================================== | |
361 | */ | |
66101de1 | 362 | |
9ce922fd PE |
363 | #include "wbusb_s.h" |
364 | #include "wb35reg_s.h" | |
365 | #include "wb35tx_s.h" | |
366 | #include "wb35rx_s.h" | |
66101de1 | 367 | |
5a7df3c4 | 368 | /* For Hal using ============================================ */ |
8e41b4b6 | 369 | struct hw_data { |
5a7df3c4 | 370 | /* For compatible with 33 */ |
66101de1 | 371 | u32 revision; |
5a7df3c4 LL |
372 | u32 BB3c_cal; /* The value for Tx calibration comes from EEPROM */ |
373 | u32 BB54_cal; /* The value for Rx calibration comes from EEPROM */ | |
66101de1 | 374 | |
5a7df3c4 LL |
375 | /* For surprise remove */ |
376 | u32 SurpriseRemove; /* 0: Normal 1: Surprise remove */ | |
66101de1 | 377 | u8 IsKeyPreSet; |
5a7df3c4 | 378 | u8 CalOneTime; |
66101de1 PM |
379 | |
380 | u8 VCO_trim; | |
381 | ||
66101de1 | 382 | u32 FragCount; |
5a7df3c4 LL |
383 | u32 DMAFix; /* V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. */ |
384 | ||
385 | /* | |
386 | * =============================================== | |
387 | * Definition for MAC address | |
388 | * =============================================== | |
389 | */ | |
390 | u8 PermanentMacAddress[ETH_ALEN + 2]; /* The Ethernet addr that are stored in EEPROM. + 2 to 8-byte alignment */ | |
391 | u8 CurrentMacAddress[ETH_ALEN + 2]; /* The Enthernet addr that are in used. + 2 to 8-byte alignment */ | |
392 | ||
393 | /* | |
394 | * ========================================= | |
395 | * Definition for 802.11 | |
396 | * ========================================= | |
397 | */ | |
398 | u8 *bssid_pointer; /* Used by hal_get_bssid for return value */ | |
399 | u8 bssid[8]; /* Only 6 byte will be used. 8 byte is required for read buffer */ | |
400 | u8 ssid[32]; /* maximum ssid length is 32 byte */ | |
66101de1 PM |
401 | |
402 | u16 AID; | |
403 | u8 ssid_length; | |
404 | u8 Channel; | |
405 | ||
406 | u16 ListenInterval; | |
407 | u16 CapabilityInformation; | |
408 | ||
409 | u16 BeaconPeriod; | |
410 | u16 ProbeDelay; | |
411 | ||
5a7df3c4 LL |
412 | u8 bss_type;/* 0: IBSS_NET or 1:ESS_NET */ |
413 | u8 preamble;/* 0: short preamble, 1: long preamble */ | |
414 | u8 slot_time_select; /* 9 or 20 value */ | |
415 | u8 phy_type; /* Phy select */ | |
66101de1 PM |
416 | |
417 | u32 phy_para[MAX_RF_PARAMETER]; | |
418 | u32 phy_number; | |
419 | ||
5a7df3c4 LL |
420 | u32 CurrentRadioSw; /* 0:On 1:Off */ |
421 | u32 CurrentRadioHw; /* 0:On 1:Off */ | |
66101de1 | 422 | |
5a7df3c4 | 423 | u8 *power_save_point; /* Used by hal_get_power_save_mode for return value */ |
66101de1 PM |
424 | u8 cwmin; |
425 | u8 desired_power_save; | |
5a7df3c4 LL |
426 | u8 dtim; /* Is running dtim */ |
427 | u8 mapping_key_replace_index; /* In Key table, the next index be replaced */ | |
66101de1 PM |
428 | |
429 | u16 MaxReceiveLifeTime; | |
430 | u16 FragmentThreshold; | |
431 | u16 FragmentThreshold_tmp; | |
432 | u16 cwmax; | |
433 | ||
5a7df3c4 LL |
434 | u8 Key_slot[MAX_KEY_TABLE][8]; /* Ownership record for key slot. For Alignment */ |
435 | u32 Key_content[MAX_KEY_TABLE][12]; /* 10DW for each entry + 2 for burst command (Off and On valid bit) */ | |
66101de1 PM |
436 | u8 CurrentDefaultKeyIndex; |
437 | u32 CurrentDefaultKeyLength; | |
438 | ||
5a7df3c4 LL |
439 | /* |
440 | * ================================================== | |
441 | * Variable for each module | |
442 | * ================================================== | |
443 | */ | |
444 | struct wb_usb WbUsb; /* Need WbUsb.h */ | |
445 | struct wb35_reg reg; /* Need Wb35Reg.h */ | |
446 | struct wb35_tx Wb35Tx; /* Need Wb35Tx.h */ | |
447 | struct wb35_rx Wb35Rx; /* Need Wb35Rx.h */ | |
66101de1 | 448 | |
5a7df3c4 | 449 | struct timer_list LEDTimer; /* For LED */ |
66101de1 | 450 | |
5a7df3c4 | 451 | u32 LEDpoint; /* For LED */ |
66101de1 | 452 | |
5a7df3c4 LL |
453 | u32 dto_tx_retry_count; |
454 | u32 dto_tx_frag_count; | |
455 | u32 rx_ok_count[13]; /* index=0: total rx ok */ | |
456 | u32 rx_err_count[13]; /* index=0: total rx err */ | |
66101de1 | 457 | |
5a7df3c4 | 458 | /* for Tx debug */ |
66101de1 PM |
459 | u32 tx_TBTT_start_count; |
460 | u32 tx_ETR_count; | |
461 | u32 tx_WepOn_false_count; | |
462 | u32 tx_Null_key_count; | |
463 | u32 tx_retry_count[8]; | |
464 | ||
5a7df3c4 LL |
465 | u8 PowerIndexFromEEPROM; /* For 2412MHz */ |
466 | u8 power_index; | |
467 | u8 IsWaitJoinComplete; /* TRUE: set join request */ | |
468 | u8 band; | |
66101de1 | 469 | |
5a7df3c4 LL |
470 | u16 SoftwareSet; |
471 | u16 Reserved_s; | |
66101de1 | 472 | |
5a7df3c4 | 473 | u32 IsInitOK; /* 0: Driver starting 1: Driver init OK */ |
66101de1 | 474 | |
5a7df3c4 LL |
475 | /* For Phy calibration */ |
476 | s32 iq_rsdl_gain_tx_d2; | |
477 | s32 iq_rsdl_phase_tx_d2; | |
478 | u32 txvga_setting_for_cal; | |
66101de1 | 479 | |
5a7df3c4 LL |
480 | u8 TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */ |
481 | u8 TxVgaFor24[16]; /* Max is 14, 2 for alignment */ | |
482 | TXVGA_FOR_50 TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */ | |
66101de1 | 483 | |
5a7df3c4 LL |
484 | u16 Scan_Interval; |
485 | u16 RESERVED6; | |
66101de1 | 486 | |
5a7df3c4 | 487 | /* LED control */ |
66101de1 | 488 | u32 LED_control; |
5a7df3c4 LL |
489 | /* |
490 | * LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0] | |
491 | * Gray_Led | |
492 | * For Led gray setting | |
493 | * Led | |
494 | * 0: normal control, | |
495 | * LED behavior will decide by EEPROM setting | |
496 | * 1: Turn off specific LED | |
497 | * 2: Always on specific LED | |
498 | * 3: slow blinking specific LED | |
499 | * 4: fast blinking specific LED | |
500 | * 5: WPS led control is set. Led0 is Red, Led1 id Green | |
501 | * | |
502 | * Led[1] is parameter for WPS LED mode | |
503 | * 1:InProgress | |
504 | * 2: Error | |
505 | * 3: Session overlap | |
506 | * 4: Success control | |
507 | */ | |
508 | u32 LED_LinkOn; /* Turn LED on control */ | |
509 | u32 LED_Scanning; /* Let LED in scan process control */ | |
510 | u32 LED_Blinking; /* Temp variable for shining */ | |
66101de1 PM |
511 | u32 RxByteCountLast; |
512 | u32 TxByteCountLast; | |
513 | ||
44e8541c | 514 | atomic_t SurpriseRemoveCount; |
66101de1 | 515 | |
5a7df3c4 LL |
516 | /* For global timer */ |
517 | u32 time_count; /* TICK_TIME_100ms 1 = 100ms */ | |
66101de1 | 518 | |
5a7df3c4 | 519 | /* For error recover */ |
66101de1 PM |
520 | u32 HwStop; |
521 | ||
5a7df3c4 | 522 | /* For avoid AP disconnect */ |
66101de1 | 523 | u32 NullPacketCount; |
8e41b4b6 | 524 | }; |
66101de1 | 525 | |
80aba536 | 526 | #endif |