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66101de1 PM |
1 | /* |
2 | * phy_302_calibration.c | |
3 | * | |
4 | * Copyright (C) 2002, 2005 Winbond Electronics Corp. | |
5 | * | |
6 | * modification history | |
7 | * --------------------------------------------------------------------------- | |
8 | * 0.01.001, 2003-04-16, Kevin created | |
9 | * | |
10 | */ | |
11 | ||
12 | /****************** INCLUDE FILES SECTION ***********************************/ | |
7e797abf | 13 | #include "sysdef.h" |
66101de1 | 14 | #include "phy_calibration.h" |
80aba536 | 15 | #include "wbhal_f.h" |
66101de1 PM |
16 | |
17 | ||
18 | /****************** DEBUG CONSTANT AND MACRO SECTION ************************/ | |
19 | ||
20 | /****************** LOCAL CONSTANT AND MACRO SECTION ************************/ | |
21 | #define LOOP_TIMES 20 | |
22 | #define US 1000//MICROSECOND | |
23 | ||
24 | #define AG_CONST 0.6072529350 | |
25 | #define FIXED(X) ((s32)((X) * 32768.0)) | |
26 | #define DEG2RAD(X) 0.017453 * (X) | |
27 | ||
20dbe695 | 28 | static const s32 Angles[] = |
66101de1 PM |
29 | { |
30 | FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)), | |
31 | FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), | |
32 | FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)), | |
33 | FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977)) | |
34 | }; | |
35 | ||
36 | /****************** LOCAL FUNCTION DECLARATION SECTION **********************/ | |
8e41b4b6 PE |
37 | //void _phy_rf_write_delay(struct hw_data *phw_data); |
38 | //void phy_init_rf(struct hw_data *phw_data); | |
66101de1 PM |
39 | |
40 | /****************** FUNCTION DEFINITION SECTION *****************************/ | |
41 | ||
42 | s32 _s13_to_s32(u32 data) | |
43 | { | |
44 | u32 val; | |
45 | ||
46 | val = (data & 0x0FFF); | |
47 | ||
48 | if ((data & BIT(12)) != 0) | |
49 | { | |
50 | val |= 0xFFFFF000; | |
51 | } | |
52 | ||
53 | return ((s32) val); | |
54 | } | |
55 | ||
56 | u32 _s32_to_s13(s32 data) | |
57 | { | |
58 | u32 val; | |
59 | ||
60 | if (data > 4095) | |
61 | { | |
62 | data = 4095; | |
63 | } | |
64 | else if (data < -4096) | |
65 | { | |
66 | data = -4096; | |
67 | } | |
68 | ||
69 | val = data & 0x1FFF; | |
70 | ||
71 | return val; | |
72 | } | |
73 | ||
74 | /****************************************************************************/ | |
75 | s32 _s4_to_s32(u32 data) | |
76 | { | |
77 | s32 val; | |
78 | ||
79 | val = (data & 0x0007); | |
80 | ||
81 | if ((data & BIT(3)) != 0) | |
82 | { | |
83 | val |= 0xFFFFFFF8; | |
84 | } | |
85 | ||
86 | return val; | |
87 | } | |
88 | ||
89 | u32 _s32_to_s4(s32 data) | |
90 | { | |
91 | u32 val; | |
92 | ||
93 | if (data > 7) | |
94 | { | |
95 | data = 7; | |
96 | } | |
97 | else if (data < -8) | |
98 | { | |
99 | data = -8; | |
100 | } | |
101 | ||
102 | val = data & 0x000F; | |
103 | ||
104 | return val; | |
105 | } | |
106 | ||
107 | /****************************************************************************/ | |
108 | s32 _s5_to_s32(u32 data) | |
109 | { | |
110 | s32 val; | |
111 | ||
112 | val = (data & 0x000F); | |
113 | ||
114 | if ((data & BIT(4)) != 0) | |
115 | { | |
116 | val |= 0xFFFFFFF0; | |
117 | } | |
118 | ||
119 | return val; | |
120 | } | |
121 | ||
122 | u32 _s32_to_s5(s32 data) | |
123 | { | |
124 | u32 val; | |
125 | ||
126 | if (data > 15) | |
127 | { | |
128 | data = 15; | |
129 | } | |
130 | else if (data < -16) | |
131 | { | |
132 | data = -16; | |
133 | } | |
134 | ||
135 | val = data & 0x001F; | |
136 | ||
137 | return val; | |
138 | } | |
139 | ||
140 | /****************************************************************************/ | |
141 | s32 _s6_to_s32(u32 data) | |
142 | { | |
143 | s32 val; | |
144 | ||
145 | val = (data & 0x001F); | |
146 | ||
147 | if ((data & BIT(5)) != 0) | |
148 | { | |
149 | val |= 0xFFFFFFE0; | |
150 | } | |
151 | ||
152 | return val; | |
153 | } | |
154 | ||
155 | u32 _s32_to_s6(s32 data) | |
156 | { | |
157 | u32 val; | |
158 | ||
159 | if (data > 31) | |
160 | { | |
161 | data = 31; | |
162 | } | |
163 | else if (data < -32) | |
164 | { | |
165 | data = -32; | |
166 | } | |
167 | ||
168 | val = data & 0x003F; | |
169 | ||
170 | return val; | |
171 | } | |
172 | ||
173 | /****************************************************************************/ | |
174 | s32 _s9_to_s32(u32 data) | |
175 | { | |
176 | s32 val; | |
177 | ||
178 | val = data & 0x00FF; | |
179 | ||
180 | if ((data & BIT(8)) != 0) | |
181 | { | |
182 | val |= 0xFFFFFF00; | |
183 | } | |
184 | ||
185 | return val; | |
186 | } | |
187 | ||
188 | u32 _s32_to_s9(s32 data) | |
189 | { | |
190 | u32 val; | |
191 | ||
192 | if (data > 255) | |
193 | { | |
194 | data = 255; | |
195 | } | |
196 | else if (data < -256) | |
197 | { | |
198 | data = -256; | |
199 | } | |
200 | ||
201 | val = data & 0x01FF; | |
202 | ||
203 | return val; | |
204 | } | |
205 | ||
206 | /****************************************************************************/ | |
207 | s32 _floor(s32 n) | |
208 | { | |
209 | if (n > 0) | |
210 | { | |
211 | n += 5; | |
212 | } | |
213 | else | |
214 | { | |
215 | n -= 5; | |
216 | } | |
217 | ||
218 | return (n/10); | |
219 | } | |
220 | ||
221 | /****************************************************************************/ | |
222 | // The following code is sqare-root function. | |
223 | // sqsum is the input and the output is sq_rt; | |
224 | // The maximum of sqsum = 2^27 -1; | |
225 | u32 _sqrt(u32 sqsum) | |
226 | { | |
227 | u32 sq_rt; | |
228 | ||
229 | int g0, g1, g2, g3, g4; | |
230 | int seed; | |
231 | int next; | |
232 | int step; | |
233 | ||
234 | g4 = sqsum / 100000000; | |
235 | g3 = (sqsum - g4*100000000) /1000000; | |
236 | g2 = (sqsum - g4*100000000 - g3*1000000) /10000; | |
237 | g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100; | |
238 | g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100); | |
239 | ||
240 | next = g4; | |
241 | step = 0; | |
242 | seed = 0; | |
243 | while (((seed+1)*(step+1)) <= next) | |
244 | { | |
245 | step++; | |
246 | seed++; | |
247 | } | |
248 | ||
249 | sq_rt = seed * 10000; | |
250 | next = (next-(seed*step))*100 + g3; | |
251 | ||
252 | step = 0; | |
253 | seed = 2 * seed * 10; | |
254 | while (((seed+1)*(step+1)) <= next) | |
255 | { | |
256 | step++; | |
257 | seed++; | |
258 | } | |
259 | ||
260 | sq_rt = sq_rt + step * 1000; | |
261 | next = (next - seed * step) * 100 + g2; | |
262 | seed = (seed + step) * 10; | |
263 | step = 0; | |
264 | while (((seed+1)*(step+1)) <= next) | |
265 | { | |
266 | step++; | |
267 | seed++; | |
268 | } | |
269 | ||
270 | sq_rt = sq_rt + step * 100; | |
271 | next = (next - seed * step) * 100 + g1; | |
272 | seed = (seed + step) * 10; | |
273 | step = 0; | |
274 | ||
275 | while (((seed+1)*(step+1)) <= next) | |
276 | { | |
277 | step++; | |
278 | seed++; | |
279 | } | |
280 | ||
281 | sq_rt = sq_rt + step * 10; | |
282 | next = (next - seed* step) * 100 + g0; | |
283 | seed = (seed + step) * 10; | |
284 | step = 0; | |
285 | ||
286 | while (((seed+1)*(step+1)) <= next) | |
287 | { | |
288 | step++; | |
289 | seed++; | |
290 | } | |
291 | ||
292 | sq_rt = sq_rt + step; | |
293 | ||
294 | return sq_rt; | |
295 | } | |
296 | ||
297 | /****************************************************************************/ | |
298 | void _sin_cos(s32 angle, s32 *sin, s32 *cos) | |
299 | { | |
20dbe695 | 300 | s32 X, Y, TargetAngle, CurrAngle; |
66101de1 PM |
301 | unsigned Step; |
302 | ||
303 | X=FIXED(AG_CONST); // AG_CONST * cos(0) | |
304 | Y=0; // AG_CONST * sin(0) | |
305 | TargetAngle=abs(angle); | |
306 | CurrAngle=0; | |
307 | ||
308 | for (Step=0; Step < 12; Step++) | |
309 | { | |
20dbe695 | 310 | s32 NewX; |
66101de1 PM |
311 | |
312 | if(TargetAngle > CurrAngle) | |
313 | { | |
314 | NewX=X - (Y >> Step); | |
315 | Y=(X >> Step) + Y; | |
316 | X=NewX; | |
317 | CurrAngle += Angles[Step]; | |
318 | } | |
319 | else | |
320 | { | |
321 | NewX=X + (Y >> Step); | |
322 | Y=-(X >> Step) + Y; | |
323 | X=NewX; | |
324 | CurrAngle -= Angles[Step]; | |
325 | } | |
326 | } | |
327 | ||
328 | if (angle > 0) | |
329 | { | |
330 | *cos = X; | |
331 | *sin = Y; | |
332 | } | |
333 | else | |
334 | { | |
335 | *cos = X; | |
336 | *sin = -Y; | |
337 | } | |
338 | } | |
339 | ||
dd68e1b4 PE |
340 | static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, u32 * pValue) |
341 | { | |
342 | if (number < 0x1000) | |
343 | number += 0x1000; | |
344 | return Wb35Reg_ReadSync(pHwData, number, pValue); | |
345 | } | |
346 | #define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C ) | |
347 | ||
348 | static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 value) | |
349 | { | |
350 | unsigned char ret; | |
351 | ||
352 | if (number < 0x1000) | |
353 | number += 0x1000; | |
354 | ret = Wb35Reg_WriteSync(pHwData, number, value); | |
355 | return ret; | |
356 | } | |
357 | #define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C ) | |
358 | ||
66101de1 | 359 | |
8e41b4b6 | 360 | void _reset_rx_cal(struct hw_data *phw_data) |
66101de1 PM |
361 | { |
362 | u32 val; | |
363 | ||
364 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
365 | ||
366 | if (phw_data->revision == 0x2002) // 1st-cut | |
367 | { | |
368 | val &= 0xFFFF0000; | |
369 | } | |
370 | else // 2nd-cut | |
371 | { | |
372 | val &= 0x000003FF; | |
373 | } | |
374 | ||
375 | hw_set_dxx_reg(phw_data, 0x54, val); | |
376 | } | |
377 | ||
378 | ||
379 | // ************for winbond calibration********* | |
380 | // | |
381 | ||
382 | // | |
383 | // | |
384 | // ********************************************* | |
8e41b4b6 | 385 | void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) |
66101de1 PM |
386 | { |
387 | u32 reg_agc_ctrl3; | |
388 | u32 reg_a_acq_ctrl; | |
389 | u32 reg_b_acq_ctrl; | |
390 | u32 val; | |
391 | ||
392 | PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n")); | |
393 | phy_init_rf(phw_data); | |
394 | ||
395 | // set calibration channel | |
396 | if( (RF_WB_242 == phw_data->phy_type) || | |
397 | (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add | |
398 | { | |
399 | if ((frequency >= 2412) && (frequency <= 2484)) | |
400 | { | |
401 | // w89rf242 change frequency to 2390Mhz | |
402 | PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n")); | |
403 | phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); | |
404 | ||
405 | } | |
406 | } | |
407 | else | |
408 | { | |
409 | ||
410 | } | |
411 | ||
412 | // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel | |
413 | hw_get_dxx_reg(phw_data, 0x5C, &val); | |
414 | val &= ~(0x03FF); | |
415 | hw_set_dxx_reg(phw_data, 0x5C, val); | |
416 | ||
417 | // reset the TX and RX IQ calibration data | |
418 | hw_set_dxx_reg(phw_data, 0x3C, 0); | |
419 | hw_set_dxx_reg(phw_data, 0x54, 0); | |
420 | ||
421 | hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed | |
422 | ||
423 | // a. Disable AGC | |
424 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); | |
425 | reg_agc_ctrl3 &= ~BIT(2); | |
426 | reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); | |
427 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); | |
428 | ||
429 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); | |
430 | val |= MASK_AGC_FIX_GAIN; | |
431 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); | |
432 | ||
433 | // b. Turn off BB RX | |
434 | hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); | |
435 | reg_a_acq_ctrl |= MASK_AMER_OFF_REG; | |
436 | hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); | |
437 | ||
438 | hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl); | |
439 | reg_b_acq_ctrl |= MASK_BMER_OFF_REG; | |
440 | hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); | |
441 | ||
442 | // c. Make sure MAC is in receiving mode | |
443 | // d. Turn ON ADC calibration | |
444 | // - ADC calibrator is triggered by this signal rising from 0 to 1 | |
445 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); | |
446 | val &= ~MASK_ADC_DC_CAL_STR; | |
447 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); | |
448 | ||
449 | val |= MASK_ADC_DC_CAL_STR; | |
450 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); | |
66101de1 PM |
451 | |
452 | // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" | |
453 | #ifdef _DEBUG | |
454 | hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val); | |
455 | PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val)); | |
456 | ||
457 | PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n", | |
458 | _s9_to_s32(val&0x000001FF), val&0x000001FF)); | |
459 | PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n", | |
460 | _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9)); | |
461 | #endif | |
462 | ||
463 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); | |
464 | val &= ~MASK_ADC_DC_CAL_STR; | |
465 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); | |
466 | ||
467 | // f. Turn on BB RX | |
468 | //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); | |
469 | reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG; | |
470 | hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); | |
471 | ||
472 | //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl); | |
473 | reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG; | |
474 | hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); | |
475 | ||
476 | // g. Enable AGC | |
477 | //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); | |
478 | reg_agc_ctrl3 |= BIT(2); | |
479 | reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); | |
480 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); | |
481 | } | |
482 | ||
483 | //////////////////////////////////////////////////////// | |
8e41b4b6 | 484 | void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data) |
66101de1 PM |
485 | { |
486 | u32 reg_agc_ctrl3; | |
487 | u32 reg_mode_ctrl; | |
488 | u32 reg_dc_cancel; | |
489 | s32 iqcal_image_i; | |
490 | s32 iqcal_image_q; | |
491 | u32 sqsum; | |
492 | s32 mag_0; | |
493 | s32 mag_1; | |
494 | s32 fix_cancel_dc_i = 0; | |
495 | u32 val; | |
496 | int loop; | |
497 | ||
498 | PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n")); | |
499 | ||
500 | // a. Set to "TX calibration mode" | |
501 | ||
502 | //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits | |
503 | phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); | |
504 | //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit | |
505 | phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); | |
506 | //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized | |
507 | phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); | |
508 | //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized | |
509 | phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); | |
510 | //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode | |
511 | phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); | |
512 | ||
513 | hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed | |
514 | ||
515 | // a. Disable AGC | |
516 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); | |
517 | reg_agc_ctrl3 &= ~BIT(2); | |
518 | reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); | |
519 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); | |
520 | ||
521 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); | |
522 | val |= MASK_AGC_FIX_GAIN; | |
523 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); | |
524 | ||
525 | // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 | |
526 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
527 | ||
528 | PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); | |
529 | reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); | |
530 | ||
531 | // mode=2, tone=0 | |
532 | //reg_mode_ctrl |= (MASK_CALIB_START|2); | |
533 | ||
534 | // mode=2, tone=1 | |
535 | //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); | |
536 | ||
537 | // mode=2, tone=2 | |
538 | reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2)); | |
539 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
540 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
66101de1 PM |
541 | |
542 | hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel); | |
543 | PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); | |
544 | ||
545 | for (loop = 0; loop < LOOP_TIMES; loop++) | |
546 | { | |
547 | PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); | |
548 | ||
549 | // c. | |
550 | // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel | |
551 | reg_dc_cancel &= ~(0x03FF); | |
552 | PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); | |
553 | hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); | |
66101de1 PM |
554 | |
555 | hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); | |
556 | PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); | |
557 | ||
558 | iqcal_image_i = _s13_to_s32(val & 0x00001FFF); | |
559 | iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
560 | sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; | |
561 | mag_0 = (s32) _sqrt(sqsum); | |
562 | PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", | |
563 | mag_0, iqcal_image_i, iqcal_image_q)); | |
564 | ||
565 | // d. | |
566 | reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT); | |
567 | PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); | |
568 | hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); | |
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569 | |
570 | hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); | |
571 | PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); | |
572 | ||
573 | iqcal_image_i = _s13_to_s32(val & 0x00001FFF); | |
574 | iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
575 | sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; | |
576 | mag_1 = (s32) _sqrt(sqsum); | |
577 | PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", | |
578 | mag_1, iqcal_image_i, iqcal_image_q)); | |
579 | ||
580 | // e. Calculate the correct DC offset cancellation value for I | |
581 | if (mag_0 != mag_1) | |
582 | { | |
583 | fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000); | |
584 | } | |
585 | else | |
586 | { | |
587 | if (mag_0 == mag_1) | |
588 | { | |
589 | PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); | |
590 | } | |
591 | ||
592 | fix_cancel_dc_i = 0; | |
593 | } | |
594 | ||
595 | PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n", | |
596 | fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i))); | |
597 | ||
598 | if ((abs(mag_1-mag_0)*6) > mag_0) | |
599 | { | |
600 | break; | |
601 | } | |
602 | } | |
603 | ||
604 | if ( loop >= 19 ) | |
605 | fix_cancel_dc_i = 0; | |
606 | ||
607 | reg_dc_cancel &= ~(0x03FF); | |
608 | reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT); | |
609 | hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); | |
610 | PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); | |
611 | ||
612 | // g. | |
613 | reg_mode_ctrl &= ~MASK_CALIB_START; | |
614 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
615 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
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616 | } |
617 | ||
618 | /////////////////////////////////////////////////////// | |
8e41b4b6 | 619 | void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data) |
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620 | { |
621 | u32 reg_agc_ctrl3; | |
622 | u32 reg_mode_ctrl; | |
623 | u32 reg_dc_cancel; | |
624 | s32 iqcal_image_i; | |
625 | s32 iqcal_image_q; | |
626 | u32 sqsum; | |
627 | s32 mag_0; | |
628 | s32 mag_1; | |
629 | s32 fix_cancel_dc_q = 0; | |
630 | u32 val; | |
631 | int loop; | |
632 | ||
633 | PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n")); | |
634 | //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits | |
635 | phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); | |
636 | //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit | |
637 | phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); | |
638 | //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized | |
639 | phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); | |
640 | //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized | |
641 | phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); | |
642 | //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode | |
643 | phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); | |
644 | ||
645 | hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed | |
646 | ||
647 | // a. Disable AGC | |
648 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); | |
649 | reg_agc_ctrl3 &= ~BIT(2); | |
650 | reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); | |
651 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); | |
652 | ||
653 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); | |
654 | val |= MASK_AGC_FIX_GAIN; | |
655 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); | |
656 | ||
657 | // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 | |
658 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
659 | PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); | |
660 | ||
661 | //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); | |
662 | reg_mode_ctrl &= ~(MASK_IQCAL_MODE); | |
663 | reg_mode_ctrl |= (MASK_CALIB_START|3); | |
664 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
665 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
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666 | |
667 | hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel); | |
668 | PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); | |
669 | ||
670 | for (loop = 0; loop < LOOP_TIMES; loop++) | |
671 | { | |
672 | PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); | |
673 | ||
674 | // b. | |
675 | // reset cancel_dc_q[4:0] in register DC_Cancel | |
676 | reg_dc_cancel &= ~(0x001F); | |
677 | PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); | |
678 | hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); | |
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679 | |
680 | hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); | |
681 | PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); | |
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682 | |
683 | iqcal_image_i = _s13_to_s32(val & 0x00001FFF); | |
684 | iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
685 | sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; | |
686 | mag_0 = _sqrt(sqsum); | |
687 | PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", | |
688 | mag_0, iqcal_image_i, iqcal_image_q)); | |
689 | ||
690 | // c. | |
691 | reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT); | |
692 | PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); | |
693 | hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); | |
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694 | |
695 | hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); | |
696 | PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); | |
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697 | |
698 | iqcal_image_i = _s13_to_s32(val & 0x00001FFF); | |
699 | iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
700 | sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; | |
701 | mag_1 = _sqrt(sqsum); | |
702 | PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", | |
703 | mag_1, iqcal_image_i, iqcal_image_q)); | |
704 | ||
705 | // d. Calculate the correct DC offset cancellation value for I | |
706 | if (mag_0 != mag_1) | |
707 | { | |
708 | fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000); | |
709 | } | |
710 | else | |
711 | { | |
712 | if (mag_0 == mag_1) | |
713 | { | |
714 | PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); | |
715 | } | |
716 | ||
717 | fix_cancel_dc_q = 0; | |
718 | } | |
719 | ||
720 | PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n", | |
721 | fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q))); | |
722 | ||
723 | if ((abs(mag_1-mag_0)*6) > mag_0) | |
724 | { | |
725 | break; | |
726 | } | |
727 | } | |
728 | ||
729 | if ( loop >= 19 ) | |
730 | fix_cancel_dc_q = 0; | |
731 | ||
732 | reg_dc_cancel &= ~(0x001F); | |
733 | reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT); | |
734 | hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); | |
735 | PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); | |
736 | ||
737 | ||
738 | // f. | |
739 | reg_mode_ctrl &= ~MASK_CALIB_START; | |
740 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
741 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
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742 | } |
743 | ||
744 | //20060612.1.a 20060718.1 Modify | |
8e41b4b6 | 745 | u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, |
66101de1 PM |
746 | s32 a_2_threshold, |
747 | s32 b_2_threshold) | |
748 | { | |
749 | u32 reg_mode_ctrl; | |
750 | s32 iq_mag_0_tx; | |
751 | s32 iqcal_tone_i0; | |
752 | s32 iqcal_tone_q0; | |
753 | s32 iqcal_tone_i; | |
754 | s32 iqcal_tone_q; | |
755 | u32 sqsum; | |
756 | s32 rot_i_b; | |
757 | s32 rot_q_b; | |
758 | s32 tx_cal_flt_b[4]; | |
759 | s32 tx_cal[4]; | |
760 | s32 tx_cal_reg[4]; | |
761 | s32 a_2, b_2; | |
762 | s32 sin_b, sin_2b; | |
763 | s32 cos_b, cos_2b; | |
764 | s32 divisor; | |
765 | s32 temp1, temp2; | |
766 | u32 val; | |
767 | u16 loop; | |
768 | s32 iqcal_tone_i_avg,iqcal_tone_q_avg; | |
769 | u8 verify_count; | |
770 | int capture_time; | |
771 | ||
772 | PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n")); | |
773 | PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold)); | |
774 | PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold)); | |
775 | ||
776 | verify_count = 0; | |
777 | ||
778 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
779 | PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); | |
780 | ||
781 | loop = LOOP_TIMES; | |
782 | ||
783 | while (loop > 0) | |
784 | { | |
785 | PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); | |
786 | ||
787 | iqcal_tone_i_avg=0; | |
788 | iqcal_tone_q_avg=0; | |
789 | if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify | |
790 | return 0; | |
791 | for(capture_time=0;capture_time<10;capture_time++) | |
792 | { | |
793 | // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to | |
794 | // enable "IQ alibration Mode II" | |
795 | reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); | |
796 | reg_mode_ctrl &= ~MASK_IQCAL_MODE; | |
797 | reg_mode_ctrl |= (MASK_CALIB_START|0x02); | |
798 | reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2); | |
799 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
800 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
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801 | |
802 | // b. | |
803 | hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); | |
804 | PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); | |
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805 | |
806 | iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); | |
807 | iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); | |
808 | PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n", | |
809 | iqcal_tone_i0, iqcal_tone_q0)); | |
810 | ||
811 | sqsum = iqcal_tone_i0*iqcal_tone_i0 + | |
812 | iqcal_tone_q0*iqcal_tone_q0; | |
813 | iq_mag_0_tx = (s32) _sqrt(sqsum); | |
814 | PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx)); | |
815 | ||
816 | // c. Set "calib_start" to 0x0 | |
817 | reg_mode_ctrl &= ~MASK_CALIB_START; | |
818 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
819 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
66101de1 PM |
820 | |
821 | // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to | |
822 | // enable "IQ alibration Mode II" | |
823 | //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); | |
824 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
825 | reg_mode_ctrl &= ~MASK_IQCAL_MODE; | |
826 | reg_mode_ctrl |= (MASK_CALIB_START|0x03); | |
827 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
828 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
66101de1 PM |
829 | |
830 | // e. | |
831 | hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); | |
832 | PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); | |
66101de1 PM |
833 | |
834 | iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); | |
835 | iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
836 | PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", | |
837 | iqcal_tone_i, iqcal_tone_q)); | |
838 | if( capture_time == 0) | |
839 | { | |
840 | continue; | |
841 | } | |
842 | else | |
843 | { | |
844 | iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time; | |
845 | iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time; | |
846 | } | |
847 | } | |
848 | ||
849 | iqcal_tone_i = iqcal_tone_i_avg; | |
850 | iqcal_tone_q = iqcal_tone_q_avg; | |
851 | ||
852 | ||
853 | rot_i_b = (iqcal_tone_i * iqcal_tone_i0 + | |
854 | iqcal_tone_q * iqcal_tone_q0) / 1024; | |
855 | rot_q_b = (iqcal_tone_i * iqcal_tone_q0 * (-1) + | |
856 | iqcal_tone_q * iqcal_tone_i0) / 1024; | |
857 | PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n", | |
858 | rot_i_b, rot_q_b)); | |
859 | ||
860 | // f. | |
861 | divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2; | |
862 | ||
863 | if (divisor == 0) | |
864 | { | |
865 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); | |
866 | PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n")); | |
867 | PHY_DEBUG(("[CAL] ******************************************\n")); | |
868 | break; | |
869 | } | |
870 | ||
871 | a_2 = (rot_i_b * 32768) / divisor; | |
872 | b_2 = (rot_q_b * (-32768)) / divisor; | |
873 | PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); | |
874 | PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); | |
875 | ||
876 | phw_data->iq_rsdl_gain_tx_d2 = a_2; | |
877 | phw_data->iq_rsdl_phase_tx_d2 = b_2; | |
878 | ||
879 | //if ((abs(a_2) < 150) && (abs(b_2) < 100)) | |
880 | //if ((abs(a_2) < 200) && (abs(b_2) < 200)) | |
881 | if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) | |
882 | { | |
883 | verify_count++; | |
884 | ||
885 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); | |
886 | PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); | |
887 | PHY_DEBUG(("[CAL] ******************************************\n")); | |
888 | ||
889 | if (verify_count > 2) | |
890 | { | |
891 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); | |
892 | PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n")); | |
893 | PHY_DEBUG(("[CAL] **************************************\n")); | |
894 | return 0; | |
895 | } | |
896 | ||
897 | continue; | |
898 | } | |
899 | else | |
900 | { | |
901 | verify_count = 0; | |
902 | } | |
903 | ||
904 | _sin_cos(b_2, &sin_b, &cos_b); | |
905 | _sin_cos(b_2*2, &sin_2b, &cos_2b); | |
906 | PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); | |
907 | PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); | |
908 | ||
909 | if (cos_2b == 0) | |
910 | { | |
911 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); | |
912 | PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); | |
913 | PHY_DEBUG(("[CAL] ******************************************\n")); | |
914 | break; | |
915 | } | |
916 | ||
917 | // 1280 * 32768 = 41943040 | |
918 | temp1 = (41943040/cos_2b)*cos_b; | |
919 | ||
920 | //temp2 = (41943040/cos_2b)*sin_b*(-1); | |
921 | if (phw_data->revision == 0x2002) // 1st-cut | |
922 | { | |
923 | temp2 = (41943040/cos_2b)*sin_b*(-1); | |
924 | } | |
925 | else // 2nd-cut | |
926 | { | |
927 | temp2 = (41943040*4/cos_2b)*sin_b*(-1); | |
928 | } | |
929 | ||
930 | tx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); | |
931 | tx_cal_flt_b[1] = _floor(temp2/(32768+a_2)); | |
932 | tx_cal_flt_b[2] = _floor(temp2/(32768-a_2)); | |
933 | tx_cal_flt_b[3] = _floor(temp1/(32768-a_2)); | |
934 | PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b[0])); | |
935 | PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b[1])); | |
936 | PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b[2])); | |
937 | PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3])); | |
938 | ||
939 | tx_cal[2] = tx_cal_flt_b[2]; | |
940 | tx_cal[2] = tx_cal[2] +3; | |
941 | tx_cal[1] = tx_cal[2]; | |
942 | tx_cal[3] = tx_cal_flt_b[3] - 128; | |
943 | tx_cal[0] = -tx_cal[3]+1; | |
944 | ||
945 | PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0])); | |
946 | PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1])); | |
947 | PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2])); | |
948 | PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3])); | |
949 | ||
950 | //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) && | |
951 | // (tx_cal[2] == 0) && (tx_cal[3] == 0)) | |
952 | //{ | |
953 | // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); | |
954 | // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n")); | |
955 | // PHY_DEBUG(("[CAL] ******************************************\n")); | |
956 | // return 0; | |
957 | //} | |
958 | ||
959 | // g. | |
960 | if (phw_data->revision == 0x2002) // 1st-cut | |
961 | { | |
962 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
963 | PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); | |
964 | tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); | |
965 | tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); | |
966 | tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); | |
967 | tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); | |
968 | } | |
969 | else // 2nd-cut | |
970 | { | |
971 | hw_get_dxx_reg(phw_data, 0x3C, &val); | |
972 | PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); | |
973 | tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); | |
974 | tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); | |
975 | tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); | |
976 | tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); | |
977 | ||
978 | } | |
979 | ||
980 | PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0])); | |
981 | PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1])); | |
982 | PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); | |
983 | PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); | |
984 | ||
985 | if (phw_data->revision == 0x2002) // 1st-cut | |
986 | { | |
987 | if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) && | |
988 | ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8)))) | |
989 | { | |
990 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); | |
991 | PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); | |
992 | PHY_DEBUG(("[CAL] **************************************\n")); | |
993 | break; | |
994 | } | |
995 | } | |
996 | else // 2nd-cut | |
997 | { | |
998 | if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) && | |
999 | ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32)))) | |
1000 | { | |
1001 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); | |
1002 | PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); | |
1003 | PHY_DEBUG(("[CAL] **************************************\n")); | |
1004 | break; | |
1005 | } | |
1006 | } | |
1007 | ||
1008 | tx_cal[0] = tx_cal[0] + tx_cal_reg[0]; | |
1009 | tx_cal[1] = tx_cal[1] + tx_cal_reg[1]; | |
1010 | tx_cal[2] = tx_cal[2] + tx_cal_reg[2]; | |
1011 | tx_cal[3] = tx_cal[3] + tx_cal_reg[3]; | |
1012 | PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal[0])); | |
1013 | PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal[1])); | |
1014 | PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2])); | |
1015 | PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3])); | |
1016 | ||
1017 | if (phw_data->revision == 0x2002) // 1st-cut | |
1018 | { | |
1019 | val &= 0x0000FFFF; | |
1020 | val |= ((_s32_to_s4(tx_cal[0]) << 28)| | |
1021 | (_s32_to_s4(tx_cal[1]) << 24)| | |
1022 | (_s32_to_s4(tx_cal[2]) << 20)| | |
1023 | (_s32_to_s4(tx_cal[3]) << 16)); | |
1024 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1025 | PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); | |
1026 | return 0; | |
1027 | } | |
1028 | else // 2nd-cut | |
1029 | { | |
1030 | val &= 0x000003FF; | |
1031 | val |= ((_s32_to_s5(tx_cal[0]) << 27)| | |
1032 | (_s32_to_s6(tx_cal[1]) << 21)| | |
1033 | (_s32_to_s6(tx_cal[2]) << 15)| | |
1034 | (_s32_to_s5(tx_cal[3]) << 10)); | |
1035 | hw_set_dxx_reg(phw_data, 0x3C, val); | |
1036 | PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val)); | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | // i. Set "calib_start" to 0x0 | |
1041 | reg_mode_ctrl &= ~MASK_CALIB_START; | |
1042 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
1043 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
1044 | ||
1045 | loop--; | |
1046 | } | |
1047 | ||
1048 | return 1; | |
1049 | } | |
1050 | ||
8e41b4b6 | 1051 | void _tx_iq_calibration_winbond(struct hw_data *phw_data) |
66101de1 PM |
1052 | { |
1053 | u32 reg_agc_ctrl3; | |
1054 | #ifdef _DEBUG | |
1055 | s32 tx_cal_reg[4]; | |
1056 | ||
1057 | #endif | |
1058 | u32 reg_mode_ctrl; | |
1059 | u32 val; | |
1060 | u8 result; | |
1061 | ||
1062 | PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n")); | |
1063 | ||
1064 | //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits | |
1065 | phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); | |
1066 | //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit | |
1067 | phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6); | |
1068 | //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized | |
1069 | phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature) | |
1070 | //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized | |
1071 | phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C); | |
1072 | //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode | |
1073 | phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); | |
1074 | //; [BB-chip]: Calibration (6f).Send test pattern | |
1075 | //; [BB-chip]: Calibration (6g). Search RXGCL optimal value | |
1076 | //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table | |
1077 | //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); | |
1078 | ||
34222e0a | 1079 | msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines |
66101de1 PM |
1080 | //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 |
1081 | adjust_TXVGA_for_iq_mag( phw_data ); | |
1082 | ||
1083 | // a. Disable AGC | |
1084 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); | |
1085 | reg_agc_ctrl3 &= ~BIT(2); | |
1086 | reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); | |
1087 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); | |
1088 | ||
1089 | hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); | |
1090 | val |= MASK_AGC_FIX_GAIN; | |
1091 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); | |
1092 | ||
1093 | result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100); | |
1094 | ||
1095 | if (result > 0) | |
1096 | { | |
1097 | if (phw_data->revision == 0x2002) // 1st-cut | |
1098 | { | |
1099 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1100 | val &= 0x0000FFFF; | |
1101 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1102 | } | |
1103 | else // 2nd-cut | |
1104 | { | |
1105 | hw_get_dxx_reg(phw_data, 0x3C, &val); | |
1106 | val &= 0x000003FF; | |
1107 | hw_set_dxx_reg(phw_data, 0x3C, val); | |
1108 | } | |
1109 | ||
1110 | result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200); | |
1111 | ||
1112 | if (result > 0) | |
1113 | { | |
1114 | if (phw_data->revision == 0x2002) // 1st-cut | |
1115 | { | |
1116 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1117 | val &= 0x0000FFFF; | |
1118 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1119 | } | |
1120 | else // 2nd-cut | |
1121 | { | |
1122 | hw_get_dxx_reg(phw_data, 0x3C, &val); | |
1123 | val &= 0x000003FF; | |
1124 | hw_set_dxx_reg(phw_data, 0x3C, val); | |
1125 | } | |
1126 | ||
1127 | result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400); | |
1128 | if (result > 0) | |
1129 | { | |
1130 | if (phw_data->revision == 0x2002) // 1st-cut | |
1131 | { | |
1132 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1133 | val &= 0x0000FFFF; | |
1134 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1135 | } | |
1136 | else // 2nd-cut | |
1137 | { | |
1138 | hw_get_dxx_reg(phw_data, 0x3C, &val); | |
1139 | val &= 0x000003FF; | |
1140 | hw_set_dxx_reg(phw_data, 0x3C, val); | |
1141 | } | |
1142 | ||
1143 | ||
1144 | result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500); | |
1145 | ||
1146 | if (result > 0) | |
1147 | { | |
1148 | PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n")); | |
1149 | PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n")); | |
1150 | PHY_DEBUG(("[CAL] **************************************\n")); | |
1151 | ||
1152 | if (phw_data->revision == 0x2002) // 1st-cut | |
1153 | { | |
1154 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1155 | val &= 0x0000FFFF; | |
1156 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1157 | } | |
1158 | else // 2nd-cut | |
1159 | { | |
1160 | hw_get_dxx_reg(phw_data, 0x3C, &val); | |
1161 | val &= 0x000003FF; | |
1162 | hw_set_dxx_reg(phw_data, 0x3C, val); | |
1163 | } | |
1164 | } | |
1165 | } | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | // i. Set "calib_start" to 0x0 | |
1170 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
1171 | reg_mode_ctrl &= ~MASK_CALIB_START; | |
1172 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
1173 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
1174 | ||
1175 | // g. Enable AGC | |
1176 | //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); | |
1177 | reg_agc_ctrl3 |= BIT(2); | |
1178 | reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); | |
1179 | hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); | |
1180 | ||
1181 | #ifdef _DEBUG | |
1182 | if (phw_data->revision == 0x2002) // 1st-cut | |
1183 | { | |
1184 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1185 | PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); | |
1186 | tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); | |
1187 | tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); | |
1188 | tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); | |
1189 | tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); | |
1190 | } | |
1191 | else // 2nd-cut | |
1192 | { | |
1193 | hw_get_dxx_reg(phw_data, 0x3C, &val); | |
1194 | PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); | |
1195 | tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); | |
1196 | tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); | |
1197 | tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); | |
1198 | tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); | |
1199 | ||
1200 | } | |
1201 | ||
1202 | PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0])); | |
1203 | PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1])); | |
1204 | PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); | |
1205 | PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); | |
1206 | #endif | |
1207 | ||
1208 | ||
1209 | // for test - BEN | |
1210 | // RF Control Override | |
1211 | } | |
1212 | ||
1213 | ///////////////////////////////////////////////////////////////////////////////////////// | |
8e41b4b6 | 1214 | u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) |
66101de1 PM |
1215 | { |
1216 | u32 reg_mode_ctrl; | |
1217 | s32 iqcal_tone_i; | |
1218 | s32 iqcal_tone_q; | |
1219 | s32 iqcal_image_i; | |
1220 | s32 iqcal_image_q; | |
1221 | s32 rot_tone_i_b; | |
1222 | s32 rot_tone_q_b; | |
1223 | s32 rot_image_i_b; | |
1224 | s32 rot_image_q_b; | |
1225 | s32 rx_cal_flt_b[4]; | |
1226 | s32 rx_cal[4]; | |
1227 | s32 rx_cal_reg[4]; | |
1228 | s32 a_2, b_2; | |
1229 | s32 sin_b, sin_2b; | |
1230 | s32 cos_b, cos_2b; | |
1231 | s32 temp1, temp2; | |
1232 | u32 val; | |
1233 | u16 loop; | |
1234 | ||
1235 | u32 pwr_tone; | |
1236 | u32 pwr_image; | |
1237 | u8 verify_count; | |
1238 | ||
1239 | s32 iqcal_tone_i_avg,iqcal_tone_q_avg; | |
1240 | s32 iqcal_image_i_avg,iqcal_image_q_avg; | |
1241 | u16 capture_time; | |
1242 | ||
1243 | PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n")); | |
1244 | PHY_DEBUG(("[CAL] ** factor = %d\n", factor)); | |
1245 | ||
1246 | ||
1247 | // RF Control Override | |
1248 | hw_get_cxx_reg(phw_data, 0x80, &val); | |
1249 | val |= BIT(19); | |
1250 | hw_set_cxx_reg(phw_data, 0x80, val); | |
1251 | ||
1252 | // RF_Ctrl | |
1253 | hw_get_cxx_reg(phw_data, 0xE4, &val); | |
1254 | val |= BIT(0); | |
1255 | hw_set_cxx_reg(phw_data, 0xE4, val); | |
1256 | PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val)); | |
1257 | ||
1258 | hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha | |
1259 | ||
1260 | // b. | |
1261 | ||
1262 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
1263 | PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); | |
1264 | ||
1265 | verify_count = 0; | |
1266 | ||
1267 | //for (loop = 0; loop < 1; loop++) | |
1268 | //for (loop = 0; loop < LOOP_TIMES; loop++) | |
1269 | loop = LOOP_TIMES; | |
1270 | while (loop > 0) | |
1271 | { | |
1272 | PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); | |
1273 | iqcal_tone_i_avg=0; | |
1274 | iqcal_tone_q_avg=0; | |
1275 | iqcal_image_i_avg=0; | |
1276 | iqcal_image_q_avg=0; | |
1277 | capture_time=0; | |
1278 | ||
1279 | for(capture_time=0; capture_time<10; capture_time++) | |
1280 | { | |
1281 | // i. Set "calib_start" to 0x0 | |
1282 | reg_mode_ctrl &= ~MASK_CALIB_START; | |
1283 | if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify | |
1284 | return 0; | |
1285 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
66101de1 PM |
1286 | |
1287 | reg_mode_ctrl &= ~MASK_IQCAL_MODE; | |
1288 | reg_mode_ctrl |= (MASK_CALIB_START|0x1); | |
1289 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
1290 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
66101de1 PM |
1291 | |
1292 | // c. | |
1293 | hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); | |
1294 | PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); | |
1295 | ||
1296 | iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); | |
1297 | iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
1298 | PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", | |
1299 | iqcal_tone_i, iqcal_tone_q)); | |
1300 | ||
1301 | hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); | |
1302 | PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); | |
1303 | ||
1304 | iqcal_image_i = _s13_to_s32(val & 0x00001FFF); | |
1305 | iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); | |
1306 | PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n", | |
1307 | iqcal_image_i, iqcal_image_q)); | |
1308 | if( capture_time == 0) | |
1309 | { | |
1310 | continue; | |
1311 | } | |
1312 | else | |
1313 | { | |
1314 | iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time; | |
1315 | iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time; | |
1316 | iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time; | |
1317 | iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | ||
1322 | iqcal_image_i = iqcal_image_i_avg; | |
1323 | iqcal_image_q = iqcal_image_q_avg; | |
1324 | iqcal_tone_i = iqcal_tone_i_avg; | |
1325 | iqcal_tone_q = iqcal_tone_q_avg; | |
1326 | ||
1327 | // d. | |
1328 | rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i + | |
1329 | iqcal_tone_q * iqcal_tone_q) / 1024; | |
1330 | rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) + | |
1331 | iqcal_tone_q * iqcal_tone_i) / 1024; | |
1332 | rot_image_i_b = (iqcal_image_i * iqcal_tone_i - | |
1333 | iqcal_image_q * iqcal_tone_q) / 1024; | |
1334 | rot_image_q_b = (iqcal_image_i * iqcal_tone_q + | |
1335 | iqcal_image_q * iqcal_tone_i) / 1024; | |
1336 | ||
1337 | PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b)); | |
1338 | PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b)); | |
1339 | PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b)); | |
1340 | PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b)); | |
1341 | ||
1342 | // f. | |
1343 | if (rot_tone_i_b == 0) | |
1344 | { | |
1345 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); | |
1346 | PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n")); | |
1347 | PHY_DEBUG(("[CAL] ******************************************\n")); | |
1348 | break; | |
1349 | } | |
1350 | ||
1351 | a_2 = (rot_image_i_b * 32768) / rot_tone_i_b - | |
1352 | phw_data->iq_rsdl_gain_tx_d2; | |
1353 | b_2 = (rot_image_q_b * 32768) / rot_tone_i_b - | |
1354 | phw_data->iq_rsdl_phase_tx_d2; | |
1355 | ||
1356 | PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2)); | |
1357 | PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2)); | |
1358 | PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); | |
1359 | PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); | |
1360 | ||
1361 | _sin_cos(b_2, &sin_b, &cos_b); | |
1362 | _sin_cos(b_2*2, &sin_2b, &cos_2b); | |
1363 | PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); | |
1364 | PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); | |
1365 | ||
1366 | if (cos_2b == 0) | |
1367 | { | |
1368 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); | |
1369 | PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); | |
1370 | PHY_DEBUG(("[CAL] ******************************************\n")); | |
1371 | break; | |
1372 | } | |
1373 | ||
1374 | // 1280 * 32768 = 41943040 | |
1375 | temp1 = (41943040/cos_2b)*cos_b; | |
1376 | ||
1377 | //temp2 = (41943040/cos_2b)*sin_b*(-1); | |
1378 | if (phw_data->revision == 0x2002) // 1st-cut | |
1379 | { | |
1380 | temp2 = (41943040/cos_2b)*sin_b*(-1); | |
1381 | } | |
1382 | else // 2nd-cut | |
1383 | { | |
1384 | temp2 = (41943040*4/cos_2b)*sin_b*(-1); | |
1385 | } | |
1386 | ||
1387 | rx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); | |
1388 | rx_cal_flt_b[1] = _floor(temp2/(32768-a_2)); | |
1389 | rx_cal_flt_b[2] = _floor(temp2/(32768+a_2)); | |
1390 | rx_cal_flt_b[3] = _floor(temp1/(32768-a_2)); | |
1391 | ||
1392 | PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b[0])); | |
1393 | PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b[1])); | |
1394 | PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b[2])); | |
1395 | PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b[3])); | |
1396 | ||
1397 | rx_cal[0] = rx_cal_flt_b[0] - 128; | |
1398 | rx_cal[1] = rx_cal_flt_b[1]; | |
1399 | rx_cal[2] = rx_cal_flt_b[2]; | |
1400 | rx_cal[3] = rx_cal_flt_b[3] - 128; | |
1401 | PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal[0])); | |
1402 | PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal[1])); | |
1403 | PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2])); | |
1404 | PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3])); | |
1405 | ||
1406 | // e. | |
1407 | pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q); | |
1408 | pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor; | |
1409 | ||
1410 | PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone)); | |
1411 | PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image)); | |
1412 | ||
1413 | if (pwr_tone > pwr_image) | |
1414 | { | |
1415 | verify_count++; | |
1416 | ||
1417 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n")); | |
1418 | PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); | |
1419 | PHY_DEBUG(("[CAL] ******************************************\n")); | |
1420 | ||
1421 | if (verify_count > 2) | |
1422 | { | |
1423 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); | |
1424 | PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n")); | |
1425 | PHY_DEBUG(("[CAL] **************************************\n")); | |
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | continue; | |
1430 | } | |
1431 | // g. | |
1432 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1433 | PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); | |
1434 | ||
1435 | if (phw_data->revision == 0x2002) // 1st-cut | |
1436 | { | |
1437 | rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); | |
1438 | rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); | |
1439 | rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); | |
1440 | rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); | |
1441 | } | |
1442 | else // 2nd-cut | |
1443 | { | |
1444 | rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); | |
1445 | rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); | |
1446 | rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); | |
1447 | rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); | |
1448 | } | |
1449 | ||
1450 | PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0])); | |
1451 | PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1])); | |
1452 | PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); | |
1453 | PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); | |
1454 | ||
1455 | if (phw_data->revision == 0x2002) // 1st-cut | |
1456 | { | |
1457 | if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) && | |
1458 | ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8)))) | |
1459 | { | |
1460 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); | |
1461 | PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); | |
1462 | PHY_DEBUG(("[CAL] **************************************\n")); | |
1463 | break; | |
1464 | } | |
1465 | } | |
1466 | else // 2nd-cut | |
1467 | { | |
1468 | if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) && | |
1469 | ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32)))) | |
1470 | { | |
1471 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); | |
1472 | PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); | |
1473 | PHY_DEBUG(("[CAL] **************************************\n")); | |
1474 | break; | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | rx_cal[0] = rx_cal[0] + rx_cal_reg[0]; | |
1479 | rx_cal[1] = rx_cal[1] + rx_cal_reg[1]; | |
1480 | rx_cal[2] = rx_cal[2] + rx_cal_reg[2]; | |
1481 | rx_cal[3] = rx_cal[3] + rx_cal_reg[3]; | |
1482 | PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal[0])); | |
1483 | PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal[1])); | |
1484 | PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal[2])); | |
1485 | PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3])); | |
1486 | ||
1487 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1488 | if (phw_data->revision == 0x2002) // 1st-cut | |
1489 | { | |
1490 | val &= 0x0000FFFF; | |
1491 | val |= ((_s32_to_s4(rx_cal[0]) << 12)| | |
1492 | (_s32_to_s4(rx_cal[1]) << 8)| | |
1493 | (_s32_to_s4(rx_cal[2]) << 4)| | |
1494 | (_s32_to_s4(rx_cal[3]))); | |
1495 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1496 | } | |
1497 | else // 2nd-cut | |
1498 | { | |
1499 | val &= 0x000003FF; | |
1500 | val |= ((_s32_to_s5(rx_cal[0]) << 27)| | |
1501 | (_s32_to_s6(rx_cal[1]) << 21)| | |
1502 | (_s32_to_s6(rx_cal[2]) << 15)| | |
1503 | (_s32_to_s5(rx_cal[3]) << 10)); | |
1504 | hw_set_dxx_reg(phw_data, 0x54, val); | |
1505 | ||
1506 | if( loop == 3 ) | |
1507 | return 0; | |
1508 | } | |
1509 | PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); | |
1510 | ||
1511 | loop--; | |
1512 | } | |
1513 | ||
1514 | return 1; | |
1515 | } | |
1516 | ||
1517 | ////////////////////////////////////////////////////////// | |
1518 | ||
1519 | ////////////////////////////////////////////////////////////////////////// | |
8e41b4b6 | 1520 | void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) |
66101de1 PM |
1521 | { |
1522 | // figo 20050523 marked thsi flag for can't compile for relesase | |
1523 | #ifdef _DEBUG | |
1524 | s32 rx_cal_reg[4]; | |
1525 | u32 val; | |
1526 | #endif | |
1527 | ||
1528 | u8 result; | |
1529 | ||
1530 | PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n")); | |
1531 | // a. Set RFIC to "RX calibration mode" | |
1532 | //; ----- Calibration (7). RX path IQ imbalance calibration loop | |
1533 | // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits | |
1534 | phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2); | |
1535 | // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit | |
1536 | phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6); | |
1537 | //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized | |
1538 | phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal); | |
1539 | //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized | |
1540 | phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C); | |
1541 | //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode | |
1542 | phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0); | |
1543 | ||
1544 | // ; [BB-chip]: Calibration (7f). Send test pattern | |
1545 | // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value | |
1546 | // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table | |
1547 | ||
1548 | result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency); | |
1549 | ||
1550 | if (result > 0) | |
1551 | { | |
1552 | _reset_rx_cal(phw_data); | |
1553 | result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency); | |
1554 | ||
1555 | if (result > 0) | |
1556 | { | |
1557 | _reset_rx_cal(phw_data); | |
1558 | result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency); | |
1559 | ||
1560 | if (result > 0) | |
1561 | { | |
1562 | PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n")); | |
1563 | PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n")); | |
1564 | PHY_DEBUG(("[CAL] **************************************\n")); | |
1565 | _reset_rx_cal(phw_data); | |
1566 | } | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | #ifdef _DEBUG | |
1571 | hw_get_dxx_reg(phw_data, 0x54, &val); | |
1572 | PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); | |
1573 | ||
1574 | if (phw_data->revision == 0x2002) // 1st-cut | |
1575 | { | |
1576 | rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); | |
1577 | rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); | |
1578 | rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); | |
1579 | rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); | |
1580 | } | |
1581 | else // 2nd-cut | |
1582 | { | |
1583 | rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); | |
1584 | rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); | |
1585 | rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); | |
1586 | rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); | |
1587 | } | |
1588 | ||
1589 | PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0])); | |
1590 | PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1])); | |
1591 | PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); | |
1592 | PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); | |
1593 | #endif | |
1594 | ||
1595 | } | |
1596 | ||
1597 | //////////////////////////////////////////////////////////////////////// | |
8e41b4b6 | 1598 | void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency) |
66101de1 PM |
1599 | { |
1600 | u32 reg_mode_ctrl; | |
1601 | u32 iq_alpha; | |
1602 | ||
1603 | PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n")); | |
1604 | ||
1605 | // 20040701 1.1.25.1000 kevin | |
1606 | hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl); | |
1607 | hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl); | |
1608 | hw_get_dxx_reg(phw_data, 0x58, &iq_alpha); | |
1609 | ||
1610 | ||
1611 | ||
1612 | _rxadc_dc_offset_cancellation_winbond(phw_data, frequency); | |
1613 | //_txidac_dc_offset_cancellation_winbond(phw_data); | |
1614 | //_txqdac_dc_offset_cacellation_winbond(phw_data); | |
1615 | ||
1616 | _tx_iq_calibration_winbond(phw_data); | |
1617 | _rx_iq_calibration_winbond(phw_data, frequency); | |
1618 | ||
1619 | //------------------------------------------------------------------------ | |
1620 | hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); | |
1621 | reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish | |
1622 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
1623 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
1624 | ||
1625 | // i. Set RFIC to "Normal mode" | |
1626 | hw_set_cxx_reg(phw_data, 0x80, mac_ctrl); | |
1627 | hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl); | |
1628 | hw_set_dxx_reg(phw_data, 0x58, iq_alpha); | |
1629 | ||
1630 | ||
1631 | //------------------------------------------------------------------------ | |
1632 | phy_init_rf(phw_data); | |
1633 | ||
1634 | } | |
1635 | ||
1636 | //=========================== | |
8e41b4b6 | 1637 | void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value ) |
66101de1 PM |
1638 | { |
1639 | u32 ltmp=0; | |
1640 | ||
1641 | switch( pHwData->phy_type ) | |
1642 | { | |
1643 | case RF_MAXIM_2825: | |
1644 | case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) | |
1645 | ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); | |
1646 | break; | |
1647 | ||
1648 | case RF_MAXIM_2827: | |
1649 | ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); | |
1650 | break; | |
1651 | ||
1652 | case RF_MAXIM_2828: | |
1653 | ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); | |
1654 | break; | |
1655 | ||
1656 | case RF_MAXIM_2829: | |
1657 | ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); | |
1658 | break; | |
1659 | ||
1660 | case RF_AIROHA_2230: | |
1661 | case RF_AIROHA_2230S: // 20060420 Add this | |
1662 | ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 ); | |
1663 | break; | |
1664 | ||
1665 | case RF_AIROHA_7230: | |
1666 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff); | |
1667 | break; | |
1668 | ||
1669 | case RF_WB_242: | |
1670 | case RF_WB_242_1: // 20060619.5 Add | |
1671 | ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 ); | |
1672 | break; | |
1673 | } | |
1674 | ||
1675 | Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); | |
1676 | } | |
1677 | ||
1678 | // 20060717 modify as Bruce's mail | |
8e41b4b6 | 1679 | unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) |
66101de1 PM |
1680 | { |
1681 | int init_txvga = 0; | |
1682 | u32 reg_mode_ctrl; | |
1683 | u32 val; | |
1684 | s32 iqcal_tone_i0; | |
1685 | s32 iqcal_tone_q0; | |
1686 | u32 sqsum; | |
1687 | s32 iq_mag_0_tx; | |
1688 | u8 reg_state; | |
1689 | int current_txvga; | |
1690 | ||
1691 | ||
1692 | reg_state = 0; | |
1693 | for( init_txvga=0; init_txvga<10; init_txvga++) | |
1694 | { | |
1695 | current_txvga = ( 0x24C40A|(init_txvga<<6) ); | |
1696 | phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) ); | |
1697 | phw_data->txvga_setting_for_cal = current_txvga; | |
1698 | ||
34222e0a | 1699 | msleep(30); // 20060612.1.a |
66101de1 PM |
1700 | |
1701 | if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl) ) // 20060718.1 modify | |
279b6ccc | 1702 | return false; |
66101de1 PM |
1703 | |
1704 | PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); | |
1705 | ||
1706 | // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to | |
1707 | // enable "IQ alibration Mode II" | |
1708 | reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); | |
1709 | reg_mode_ctrl &= ~MASK_IQCAL_MODE; | |
1710 | reg_mode_ctrl |= (MASK_CALIB_START|0x02); | |
1711 | reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2); | |
1712 | hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); | |
1713 | PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); | |
1714 | ||
34222e0a | 1715 | udelay(1); // 20060612.1.a |
66101de1 | 1716 | |
34222e0a | 1717 | udelay(300); // 20060612.1.a |
66101de1 PM |
1718 | |
1719 | // b. | |
1720 | hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); | |
1721 | ||
1722 | PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); | |
34222e0a | 1723 | udelay(300); // 20060612.1.a |
66101de1 PM |
1724 | |
1725 | iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); | |
1726 | iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); | |
1727 | PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n", | |
1728 | iqcal_tone_i0, iqcal_tone_q0)); | |
1729 | ||
1730 | sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0; | |
1731 | iq_mag_0_tx = (s32) _sqrt(sqsum); | |
1732 | PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx)); | |
1733 | ||
1734 | if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) | |
1735 | break; | |
1736 | else if(iq_mag_0_tx > 1750) | |
1737 | { | |
1738 | init_txvga=-2; | |
1739 | continue; | |
1740 | } | |
1741 | else | |
1742 | continue; | |
1743 | ||
1744 | } | |
1745 | ||
1746 | if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) | |
279b6ccc | 1747 | return true; |
66101de1 | 1748 | else |
279b6ccc | 1749 | return false; |
66101de1 PM |
1750 | } |
1751 | ||
1752 | ||
1753 |