Merge tag 'staging-3.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / vt6656 / upc.h
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1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * File: upc.h
20 *
21 * Purpose: Macros to access device
22 *
23 * Author: Tevin Chen
24 *
25 * Date: Mar 17, 1997
26 *
27 */
28
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29#ifndef __UPC_H__
30#define __UPC_H__
31
92b96797 32#include "device.h"
92b96797 33#include "ttype.h"
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34
35/*--------------------- Export Definitions -------------------------*/
36
37
38//
39// For IO mapped
40//
41
42#ifdef IO_MAP
43
44#define VNSvInPortB(dwIOAddress, pbyData) { \
45 *(pbyData) = inb(dwIOAddress); \
46}
47
48
49#define VNSvInPortW(dwIOAddress, pwData) { \
50 *(pwData) = inw(dwIOAddress); \
51}
52
53#define VNSvInPortD(dwIOAddress, pdwData) { \
54 *(pdwData) = inl(dwIOAddress); \
55}
56
57
58#define VNSvOutPortB(dwIOAddress, byData) { \
59 outb(byData, dwIOAddress); \
60}
61
62
63#define VNSvOutPortW(dwIOAddress, wData) { \
64 outw(wData, dwIOAddress); \
65}
66
67#define VNSvOutPortD(dwIOAddress, dwData) { \
68 outl(dwData, dwIOAddress); \
69}
70
71#else
72
73//
74// For memory mapped IO
75//
76
77
78#define VNSvInPortB(dwIOAddress, pbyData) { \
79 volatile BYTE* pbyAddr = ((PBYTE)(dwIOAddress)); \
80 *(pbyData) = readb(pbyAddr); \
81}
82
83
84#define VNSvInPortW(dwIOAddress, pwData) { \
85 volatile WORD* pwAddr = ((PWORD)(dwIOAddress)); \
86 *(pwData) = readw(pwAddr); \
87}
88
89#define VNSvInPortD(dwIOAddress, pdwData) { \
90 volatile DWORD* pdwAddr = ((PDWORD)(dwIOAddress)); \
91 *(pdwData) = readl(pdwAddr); \
92}
93
94
95#define VNSvOutPortB(dwIOAddress, byData) { \
96 volatile BYTE* pbyAddr = ((PBYTE)(dwIOAddress)); \
97 writeb((BYTE)byData, pbyAddr); \
98}
99
100
101#define VNSvOutPortW(dwIOAddress, wData) { \
102 volatile WORD* pwAddr = ((PWORD)(dwIOAddress)); \
103 writew((WORD)wData, pwAddr); \
104}
105
106#define VNSvOutPortD(dwIOAddress, dwData) { \
107 volatile DWORD* pdwAddr = ((PDWORD)(dwIOAddress)); \
108 writel((DWORD)dwData, pdwAddr); \
109}
110
111#endif
112
113
114//
115// ALWAYS IO-Mapped IO when in 16-bit/32-bit environment
116//
117#define PCBvInPortB(dwIOAddress, pbyData) { \
118 *(pbyData) = inb(dwIOAddress); \
119}
120
121#define PCBvInPortW(dwIOAddress, pwData) { \
122 *(pwData) = inw(dwIOAddress); \
123}
124
125#define PCBvInPortD(dwIOAddress, pdwData) { \
126 *(pdwData) = inl(dwIOAddress); \
127}
128
129#define PCBvOutPortB(dwIOAddress, byData) { \
130 outb(byData, dwIOAddress); \
131}
132
133#define PCBvOutPortW(dwIOAddress, wData) { \
134 outw(wData, dwIOAddress); \
135}
136
137#define PCBvOutPortD(dwIOAddress, dwData) { \
138 outl(dwData, dwIOAddress); \
139}
140
141
142#define PCAvDelayByIO(uDelayUnit) { \
143 BYTE byData; \
cc856e61 144 unsigned long ii; \
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145 \
146 if (uDelayUnit <= 50) { \
147 udelay(uDelayUnit); \
148 } \
149 else { \
150 for (ii = 0; ii < (uDelayUnit); ii++) \
151 byData = inb(0x61); \
152 } \
153}
154
155
156/*--------------------- Export Classes ----------------------------*/
157
158/*--------------------- Export Variables --------------------------*/
159
160/*--------------------- Export Functions --------------------------*/
161
e7b07d1d 162#endif /* __UPC_H__ */