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1 | /* |
2 | * ca91c042.h | |
3 | * | |
4 | * Support for the Tundra Universe 1 and Universe II VME bridge chips | |
5 | * | |
6 | * Author: Tom Armistead | |
3d0f8bc7 | 7 | * Updated by Ajit Prem |
60479690 MW |
8 | * Copyright 2004 Motorola Inc. |
9 | * | |
66bd8db5 MW |
10 | * Further updated by Martyn Welch <martyn.welch@ge.com> |
11 | * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc. | |
3d0f8bc7 | 12 | * |
60479690 MW |
13 | * Derived from ca91c042.h by Michael Wyrick |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | */ | |
20 | ||
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21 | #ifndef _CA91CX42_H |
22 | #define _CA91CX42_H | |
60479690 MW |
23 | |
24 | #ifndef PCI_VENDOR_ID_TUNDRA | |
25 | #define PCI_VENDOR_ID_TUNDRA 0x10e3 | |
26 | #endif | |
27 | ||
3d0f8bc7 MW |
28 | #ifndef PCI_DEVICE_ID_TUNDRA_CA91C142 |
29 | #define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000 | |
60479690 MW |
30 | #endif |
31 | ||
60479690 | 32 | /* |
3d0f8bc7 | 33 | * Define the number of each that the CA91C142 supports. |
60479690 | 34 | */ |
3d0f8bc7 MW |
35 | #define CA91C142_MAX_MASTER 8 /* Max Master Windows */ |
36 | #define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */ | |
37 | #define CA91C142_MAX_DMA 1 /* Max DMA Controllers */ | |
38 | #define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */ | |
39 | ||
29848ac9 MW |
40 | /* Structure used to hold driver specific information */ |
41 | struct ca91cx42_driver { | |
42 | void *base; /* Base Address of device registers */ | |
43 | wait_queue_head_t dma_queue; | |
44 | wait_queue_head_t iack_queue; | |
45 | wait_queue_head_t mbox_queue; | |
46 | void (*lm_callback[4])(int); /* Called in interrupt handler */ | |
47 | void *crcsr_kernel; | |
48 | dma_addr_t crcsr_bus; | |
49 | struct mutex vme_rmw; /* Only one RMW cycle at a time */ | |
50 | struct mutex vme_int; /* | |
51 | * Only one VME interrupt can be | |
52 | * generated at a time, provide locking | |
53 | */ | |
54 | }; | |
55 | ||
3d0f8bc7 MW |
56 | /* See Page 2-77 in the Universe User Manual */ |
57 | struct ca91cx42_dma_descriptor { | |
58 | unsigned int dctl; /* DMA Control */ | |
59 | unsigned int dtbc; /* Transfer Byte Count */ | |
60 | unsigned int dlv; /* PCI Address */ | |
61 | unsigned int res1; /* Reserved */ | |
62 | unsigned int dva; /* Vme Address */ | |
63 | unsigned int res2; /* Reserved */ | |
64 | unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ | |
65 | unsigned int res3; /* Reserved */ | |
66 | }; | |
67 | ||
68 | struct ca91cx42_dma_entry { | |
69 | struct ca91cx42_dma_descriptor descriptor; | |
70 | struct list_head list; | |
71 | }; | |
60479690 MW |
72 | |
73 | /* Universe Register Offsets */ | |
74 | /* general PCI configuration registers */ | |
3d0f8bc7 MW |
75 | #define CA91CX42_PCI_ID 0x000 |
76 | #define CA91CX42_PCI_CSR 0x004 | |
77 | #define CA91CX42_PCI_CLASS 0x008 | |
78 | #define CA91CX42_PCI_MISC0 0x00C | |
79 | #define CA91CX42_PCI_BS 0x010 | |
80 | #define CA91CX42_PCI_MISC1 0x03C | |
81 | ||
82 | #define LSI0_CTL 0x0100 | |
83 | #define LSI0_BS 0x0104 | |
84 | #define LSI0_BD 0x0108 | |
85 | #define LSI0_TO 0x010C | |
86 | ||
87 | #define LSI1_CTL 0x0114 | |
88 | #define LSI1_BS 0x0118 | |
89 | #define LSI1_BD 0x011C | |
90 | #define LSI1_TO 0x0120 | |
91 | ||
92 | #define LSI2_CTL 0x0128 | |
93 | #define LSI2_BS 0x012C | |
94 | #define LSI2_BD 0x0130 | |
95 | #define LSI2_TO 0x0134 | |
96 | ||
97 | #define LSI3_CTL 0x013C | |
98 | #define LSI3_BS 0x0140 | |
99 | #define LSI3_BD 0x0144 | |
100 | #define LSI3_TO 0x0148 | |
101 | ||
102 | #define LSI4_CTL 0x01A0 | |
103 | #define LSI4_BS 0x01A4 | |
104 | #define LSI4_BD 0x01A8 | |
105 | #define LSI4_TO 0x01AC | |
106 | ||
107 | #define LSI5_CTL 0x01B4 | |
108 | #define LSI5_BS 0x01B8 | |
109 | #define LSI5_BD 0x01BC | |
110 | #define LSI5_TO 0x01C0 | |
111 | ||
112 | #define LSI6_CTL 0x01C8 | |
113 | #define LSI6_BS 0x01CC | |
114 | #define LSI6_BD 0x01D0 | |
115 | #define LSI6_TO 0x01D4 | |
116 | ||
117 | #define LSI7_CTL 0x01DC | |
118 | #define LSI7_BS 0x01E0 | |
119 | #define LSI7_BD 0x01E4 | |
120 | #define LSI7_TO 0x01E8 | |
121 | ||
122 | static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL, | |
123 | LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL }; | |
124 | ||
125 | static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS, | |
126 | LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS }; | |
127 | ||
128 | static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD, | |
129 | LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD }; | |
130 | ||
131 | static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO, | |
132 | LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO }; | |
60479690 MW |
133 | |
134 | #define SCYC_CTL 0x0170 | |
135 | #define SCYC_ADDR 0x0174 | |
136 | #define SCYC_EN 0x0178 | |
137 | #define SCYC_CMP 0x017C | |
138 | #define SCYC_SWP 0x0180 | |
139 | #define LMISC 0x0184 | |
60479690 | 140 | #define SLSI 0x0188 |
60479690 MW |
141 | #define L_CMDERR 0x018C |
142 | #define LAERR 0x0190 | |
143 | ||
144 | #define DCTL 0x0200 | |
145 | #define DTBC 0x0204 | |
146 | #define DLA 0x0208 | |
147 | #define DVA 0x0210 | |
148 | #define DCPP 0x0218 | |
149 | #define DGCS 0x0220 | |
150 | #define D_LLUE 0x0224 | |
151 | ||
3d0f8bc7 MW |
152 | #define LINT_EN 0x0300 |
153 | #define LINT_STAT 0x0304 | |
154 | #define LINT_MAP0 0x0308 | |
155 | #define LINT_MAP1 0x030C | |
156 | #define VINT_EN 0x0310 | |
157 | #define VINT_STAT 0x0314 | |
158 | #define VINT_MAP0 0x0318 | |
159 | #define VINT_MAP1 0x031C | |
160 | #define STATID 0x0320 | |
161 | ||
162 | #define V1_STATID 0x0324 | |
163 | #define V2_STATID 0x0328 | |
164 | #define V3_STATID 0x032C | |
165 | #define V4_STATID 0x0330 | |
166 | #define V5_STATID 0x0334 | |
167 | #define V6_STATID 0x0338 | |
168 | #define V7_STATID 0x033C | |
169 | ||
170 | static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID, | |
171 | V4_STATID, V5_STATID, V6_STATID, | |
172 | V7_STATID }; | |
173 | ||
174 | #define LINT_MAP2 0x0340 | |
175 | #define VINT_MAP2 0x0344 | |
176 | ||
177 | #define MBOX0 0x0348 | |
178 | #define MBOX1 0x034C | |
179 | #define MBOX2 0x0350 | |
180 | #define MBOX3 0x0354 | |
181 | #define SEMA0 0x0358 | |
182 | #define SEMA1 0x035C | |
183 | ||
184 | #define MAST_CTL 0x0400 | |
185 | #define MISC_CTL 0x0404 | |
186 | #define MISC_STAT 0x0408 | |
187 | #define USER_AM 0x040C | |
188 | ||
189 | #define VSI0_CTL 0x0F00 | |
190 | #define VSI0_BS 0x0F04 | |
191 | #define VSI0_BD 0x0F08 | |
192 | #define VSI0_TO 0x0F0C | |
193 | ||
194 | #define VSI1_CTL 0x0F14 | |
195 | #define VSI1_BS 0x0F18 | |
196 | #define VSI1_BD 0x0F1C | |
197 | #define VSI1_TO 0x0F20 | |
198 | ||
199 | #define VSI2_CTL 0x0F28 | |
200 | #define VSI2_BS 0x0F2C | |
201 | #define VSI2_BD 0x0F30 | |
202 | #define VSI2_TO 0x0F34 | |
203 | ||
204 | #define VSI3_CTL 0x0F3C | |
205 | #define VSI3_BS 0x0F40 | |
206 | #define VSI3_BD 0x0F44 | |
207 | #define VSI3_TO 0x0F48 | |
208 | ||
209 | #define LM_CTL 0x0F64 | |
210 | #define LM_BS 0x0F68 | |
211 | ||
212 | #define VRAI_CTL 0x0F70 | |
213 | ||
214 | #define VRAI_BS 0x0F74 | |
215 | #define VCSR_CTL 0x0F80 | |
216 | #define VCSR_TO 0x0F84 | |
217 | #define V_AMERR 0x0F88 | |
60479690 MW |
218 | #define VAERR 0x0F8C |
219 | ||
3d0f8bc7 MW |
220 | #define VSI4_CTL 0x0F90 |
221 | #define VSI4_BS 0x0F94 | |
222 | #define VSI4_BD 0x0F98 | |
223 | #define VSI4_TO 0x0F9C | |
224 | ||
225 | #define VSI5_CTL 0x0FA4 | |
226 | #define VSI5_BS 0x0FA8 | |
227 | #define VSI5_BD 0x0FAC | |
228 | #define VSI5_TO 0x0FB0 | |
229 | ||
230 | #define VSI6_CTL 0x0FB8 | |
231 | #define VSI6_BS 0x0FBC | |
232 | #define VSI6_BD 0x0FC0 | |
233 | #define VSI6_TO 0x0FC4 | |
234 | ||
235 | #define VSI7_CTL 0x0FCC | |
236 | #define VSI7_BS 0x0FD0 | |
237 | #define VSI7_BD 0x0FD4 | |
238 | #define VSI7_TO 0x0FD8 | |
239 | ||
240 | static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL, | |
241 | VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL }; | |
60479690 | 242 | |
3d0f8bc7 MW |
243 | static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS, |
244 | VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS }; | |
60479690 | 245 | |
3d0f8bc7 MW |
246 | static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD, |
247 | VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD }; | |
60479690 | 248 | |
3d0f8bc7 MW |
249 | static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO, |
250 | VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO }; | |
60479690 | 251 | |
3d0f8bc7 MW |
252 | #define VCSR_CLR 0x0FF4 |
253 | #define VCSR_SET 0x0FF8 | |
254 | #define VCSR_BS 0x0FFC | |
60479690 MW |
255 | |
256 | // DMA General Control/Status Register DGCS (0x220) | |
257 | // 32-24 || GO | STOPR | HALTR | 0 || CHAIN | 0 | 0 | 0 || | |
258 | // 23-16 || VON || VOFF || | |
259 | // 15-08 || ACT | STOP | HALT | 0 || DONE | LERR | VERR | P_ERR || | |
260 | // 07-00 || 0 | INT_S | INT_H | 0 || I_DNE | I_LER | I_VER | I_PER || | |
261 | ||
262 | // VON - Length Per DMA VMEBus Transfer | |
263 | // 0000 = None | |
264 | // 0001 = 256 Bytes | |
265 | // 0010 = 512 | |
266 | // 0011 = 1024 | |
267 | // 0100 = 2048 | |
268 | // 0101 = 4096 | |
269 | // 0110 = 8192 | |
270 | // 0111 = 16384 | |
271 | ||
272 | // VOFF - wait between DMA tenures | |
273 | // 0000 = 0 us | |
274 | // 0001 = 16 | |
275 | // 0010 = 32 | |
276 | // 0011 = 64 | |
277 | // 0100 = 128 | |
278 | // 0101 = 256 | |
279 | // 0110 = 512 | |
280 | // 0111 = 1024 | |
281 | ||
3d0f8bc7 MW |
282 | /* |
283 | * PCI Class Register | |
284 | * offset 008 | |
285 | */ | |
286 | #define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000 | |
287 | #define CA91CX42_OF_PCI_CLASS_BASE 24 | |
288 | #define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000 | |
289 | #define CA91CX42_OF_PCI_CLASS_SUB 16 | |
290 | #define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00 | |
291 | #define CA91CX42_OF_PCI_CLASS_PROG 8 | |
292 | #define CA91CX42_BM_PCI_CLASS_RID 0x000000FF | |
293 | #define CA91CX42_OF_PCI_CLASS_RID 0 | |
294 | ||
295 | #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0 | |
296 | #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1 | |
297 | ||
298 | /* | |
299 | * PCI Misc Register | |
300 | * offset 00C | |
301 | */ | |
302 | #define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000 | |
303 | #define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000 | |
304 | #define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000 | |
305 | #define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000 | |
306 | #define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000 | |
307 | #define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00 | |
308 | #define CA91CX42_OF_PCI_MISC0_LTIMER 8 | |
309 | ||
310 | ||
311 | /* | |
312 | * LSI Control Register | |
313 | * offset 100 | |
314 | */ | |
315 | #define CA91CX42_LSI_CTL_EN (1<<31) | |
316 | #define CA91CX42_LSI_CTL_PWEN (1<<30) | |
317 | ||
318 | #define CA91CX42_LSI_CTL_VDW_M (3<<22) | |
319 | #define CA91CX42_LSI_CTL_VDW_D8 0 | |
320 | #define CA91CX42_LSI_CTL_VDW_D16 (1<<22) | |
321 | #define CA91CX42_LSI_CTL_VDW_D32 (1<<23) | |
322 | #define CA91CX42_LSI_CTL_VDW_D64 (3<<22) | |
323 | ||
324 | #define CA91CX42_LSI_CTL_VAS_M (7<<16) | |
325 | #define CA91CX42_LSI_CTL_VAS_A16 0 | |
326 | #define CA91CX42_LSI_CTL_VAS_A24 (1<<16) | |
327 | #define CA91CX42_LSI_CTL_VAS_A32 (1<<17) | |
328 | #define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16) | |
329 | #define CA91CX42_LSI_CTL_VAS_USER1 (3<<17) | |
330 | #define CA91CX42_LSI_CTL_VAS_USER2 (7<<16) | |
331 | ||
332 | #define CA91CX42_LSI_CTL_PGM_M (1<<14) | |
333 | #define CA91CX42_LSI_CTL_PGM_DATA 0 | |
334 | #define CA91CX42_LSI_CTL_PGM_PGM (1<<14) | |
335 | ||
336 | #define CA91CX42_LSI_CTL_SUPER_M (1<<12) | |
337 | #define CA91CX42_LSI_CTL_SUPER_NPRIV 0 | |
338 | #define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12) | |
339 | ||
340 | #define CA91CX42_LSI_CTL_VCT_M (1<<8) | |
341 | #define CA91CX42_LSI_CTL_VCT_BLT (1<<8) | |
342 | #define CA91CX42_LSI_CTL_VCT_MBLT (1<<8) | |
343 | #define CA91CX42_LSI_CTL_LAS (1<<0) | |
344 | ||
345 | ||
346 | /* | |
347 | * LMISC Register | |
348 | * offset 184 | |
349 | */ | |
350 | #define CA91CX42_BM_LMISC_CRT 0xF0000000 | |
351 | #define CA91CX42_OF_LMISC_CRT 28 | |
352 | #define CA91CX42_BM_LMISC_CWT 0x0F000000 | |
353 | #define CA91CX42_OF_LMISC_CWT 24 | |
354 | ||
355 | /* | |
356 | * SLSI Register | |
357 | * offset 188 | |
358 | */ | |
359 | #define CA91CX42_BM_SLSI_EN 0x80000000 | |
360 | #define CA91CX42_BM_SLSI_PWEN 0x40000000 | |
361 | #define CA91CX42_BM_SLSI_VDW 0x00F00000 | |
362 | #define CA91CX42_OF_SLSI_VDW 20 | |
363 | #define CA91CX42_BM_SLSI_PGM 0x0000F000 | |
364 | #define CA91CX42_OF_SLSI_PGM 12 | |
365 | #define CA91CX42_BM_SLSI_SUPER 0x00000F00 | |
366 | #define CA91CX42_OF_SLSI_SUPER 8 | |
367 | #define CA91CX42_BM_SLSI_BS 0x000000F6 | |
368 | #define CA91CX42_OF_SLSI_BS 2 | |
369 | #define CA91CX42_BM_SLSI_LAS 0x00000003 | |
370 | #define CA91CX42_OF_SLSI_LAS 0 | |
371 | #define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000 | |
372 | ||
373 | /* | |
374 | * PCI Interrupt Enable Register | |
375 | * offset 300 | |
376 | */ | |
377 | #define CA91CX42_LINT_LM3 0x00800000 | |
378 | #define CA91CX42_LINT_LM2 0x00400000 | |
379 | #define CA91CX42_LINT_LM1 0x00200000 | |
380 | #define CA91CX42_LINT_LM0 0x00100000 | |
381 | #define CA91CX42_LINT_MBOX3 0x00080000 | |
382 | #define CA91CX42_LINT_MBOX2 0x00040000 | |
383 | #define CA91CX42_LINT_MBOX1 0x00020000 | |
384 | #define CA91CX42_LINT_MBOX0 0x00010000 | |
385 | #define CA91CX42_LINT_ACFAIL 0x00008000 | |
386 | #define CA91CX42_LINT_SYSFAIL 0x00004000 | |
387 | #define CA91CX42_LINT_SW_INT 0x00002000 | |
388 | #define CA91CX42_LINT_SW_IACK 0x00001000 | |
389 | ||
390 | #define CA91CX42_LINT_VERR 0x00000400 | |
391 | #define CA91CX42_LINT_LERR 0x00000200 | |
392 | #define CA91CX42_LINT_DMA 0x00000100 | |
393 | #define CA91CX42_LINT_VIRQ7 0x00000080 | |
394 | #define CA91CX42_LINT_VIRQ6 0x00000040 | |
395 | #define CA91CX42_LINT_VIRQ5 0x00000020 | |
396 | #define CA91CX42_LINT_VIRQ4 0x00000010 | |
397 | #define CA91CX42_LINT_VIRQ3 0x00000008 | |
398 | #define CA91CX42_LINT_VIRQ2 0x00000004 | |
399 | #define CA91CX42_LINT_VIRQ1 0x00000002 | |
400 | #define CA91CX42_LINT_VOWN 0x00000001 | |
401 | ||
402 | static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1, | |
403 | CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3, | |
404 | CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5, | |
405 | CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 }; | |
406 | ||
407 | #define CA91CX42_LINT_MBOX 0x000F0000 | |
408 | ||
409 | static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1, | |
410 | CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 }; | |
411 | ||
412 | /* | |
413 | * MAST_CTL Register | |
414 | * offset 400 | |
415 | */ | |
416 | #define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000 | |
417 | #define CA91CX42_OF_MAST_CTL_MAXRTRY 28 | |
418 | #define CA91CX42_BM_MAST_CTL_PWON 0x0F000000 | |
419 | #define CA91CX42_OF_MAST_CTL_PWON 24 | |
420 | #define CA91CX42_BM_MAST_CTL_VRL 0x00C00000 | |
421 | #define CA91CX42_OF_MAST_CTL_VRL 22 | |
422 | #define CA91CX42_BM_MAST_CTL_VRM 0x00200000 | |
423 | #define CA91CX42_BM_MAST_CTL_VREL 0x00100000 | |
424 | #define CA91CX42_BM_MAST_CTL_VOWN 0x00080000 | |
425 | #define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000 | |
426 | #define CA91CX42_BM_MAST_CTL_PABS 0x00001000 | |
427 | #define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F | |
428 | #define CA91CX42_OF_MAST_CTL_BUS_NO 0 | |
429 | ||
430 | /* | |
431 | * MISC_CTL Register | |
432 | * offset 404 | |
433 | */ | |
434 | #define CA91CX42_MISC_CTL_VBTO 0xF0000000 | |
435 | #define CA91CX42_MISC_CTL_VARB 0x04000000 | |
436 | #define CA91CX42_MISC_CTL_VARBTO 0x03000000 | |
437 | #define CA91CX42_MISC_CTL_SW_LRST 0x00800000 | |
438 | #define CA91CX42_MISC_CTL_SW_SRST 0x00400000 | |
439 | #define CA91CX42_MISC_CTL_BI 0x00100000 | |
440 | #define CA91CX42_MISC_CTL_ENGBI 0x00080000 | |
441 | #define CA91CX42_MISC_CTL_RESCIND 0x00040000 | |
442 | #define CA91CX42_MISC_CTL_SYSCON 0x00020000 | |
443 | #define CA91CX42_MISC_CTL_V64AUTO 0x00010000 | |
444 | #define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF | |
445 | ||
446 | #define CA91CX42_OF_MISC_CTL_VARBTO 24 | |
447 | #define CA91CX42_OF_MISC_CTL_VBTO 28 | |
448 | ||
449 | /* | |
450 | * MISC_STAT Register | |
451 | * offset 408 | |
452 | */ | |
453 | #define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000 | |
454 | #define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000 | |
455 | #define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000 | |
456 | #define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000 | |
457 | #define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000 | |
458 | #define CA91CX42_BM_MISC_STAT_TXFE 0x00040000 | |
459 | #define CA91CX42_BM_MISC_STAT_RXFE 0x00020000 | |
460 | #define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00 | |
461 | #define CA91CX42_OF_MISC_STAT_DY4AUTOID 8 | |
462 | ||
463 | /* | |
464 | * VSI Control Register | |
465 | * offset F00 | |
466 | */ | |
467 | #define CA91CX42_VSI_CTL_EN (1<<31) | |
468 | #define CA91CX42_VSI_CTL_PWEN (1<<30) | |
469 | #define CA91CX42_VSI_CTL_PREN (1<<29) | |
470 | ||
471 | #define CA91CX42_VSI_CTL_PGM_M (3<<22) | |
472 | #define CA91CX42_VSI_CTL_PGM_DATA (1<<22) | |
473 | #define CA91CX42_VSI_CTL_PGM_PGM (1<<23) | |
474 | ||
475 | #define CA91CX42_VSI_CTL_SUPER_M (3<<20) | |
476 | #define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20) | |
477 | #define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21) | |
478 | ||
479 | #define CA91CX42_VSI_CTL_VAS_M (7<<16) | |
480 | #define CA91CX42_VSI_CTL_VAS_A16 0 | |
481 | #define CA91CX42_VSI_CTL_VAS_A24 (1<<16) | |
482 | #define CA91CX42_VSI_CTL_VAS_A32 (1<<17) | |
483 | #define CA91CX42_VSI_CTL_VAS_USER1 (3<<17) | |
484 | #define CA91CX42_VSI_CTL_VAS_USER2 (7<<16) | |
485 | ||
486 | #define CA91CX42_VSI_CTL_LD64EN (1<<7) | |
487 | #define CA91CX42_VSI_CTL_LLRMW (1<<6) | |
488 | ||
489 | #define CA91CX42_VSI_CTL_LAS_M (3<<0) | |
490 | #define CA91CX42_VSI_CTL_LAS_PCI_MS 0 | |
491 | #define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0) | |
492 | #define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1) | |
493 | ||
494 | /* | |
495 | * VRAI_CTL Register | |
496 | * offset F70 | |
497 | */ | |
498 | #define CA91CX42_BM_VRAI_CTL_EN 0x80000000 | |
499 | #define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000 | |
500 | #define CA91CX42_OF_VRAI_CTL_PGM 22 | |
501 | #define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000 | |
502 | #define CA91CX42_OF_VRAI_CTL_SUPER 20 | |
503 | #define CA91CX42_BM_VRAI_CTL_VAS 0x00030000 | |
504 | #define CA91CX42_OF_VRAI_CTL_VAS 16 | |
505 | ||
506 | /* VCSR_CTL Register | |
507 | * offset F80 | |
508 | */ | |
509 | #define CA91CX42_VCSR_CTL_EN (1<<31) | |
510 | ||
511 | #define CA91CX42_VCSR_CTL_LAS_M (3<<0) | |
512 | #define CA91CX42_VCSR_CTL_LAS_PCI_MS 0 | |
513 | #define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0) | |
514 | #define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1) | |
515 | ||
516 | /* VCSR_BS Register | |
517 | * offset FFC | |
518 | */ | |
519 | #define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27) | |
520 | ||
521 | #endif /* _CA91CX42_H */ |