[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / tm6000 / tm6000-core.c

/*
   tm6000-core.c - driver for TM5600/TM6000 USB video capture devices

   Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>

   Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
       - DVB-T support

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation version 2

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/usb.h>
#include <linux/i2c.h>
#include "tm6000.h"
#include "tm6000-regs.h"
#include <media/v4l2-common.h>
#include <media/tuner.h>

#define USB_TIMEOUT	5*HZ /* ms */

int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
			   u16 value, u16 index, u8 *buf, u16 len)
{
	int          ret, i;
	unsigned int pipe;
	static int   ini=0, last=0, n=0;
	u8	     *data=NULL;

	if (len)
		data = kzalloc(len, GFP_KERNEL);


	if (req_type & USB_DIR_IN)
		pipe=usb_rcvctrlpipe(dev->udev, 0);
	else {
		pipe=usb_sndctrlpipe(dev->udev, 0);
		memcpy(data, buf, len);
	}

	if (tm6000_debug & V4L2_DEBUG_I2C) {
		if (!ini)
			last=ini=jiffies;

		printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);

		printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
			(req_type & USB_DIR_IN)?" IN":"OUT",
			jiffies_to_msecs(jiffies-last),
			jiffies_to_msecs(jiffies-ini),
			req_type, req,value&0xff,value>>8, index&0xff, index>>8,
			len&0xff, len>>8);
		last=jiffies;
		n++;

		if ( !(req_type & USB_DIR_IN) ) {
			printk(">>> ");
			for (i=0;i<len;i++) {
				printk(" %02x",buf[i]);
			}
		printk("\n");
		}
	}

	ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
			      len, USB_TIMEOUT);

	if (req_type &  USB_DIR_IN)
		memcpy(buf, data, len);

	if (tm6000_debug & V4L2_DEBUG_I2C) {
		if (ret<0) {
			if (req_type &  USB_DIR_IN)
				printk("<<< (len=%d)\n",len);

			printk("%s: Error #%d\n", __FUNCTION__, ret);
		} else if (req_type &  USB_DIR_IN) {
			printk("<<< ");
			for (i=0;i<len;i++) {
				printk(" %02x",buf[i]);
			}
			printk("\n");
		}
	}

	kfree(data);

	msleep(5);

	return ret;
}

int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	return
		tm6000_read_write_usb (dev, USB_DIR_OUT | USB_TYPE_VENDOR,
				       req, value, index, NULL, 0);
}

int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	int rc;
	u8 buf[1];

	rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
				       value, index, buf, 1);

	if (rc<0)
		return rc;

	return *buf;
}

int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	int rc;
	u8 buf[2];

	rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
				       value, index, buf, 2);

	if (rc<0)
		return rc;

	return buf[1]|buf[0]<<8;
}

void tm6000_set_fourcc_format(struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		if (dev->fourcc == V4L2_PIX_FMT_UYVY)
			tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfc);
		else
			tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfd);
	} else {
		if (dev->fourcc == V4L2_PIX_FMT_UYVY)
			tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0);
		else
			tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90);
	}
}

int tm6000_init_analog_mode (struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		int val;

		/* Enable video */
		val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
		val |= 0x60;
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf);

	} else {
		/* Enables soft reset */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);

		if (dev->scaler) {
			tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
		} else {
			/* Enable Hfilter and disable TS Drop err */
			tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
		}

		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);

		/* AP Software reset */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);

		tm6000_set_fourcc_format(dev);

		/* Disables soft reset */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);

		/* E3: Select input 0 - TV tuner */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);

		/* This controls input */
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
	}
	msleep(20);

	/* Tuner firmware can now be loaded */

	/*FIXME: Hack!!! */
	struct v4l2_frequency f;
	mutex_lock(&dev->lock);
	f.frequency=dev->freq;
	v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
	mutex_unlock(&dev->lock);

	msleep(100);
	tm6000_set_standard (dev, &dev->norm);
	tm6000_set_audio_bitrate (dev,48000);

	return 0;
}

int tm6000_init_digital_mode (struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		int val;
		u8 buf[2];

		/* digital init */
		val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
		val &= ~0x60;
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
		val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0);
		val |= 0x40;
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, val);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0x28);
		tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xfc);
		tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe6, 0xff);
		tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe);
		tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
		printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);


	} else  {
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60);

		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
		msleep(50);

		tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
		msleep(50);
		tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
		msleep(50);
		tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
		msleep(100);
	}
	return 0;
}

struct reg_init {
	u8 req;
	u8 reg;
	u8 val;
};

/* The meaning of those initializations are unknown */
struct reg_init tm6000_init_tab[] = {
	/* REG  VALUE */
	{ REQ_07_SET_GET_AVREG,  0xdf, 0x1f },
	{ REQ_07_SET_GET_AVREG,  0xff, 0x08 },
	{ REQ_07_SET_GET_AVREG,  0xff, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xd5, 0x4f },
	{ REQ_07_SET_GET_AVREG,  0xda, 0x23 },
	{ REQ_07_SET_GET_AVREG,  0xdb, 0x08 },
	{ REQ_07_SET_GET_AVREG,  0xe2, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xe3, 0x10 },
	{ REQ_07_SET_GET_AVREG,  0xe5, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xe8, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xeb, 0x64 },		/* 48000 bits/sample, external input */
	{ REQ_07_SET_GET_AVREG,  0xee, 0xc2 },
	{ REQ_07_SET_GET_AVREG,  0x3f, 0x01 },		/* Start of soft reset */
	{ REQ_07_SET_GET_AVREG,  0x00, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0x01, 0x07 },
	{ REQ_07_SET_GET_AVREG,  0x02, 0x5f },
	{ REQ_07_SET_GET_AVREG,  0x03, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0x05, 0x64 },
	{ REQ_07_SET_GET_AVREG,  0x07, 0x01 },
	{ REQ_07_SET_GET_AVREG,  0x08, 0x82 },
	{ REQ_07_SET_GET_AVREG,  0x09, 0x36 },
	{ REQ_07_SET_GET_AVREG,  0x0a, 0x50 },
	{ REQ_07_SET_GET_AVREG,  0x0c, 0x6a },
	{ REQ_07_SET_GET_AVREG,  0x11, 0xc9 },
	{ REQ_07_SET_GET_AVREG,  0x12, 0x07 },
	{ REQ_07_SET_GET_AVREG,  0x13, 0x3b },
	{ REQ_07_SET_GET_AVREG,  0x14, 0x47 },
	{ REQ_07_SET_GET_AVREG,  0x15, 0x6f },
	{ REQ_07_SET_GET_AVREG,  0x17, 0xcd },
	{ REQ_07_SET_GET_AVREG,  0x18, 0x1e },
	{ REQ_07_SET_GET_AVREG,  0x19, 0x8b },
	{ REQ_07_SET_GET_AVREG,  0x1a, 0xa2 },
	{ REQ_07_SET_GET_AVREG,  0x1b, 0xe9 },
	{ REQ_07_SET_GET_AVREG,  0x1c, 0x1c },
	{ REQ_07_SET_GET_AVREG,  0x1d, 0xcc },
	{ REQ_07_SET_GET_AVREG,  0x1e, 0xcc },
	{ REQ_07_SET_GET_AVREG,  0x1f, 0xcd },
	{ REQ_07_SET_GET_AVREG,  0x20, 0x3c },
	{ REQ_07_SET_GET_AVREG,  0x21, 0x3c },
	{ REQ_07_SET_GET_AVREG,  0x2d, 0x48 },
	{ REQ_07_SET_GET_AVREG,  0x2e, 0x88 },
	{ REQ_07_SET_GET_AVREG,  0x30, 0x22 },
	{ REQ_07_SET_GET_AVREG,  0x31, 0x61 },
	{ REQ_07_SET_GET_AVREG,  0x32, 0x74 },
	{ REQ_07_SET_GET_AVREG,  0x33, 0x1c },
	{ REQ_07_SET_GET_AVREG,  0x34, 0x74 },
	{ REQ_07_SET_GET_AVREG,  0x35, 0x1c },
	{ REQ_07_SET_GET_AVREG,  0x36, 0x7a },
	{ REQ_07_SET_GET_AVREG,  0x37, 0x26 },
	{ REQ_07_SET_GET_AVREG,  0x38, 0x40 },
	{ REQ_07_SET_GET_AVREG,  0x39, 0x0a },
	{ REQ_07_SET_GET_AVREG,  0x42, 0x55 },
	{ REQ_07_SET_GET_AVREG,  0x51, 0x11 },
	{ REQ_07_SET_GET_AVREG,  0x55, 0x01 },
	{ REQ_07_SET_GET_AVREG,  0x57, 0x02 },
	{ REQ_07_SET_GET_AVREG,  0x58, 0x35 },
	{ REQ_07_SET_GET_AVREG,  0x59, 0xa0 },
	{ REQ_07_SET_GET_AVREG,  0x80, 0x15 },
	{ REQ_07_SET_GET_AVREG,  0x82, 0x42 },
	{ REQ_07_SET_GET_AVREG,  0xc1, 0xd0 },
	{ REQ_07_SET_GET_AVREG,  0xc3, 0x88 },
	{ REQ_07_SET_GET_AVREG,  0x3f, 0x00 },		/* End of the soft reset */
	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
};

struct reg_init tm6010_init_tab[] = {
	{ REQ_07_SET_GET_AVREG, 0xc0, 0x00 },
	{ REQ_07_SET_GET_AVREG, 0xc4, 0xa0 },
	{ REQ_07_SET_GET_AVREG, 0xc6, 0x40 },
	{ REQ_07_SET_GET_AVREG, 0xca, 0x31 },
	{ REQ_07_SET_GET_AVREG, 0xcc, 0xe1 },
	{ REQ_07_SET_GET_AVREG, 0xe0, 0x03 },
	{ REQ_07_SET_GET_AVREG, 0xfe, 0x7f },

	{ REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc },

	{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 },
	{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
	{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
	{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
	{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
	{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
	{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
	{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
	{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
	{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
	{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
	{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
	{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
	{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
	{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
	{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
	{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
	{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
	{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
	{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
	{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
	{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
	{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
	{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
	{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
	{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
	{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
	{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
	{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
	{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
	{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
	{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
	{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
	{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
	{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
	{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
	{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
	{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
	{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
	{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
	{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
	{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
	{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
	{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
	{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
	{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
	{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
	{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
	{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
	{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 },

	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },

	/* set remote wakeup key:any key wakeup */
	{ REQ_07_SET_GET_AVREG,  0xe5,  0xfe },
	{ REQ_07_SET_GET_AVREG,  0xda,  0xff },
};

int tm6000_init (struct tm6000_core *dev)
{
	int board, rc=0, i, size;
	struct reg_init *tab;

	if (dev->dev_type == TM6010) {
		tab = tm6010_init_tab;
		size = ARRAY_SIZE(tm6010_init_tab);
	} else {
		tab = tm6000_init_tab;
		size = ARRAY_SIZE(tm6000_init_tab);
	}

	/* Load board's initialization table */
	for (i=0; i< size; i++) {
		rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
		if (rc<0) {
			printk (KERN_ERR "Error %i while setting req %d, "
					 "reg %d to value %d\n", rc,
					 tab[i].req,tab[i].reg, tab[i].val);
			return rc;
		}
	}

	msleep(5); /* Just to be conservative */

	/* Check board version - maybe 10Moons specific */
	board=tm6000_get_reg16 (dev, 0x40, 0, 0);
	if (board >=0) {
		printk (KERN_INFO "Board version = 0x%04x\n",board);
	} else {
		printk (KERN_ERR "Error %i while retrieving board version\n",board);
	}

	if (dev->dev_type == TM6010) {
		/* Turn xceive 3028 on */
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6010_GPIO_3, 0x01);
		msleep(11);
	}

	/* Reset GPIO1 and GPIO4. */
	for (i=0; i< 2; i++) {
		rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
					dev->tuner_reset_gpio, 0x00);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
			return rc;
		}

		msleep(10); /* Just to be conservative */
		rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
					dev->tuner_reset_gpio, 0x01);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
			return rc;
		}

		msleep(10);
		rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 0);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
			return rc;
		}

		msleep(10);
		rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 1);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
			return rc;
		}

		if (!i) {
			rc=tm6000_get_reg16(dev, 0x40,0,0);
			if (rc>=0) {
				printk ("board=%d\n", rc);
			}
		}
	}

	msleep(50);

	return 0;
}

int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
{
	int val;

	val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
printk("Original value=%d\n",val);
	if (val<0)
		return val;

	val &= 0x0f;		/* Preserve the audio input control bits */
	switch (bitrate) {
	case 44100:
		val|=0xd0;
		dev->audio_bitrate=bitrate;
		break;
	case 48000:
		val|=0x60;
		dev->audio_bitrate=bitrate;
		break;
	}
	val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);

	return val;
}
EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
Commit	Line	Data
9701dc94 MCC	1	/*
	2	tm6000-core.c - driver for TM5600/TM6000 USB video capture devices
	3
	4	Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
	5
3169c9b2 ML	6	Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
	7	- DVB-T support
	8
9701dc94 MCC	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation version 2
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/kernel.h>
	25	#include <linux/usb.h>
	26	#include <linux/i2c.h>
9701dc94 MCC	27	#include "tm6000.h"
	28	#include "tm6000-regs.h"
	29	#include <media/v4l2-common.h>
	30	#include <media/tuner.h>
	31
9701dc94 MCC	32	#define USB_TIMEOUT 5HZ / ms */
	33
	34	int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
	35	u16 value, u16 index, u8 *buf, u16 len)
	36	{
	37	int ret, i;
	38	unsigned int pipe;
	39	static int ini=0, last=0, n=0;
	40	u8 *data=NULL;
	41
	42	if (len)
	43	data = kzalloc(len, GFP_KERNEL);
	44
	45
	46	if (req_type & USB_DIR_IN)
	47	pipe=usb_rcvctrlpipe(dev->udev, 0);
	48	else {
	49	pipe=usb_sndctrlpipe(dev->udev, 0);
	50	memcpy(data, buf, len);
	51	}
	52
edecce0a	53	if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94 MCC	54	if (!ini)
	55	last=ini=jiffies;
	56
	57	printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
	58
	59	printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
	60	(req_type & USB_DIR_IN)?" IN":"OUT",
	61	jiffies_to_msecs(jiffies-last),
	62	jiffies_to_msecs(jiffies-ini),
	63	req_type, req,value&0xff,value>>8, index&0xff, index>>8,
	64	len&0xff, len>>8);
	65	last=jiffies;
	66	n++;
	67
	68	if ( !(req_type & USB_DIR_IN) ) {
	69	printk(">>> ");
	70	for (i=0;i<len;i++) {
	71	printk(" %02x",buf[i]);
	72	}
8ae1fc6e	73	printk("\n");
9701dc94 MCC	74	}
	75	}
	76
	77	ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
	78	len, USB_TIMEOUT);
	79
	80	if (req_type & USB_DIR_IN)
	81	memcpy(buf, data, len);
	82
edecce0a	83	if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94 MCC	84	if (ret<0) {
	85	if (req_type & USB_DIR_IN)
	86	printk("<<< (len=%d)\n",len);
	87
	88	printk("%s: Error #%d\n", __FUNCTION__, ret);
	89	} else if (req_type & USB_DIR_IN) {
	90	printk("<<< ");
	91	for (i=0;i<len;i++) {
	92	printk(" %02x",buf[i]);
	93	}
	94	printk("\n");
	95	}
	96	}
	97
	98	kfree(data);
	99
a5adfbed ML	100	msleep(5);
a5adfbed ML	101
9701dc94 MCC	102	return ret;
	103	}
	104
	105	int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	106	{
	107	return
	108	tm6000_read_write_usb (dev, USB_DIR_OUT \| USB_TYPE_VENDOR,
	109	req, value, index, NULL, 0);
	110	}
	111
	112	int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	113	{
	114	int rc;
	115	u8 buf[1];
	116
	117	rc=tm6000_read_write_usb (dev, USB_DIR_IN \| USB_TYPE_VENDOR, req,
	118	value, index, buf, 1);
	119
	120	if (rc<0)
	121	return rc;
	122
	123	return *buf;
	124	}
	125
	126	int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	127	{
	128	int rc;
	129	u8 buf[2];
	130
	131	rc=tm6000_read_write_usb (dev, USB_DIR_IN \| USB_TYPE_VENDOR, req,
	132	value, index, buf, 2);
	133
	134	if (rc<0)
	135	return rc;
	136
	137	return buf[1]\|buf[0]<<8;
	138	}
	139
	140	void tm6000_set_fourcc_format(struct tm6000_core *dev)
	141	{
717ecd2b MCC	142	if (dev->dev_type == TM6010) {
	143	if (dev->fourcc == V4L2_PIX_FMT_UYVY)
	144	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfc);
	145	else
	146	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfd);
9701dc94	147	} else {
717ecd2b MCC	148	if (dev->fourcc == V4L2_PIX_FMT_UYVY)
	149	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0);
	150	else
	151	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90);
9701dc94 MCC	152	}
	153	}
	154
	155	int tm6000_init_analog_mode (struct tm6000_core *dev)
	156	{
29c389be MCC	157	if (dev->dev_type == TM6010) {
29c389be MCC	158	int val;
9701dc94	159
29c389be MCC	160	/* Enable video */
	161	val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
	162	val \|= 0x60;
	163	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
	164	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf);
9701dc94	165
9701dc94	166	} else {
29c389be MCC	167	/* Enables soft reset */
	168	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
	169
	170	if (dev->scaler) {
	171	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
	172	} else {
	173	/* Enable Hfilter and disable TS Drop err */
	174	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
	175	}
9701dc94	176
29c389be MCC	177	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
	178	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
	179	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
	180	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
	181	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
	182	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
9701dc94	183
29c389be MCC	184	/* AP Software reset */
	185	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
	186	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);
9701dc94	187
29c389be	188	tm6000_set_fourcc_format(dev);
9701dc94	189
29c389be MCC	190	/* Disables soft reset */
29c389be MCC	191	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
9701dc94	192
29c389be MCC	193	/* E3: Select input 0 - TV tuner */
	194	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
	195	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94	196
29c389be MCC	197	/* This controls input */
	198	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
	199	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
	200	}
9701dc94 MCC	201	msleep(20);
9701dc94 MCC	202
29c389be MCC	203	/* Tuner firmware can now be loaded */
29c389be MCC	204
9701dc94 MCC	205	/FIXME: Hack!!! /
	206	struct v4l2_frequency f;
	207	mutex_lock(&dev->lock);
	208	f.frequency=dev->freq;
427f7fac	209	v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94 MCC	210	mutex_unlock(&dev->lock);
	211
	212	msleep(100);
	213	tm6000_set_standard (dev, &dev->norm);
	214	tm6000_set_audio_bitrate (dev,48000);
	215
9701dc94 MCC	216	return 0;
	217	}
	218
3169c9b2 ML	219	int tm6000_init_digital_mode (struct tm6000_core *dev)
3169c9b2 ML	220	{
c733a4d5 SR	221	if (dev->dev_type == TM6010) {
	222	int val;
	223	u8 buf[2];
3169c9b2	224
c733a4d5 SR	225	/* digital init */
	226	val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
	227	val &= ~0x60;
	228	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
	229	val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0);
	230	val \|= 0x40;
	231	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, val);
	232	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0x28);
	233	tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xfc);
	234	tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe6, 0xff);
	235	tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe);
	236	tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
	237	printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
	238
	239
	240	} else {
	241	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08);
	242	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00);
	243	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01);
	244	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08);
	245	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
	246	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
	247	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
	248	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40);
	249	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0);
	250	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09);
	251	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37);
	252	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8);
	253	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0);
	254	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60);
	255
	256	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
	257	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
	258	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
	259	msleep(50);
	260
	261	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
	262	msleep(50);
	263	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
	264	msleep(50);
	265	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
	266	msleep(100);
	267	}
3169c9b2 ML	268	return 0;
3169c9b2 ML	269	}
9701dc94	270
29c389be MCC	271	struct reg_init {
	272	u8 req;
	273	u8 reg;
	274	u8 val;
	275	};
	276
9701dc94	277	/* The meaning of those initializations are unknown */
29c389be	278	struct reg_init tm6000_init_tab[] = {
9701dc94	279	/* REG VALUE */
29c389be MCC	280	{ REQ_07_SET_GET_AVREG, 0xdf, 0x1f },
	281	{ REQ_07_SET_GET_AVREG, 0xff, 0x08 },
	282	{ REQ_07_SET_GET_AVREG, 0xff, 0x00 },
	283	{ REQ_07_SET_GET_AVREG, 0xd5, 0x4f },
	284	{ REQ_07_SET_GET_AVREG, 0xda, 0x23 },
	285	{ REQ_07_SET_GET_AVREG, 0xdb, 0x08 },
	286	{ REQ_07_SET_GET_AVREG, 0xe2, 0x00 },
	287	{ REQ_07_SET_GET_AVREG, 0xe3, 0x10 },
	288	{ REQ_07_SET_GET_AVREG, 0xe5, 0x00 },
	289	{ REQ_07_SET_GET_AVREG, 0xe8, 0x00 },
	290	{ REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
	291	{ REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
	292	{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, /* Start of soft reset */
	293	{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
	294	{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
	295	{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
	296	{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
	297	{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
	298	{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
	299	{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
	300	{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
	301	{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
	302	{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
	303	{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
	304	{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
	305	{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
	306	{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
	307	{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
	308	{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
	309	{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
	310	{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
	311	{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
	312	{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
	313	{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
	314	{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
	315	{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
	316	{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
	317	{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
	318	{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
	319	{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
	320	{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
	321	{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
	322	{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
	323	{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
	324	{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
	325	{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
	326	{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
	327	{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
	328	{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
	329	{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
	330	{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
	331	{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
	332	{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
	333	{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
	334	{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
	335	{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
	336	{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
	337	{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
	338	{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
	339	{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
	340	{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
	341	{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, /* End of the soft reset */
	342	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
	343	};
344
345	struct reg_init tm6010_init_tab[] = {
346	{ REQ_07_SET_GET_AVREG, 0xc0, 0x00 },
347	{ REQ_07_SET_GET_AVREG, 0xc4, 0xa0 },
348	{ REQ_07_SET_GET_AVREG, 0xc6, 0x40 },
349	{ REQ_07_SET_GET_AVREG, 0xca, 0x31 },
350	{ REQ_07_SET_GET_AVREG, 0xcc, 0xe1 },
351	{ REQ_07_SET_GET_AVREG, 0xe0, 0x03 },
352	{ REQ_07_SET_GET_AVREG, 0xfe, 0x7f },
353
354	{ REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 },
355	{ REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 },
356	{ REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 },
357	{ REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 },
358	{ REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 },
359	{ REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 },
360	{ REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 },
361	{ REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 },
362	{ REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc },
363
364	{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 },
365	{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
366	{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
367	{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
368	{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
369	{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
370	{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
371	{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
372	{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
373	{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
374	{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
375	{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
376	{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
377	{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
378	{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
379	{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
380	{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
381	{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
382	{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
383	{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
384	{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
385	{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
386	{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
387	{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
388	{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
389	{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
390	{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
391	{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
392	{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
393	{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
394	{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
395	{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
396	{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
397	{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
398	{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
399	{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
400	{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
401	{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
402	{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
403	{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
404	{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
405	{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
406	{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
407	{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
408	{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
409	{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
410	{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
411	{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
412	{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
413	{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 },
414
415	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
416
417	/* set remote wakeup key:any key wakeup */
418	{ REQ_07_SET_GET_AVREG, 0xe5, 0xfe },
419	{ REQ_07_SET_GET_AVREG, 0xda, 0xff },
9701dc94 MCC	420	};
	421
	422	int tm6000_init (struct tm6000_core *dev)
	423	{
29c389be MCC	424	int board, rc=0, i, size;
	425	struct reg_init *tab;
	426
	427	if (dev->dev_type == TM6010) {
	428	tab = tm6010_init_tab;
	429	size = ARRAY_SIZE(tm6010_init_tab);
	430	} else {
	431	tab = tm6000_init_tab;
	432	size = ARRAY_SIZE(tm6000_init_tab);
	433	}
9701dc94	434
9701dc94	435	/* Load board's initialization table */
29c389be MCC	436	for (i=0; i< size; i++) {
29c389be MCC	437	rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
9701dc94	438	if (rc<0) {
29c389be MCC	439	printk (KERN_ERR "Error %i while setting req %d, "
	440	"reg %d to value %d\n", rc,
	441	tab[i].req,tab[i].reg, tab[i].val);
9701dc94 MCC	442	return rc;
	443	}
	444	}
	445
29c389be MCC	446	msleep(5); /* Just to be conservative */
29c389be MCC	447
9701dc94 MCC	448	/* Check board version - maybe 10Moons specific */
	449	board=tm6000_get_reg16 (dev, 0x40, 0, 0);
	450	if (board >=0) {
	451	printk (KERN_INFO "Board version = 0x%04x\n",board);
	452	} else {
	453	printk (KERN_ERR "Error %i while retrieving board version\n",board);
	454	}
	455
29c389be MCC	456	if (dev->dev_type == TM6010) {
	457	/* Turn xceive 3028 on */
	458	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6010_GPIO_3, 0x01);
	459	msleep(11);
	460	}
9701dc94	461
a5adfbed ML	462	/* Reset GPIO1 and GPIO4. */
a5adfbed ML	463	for (i=0; i< 2; i++) {
29c389be MCC	464	rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
29c389be MCC	465	dev->tuner_reset_gpio, 0x00);
9701dc94 MCC	466	if (rc<0) {
	467	printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
	468	return rc;
	469	}
	470
	471	msleep(10); /* Just to be conservative */
29c389be MCC	472	rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
29c389be MCC	473	dev->tuner_reset_gpio, 0x01);
9701dc94 MCC	474	if (rc<0) {
	475	printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
	476	return rc;
	477	}
	478
a5adfbed ML	479	msleep(10);
	480	rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 0);
	481	if (rc<0) {
	482	printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
	483	return rc;
	484	}
	485
	486	msleep(10);
	487	rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 1);
	488	if (rc<0) {
	489	printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
	490	return rc;
	491	}
	492
29c389be	493	if (!i) {
9701dc94	494	rc=tm6000_get_reg16(dev, 0x40,0,0);
29c389be MCC	495	if (rc>=0) {
	496	printk ("board=%d\n", rc);
	497	}
	498	}
9701dc94	499	}
a5adfbed ML	500
	501	msleep(50);
	502
d544f2c3	503	return 0;
9701dc94 MCC	504	}
9701dc94 MCC	505
44351aa0	506	int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94 MCC	507	{
	508	int val;
	509
	510	val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
	511	printk("Original value=%d\n",val);
	512	if (val<0)
	513	return val;
	514
	515	val &= 0x0f; /* Preserve the audio input control bits */
	516	switch (bitrate) {
	517	case 44100:
	518	val\|=0xd0;
c13dd704	519	dev->audio_bitrate=bitrate;
9701dc94 MCC	520	break;
	521	case 48000:
	522	val\|=0x60;
c13dd704	523	dev->audio_bitrate=bitrate;
9701dc94 MCC	524	break;
	525	}
	526	val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);
	527
	528	return val;
	529	}
44351aa0	530	EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);