[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / tm6000 / tm6000-core.c

/*
   tm6000-core.c - driver for TM5600/TM6000 USB video capture devices

   Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>

   Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
       - DVB-T support

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation version 2

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/usb.h>
#include <linux/i2c.h>
#include <linux/video_decoder.h>
#include "tm6000.h"
#include "tm6000-regs.h"
#include <media/v4l2-common.h>
#include <media/tuner.h>

#define USB_TIMEOUT	5*HZ /* ms */

int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
			   u16 value, u16 index, u8 *buf, u16 len)
{
	int          ret, i;
	unsigned int pipe;
	static int   ini=0, last=0, n=0;
	u8	     *data=NULL;

	if (len)
		data = kzalloc(len, GFP_KERNEL);


	if (req_type & USB_DIR_IN)
		pipe=usb_rcvctrlpipe(dev->udev, 0);
	else {
		pipe=usb_sndctrlpipe(dev->udev, 0);
		memcpy(data, buf, len);
	}

	if (tm6000_debug & V4L2_DEBUG_I2C) {
		if (!ini)
			last=ini=jiffies;

		printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);

		printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
			(req_type & USB_DIR_IN)?" IN":"OUT",
			jiffies_to_msecs(jiffies-last),
			jiffies_to_msecs(jiffies-ini),
			req_type, req,value&0xff,value>>8, index&0xff, index>>8,
			len&0xff, len>>8);
		last=jiffies;
		n++;

		if ( !(req_type & USB_DIR_IN) ) {
			printk(">>> ");
			for (i=0;i<len;i++) {
				printk(" %02x",buf[i]);
			}
			printk("\n");
		}
	}

	ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
			      len, USB_TIMEOUT);

	if (req_type &  USB_DIR_IN)
		memcpy(buf, data, len);

	if (tm6000_debug & V4L2_DEBUG_I2C) {
		if (ret<0) {
			if (req_type &  USB_DIR_IN)
				printk("<<< (len=%d)\n",len);

			printk("%s: Error #%d\n", __FUNCTION__, ret);
		} else if (req_type &  USB_DIR_IN) {
			printk("<<< ");
			for (i=0;i<len;i++) {
				printk(" %02x",buf[i]);
			}
			printk("\n");
		}
	}

	kfree(data);

	msleep(5);

	return ret;
}

int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	return
		tm6000_read_write_usb (dev, USB_DIR_OUT | USB_TYPE_VENDOR,
				       req, value, index, NULL, 0);
}

int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	int rc;
	u8 buf[1];

	rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
				       value, index, buf, 1);

	if (rc<0)
		return rc;

	return *buf;
}

int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	int rc;
	u8 buf[2];

	rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
				       value, index, buf, 2);

	if (rc<0)
		return rc;

	return buf[1]|buf[0]<<8;
}

void tm6000_set_fourcc_format(struct tm6000_core *dev)
{
	if (dev->fourcc==V4L2_PIX_FMT_UYVY) {
		/* Sets driver to UYUV */
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0);
	} else {
		/* Sets driver to YUV2 */
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90);
	}
}

int tm6000_init_analog_mode (struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		int val;

		/* Enable video */
		val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
		val |= 0x60;
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf);

	} else {
		/* Enables soft reset */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);

		if (dev->scaler) {
			tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
		} else {
			/* Enable Hfilter and disable TS Drop err */
			tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
		}

		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);

		/* AP Software reset */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);

		tm6000_set_fourcc_format(dev);

		/* Disables soft reset */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);

		/* E3: Select input 0 - TV tuner */
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);

		/* This controls input */
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
	}
	msleep(20);

	/* Tuner firmware can now be loaded */

	/*FIXME: Hack!!! */
	struct v4l2_frequency f;
	mutex_lock(&dev->lock);
	f.frequency=dev->freq;
	tm6000_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
	mutex_unlock(&dev->lock);

	msleep(100);
	tm6000_set_standard (dev, &dev->norm);
	tm6000_set_audio_bitrate (dev,48000);

	return 0;
}

int tm6000_init_digital_mode (struct tm6000_core *dev)
{
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60);

	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
	msleep(50);

	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
	msleep(50);
	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
	msleep(50);
	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
	msleep(100);

	return 0;
}

struct reg_init {
	u8 req;
	u8 reg;
	u8 val;
};

/* The meaning of those initializations are unknown */
struct reg_init tm6000_init_tab[] = {
	/* REG  VALUE */
	{ REQ_07_SET_GET_AVREG,  0xdf, 0x1f },
	{ REQ_07_SET_GET_AVREG,  0xff, 0x08 },
	{ REQ_07_SET_GET_AVREG,  0xff, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xd5, 0x4f },
	{ REQ_07_SET_GET_AVREG,  0xda, 0x23 },
	{ REQ_07_SET_GET_AVREG,  0xdb, 0x08 },
	{ REQ_07_SET_GET_AVREG,  0xe2, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xe3, 0x10 },
	{ REQ_07_SET_GET_AVREG,  0xe5, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xe8, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xeb, 0x64 },		/* 48000 bits/sample, external input */
	{ REQ_07_SET_GET_AVREG,  0xee, 0xc2 },
	{ REQ_07_SET_GET_AVREG,  0x3f, 0x01 },		/* Start of soft reset */
	{ REQ_07_SET_GET_AVREG,  0x00, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0x01, 0x07 },
	{ REQ_07_SET_GET_AVREG,  0x02, 0x5f },
	{ REQ_07_SET_GET_AVREG,  0x03, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0x05, 0x64 },
	{ REQ_07_SET_GET_AVREG,  0x07, 0x01 },
	{ REQ_07_SET_GET_AVREG,  0x08, 0x82 },
	{ REQ_07_SET_GET_AVREG,  0x09, 0x36 },
	{ REQ_07_SET_GET_AVREG,  0x0a, 0x50 },
	{ REQ_07_SET_GET_AVREG,  0x0c, 0x6a },
	{ REQ_07_SET_GET_AVREG,  0x11, 0xc9 },
	{ REQ_07_SET_GET_AVREG,  0x12, 0x07 },
	{ REQ_07_SET_GET_AVREG,  0x13, 0x3b },
	{ REQ_07_SET_GET_AVREG,  0x14, 0x47 },
	{ REQ_07_SET_GET_AVREG,  0x15, 0x6f },
	{ REQ_07_SET_GET_AVREG,  0x17, 0xcd },
	{ REQ_07_SET_GET_AVREG,  0x18, 0x1e },
	{ REQ_07_SET_GET_AVREG,  0x19, 0x8b },
	{ REQ_07_SET_GET_AVREG,  0x1a, 0xa2 },
	{ REQ_07_SET_GET_AVREG,  0x1b, 0xe9 },
	{ REQ_07_SET_GET_AVREG,  0x1c, 0x1c },
	{ REQ_07_SET_GET_AVREG,  0x1d, 0xcc },
	{ REQ_07_SET_GET_AVREG,  0x1e, 0xcc },
	{ REQ_07_SET_GET_AVREG,  0x1f, 0xcd },
	{ REQ_07_SET_GET_AVREG,  0x20, 0x3c },
	{ REQ_07_SET_GET_AVREG,  0x21, 0x3c },
	{ REQ_07_SET_GET_AVREG,  0x2d, 0x48 },
	{ REQ_07_SET_GET_AVREG,  0x2e, 0x88 },
	{ REQ_07_SET_GET_AVREG,  0x30, 0x22 },
	{ REQ_07_SET_GET_AVREG,  0x31, 0x61 },
	{ REQ_07_SET_GET_AVREG,  0x32, 0x74 },
	{ REQ_07_SET_GET_AVREG,  0x33, 0x1c },
	{ REQ_07_SET_GET_AVREG,  0x34, 0x74 },
	{ REQ_07_SET_GET_AVREG,  0x35, 0x1c },
	{ REQ_07_SET_GET_AVREG,  0x36, 0x7a },
	{ REQ_07_SET_GET_AVREG,  0x37, 0x26 },
	{ REQ_07_SET_GET_AVREG,  0x38, 0x40 },
	{ REQ_07_SET_GET_AVREG,  0x39, 0x0a },
	{ REQ_07_SET_GET_AVREG,  0x42, 0x55 },
	{ REQ_07_SET_GET_AVREG,  0x51, 0x11 },
	{ REQ_07_SET_GET_AVREG,  0x55, 0x01 },
	{ REQ_07_SET_GET_AVREG,  0x57, 0x02 },
	{ REQ_07_SET_GET_AVREG,  0x58, 0x35 },
	{ REQ_07_SET_GET_AVREG,  0x59, 0xa0 },
	{ REQ_07_SET_GET_AVREG,  0x80, 0x15 },
	{ REQ_07_SET_GET_AVREG,  0x82, 0x42 },
	{ REQ_07_SET_GET_AVREG,  0xc1, 0xd0 },
	{ REQ_07_SET_GET_AVREG,  0xc3, 0x88 },
	{ REQ_07_SET_GET_AVREG,  0x3f, 0x00 },		/* End of the soft reset */
	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
};

struct reg_init tm6010_init_tab[] = {
	{ REQ_07_SET_GET_AVREG, 0xc0, 0x00 },
	{ REQ_07_SET_GET_AVREG, 0xc4, 0xa0 },
	{ REQ_07_SET_GET_AVREG, 0xc6, 0x40 },
	{ REQ_07_SET_GET_AVREG, 0xca, 0x31 },
	{ REQ_07_SET_GET_AVREG, 0xcc, 0xe1 },
	{ REQ_07_SET_GET_AVREG, 0xe0, 0x03 },
	{ REQ_07_SET_GET_AVREG, 0xfe, 0x7f },

	{ REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 },
	{ REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc },

	{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 },
	{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
	{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
	{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
	{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
	{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
	{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
	{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
	{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
	{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
	{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
	{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
	{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
	{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
	{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
	{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
	{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
	{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
	{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
	{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
	{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
	{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
	{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
	{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
	{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
	{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
	{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
	{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
	{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
	{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
	{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
	{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
	{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
	{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
	{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
	{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
	{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
	{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
	{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
	{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
	{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
	{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
	{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
	{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
	{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
	{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
	{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
	{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
	{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
	{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 },

	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },

	/* set remote wakeup key:any key wakeup */
	{ REQ_07_SET_GET_AVREG,  0xe5,  0xfe },
	{ REQ_07_SET_GET_AVREG,  0xda,  0xff },
};

int tm6000_init (struct tm6000_core *dev)
{
	int board, rc=0, i, size;
	struct reg_init *tab;

	if (dev->dev_type == TM6010) {
		tab = tm6010_init_tab;
		size = ARRAY_SIZE(tm6010_init_tab);
	} else {
		tab = tm6000_init_tab;
		size = ARRAY_SIZE(tm6000_init_tab);
	}

	/* Load board's initialization table */
	for (i=0; i< size; i++) {
		rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
		if (rc<0) {
			printk (KERN_ERR "Error %i while setting req %d, "
					 "reg %d to value %d\n", rc,
					 tab[i].req,tab[i].reg, tab[i].val);
			return rc;
		}
	}

	msleep(5); /* Just to be conservative */

	/* Check board version - maybe 10Moons specific */
	board=tm6000_get_reg16 (dev, 0x40, 0, 0);
	if (board >=0) {
		printk (KERN_INFO "Board version = 0x%04x\n",board);
	} else {
		printk (KERN_ERR "Error %i while retrieving board version\n",board);
	}

	if (dev->dev_type == TM6010) {
		/* Turn xceive 3028 on */
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6010_GPIO_3, 0x01);
		msleep(11);
	}

	/* Reset GPIO1 and GPIO4. */
	for (i=0; i< 2; i++) {
		rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
					dev->tuner_reset_gpio, 0x00);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
			return rc;
		}

		msleep(10); /* Just to be conservative */
		rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
					dev->tuner_reset_gpio, 0x01);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
			return rc;
		}

		msleep(10);
		rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 0);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
			return rc;
		}

		msleep(10);
		rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 1);
		if (rc<0) {
			printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
			return rc;
		}

		if (!i) {
			rc=tm6000_get_reg16(dev, 0x40,0,0);
			if (rc>=0) {
				printk ("board=%d\n", rc);
			}
		}
	}

	msleep(50);

	return 0;
}

int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
{
	int val;

	val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
printk("Original value=%d\n",val);
	if (val<0)
		return val;

	val &= 0x0f;		/* Preserve the audio input control bits */
	switch (bitrate) {
	case 44100:
		val|=0xd0;
		dev->audio_bitrate=bitrate;
		break;
	case 48000:
		val|=0x60;
		dev->audio_bitrate=bitrate;
		break;
	}
	val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);

	return val;
}
EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
Commit	Line	Data
9701dc94 MCC	1	/*
	2	tm6000-core.c - driver for TM5600/TM6000 USB video capture devices
	3
	4	Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
	5
3169c9b2 ML	6	Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
	7	- DVB-T support
	8
9701dc94 MCC	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation version 2
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/kernel.h>
	25	#include <linux/usb.h>
	26	#include <linux/i2c.h>
	27	#include <linux/video_decoder.h>
	28	#include "tm6000.h"
	29	#include "tm6000-regs.h"
	30	#include <media/v4l2-common.h>
	31	#include <media/tuner.h>
	32
9701dc94 MCC	33	#define USB_TIMEOUT 5HZ / ms */
	34
	35	int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
	36	u16 value, u16 index, u8 *buf, u16 len)
	37	{
	38	int ret, i;
	39	unsigned int pipe;
	40	static int ini=0, last=0, n=0;
	41	u8 *data=NULL;
	42
	43	if (len)
	44	data = kzalloc(len, GFP_KERNEL);
	45
	46
	47	if (req_type & USB_DIR_IN)
	48	pipe=usb_rcvctrlpipe(dev->udev, 0);
	49	else {
	50	pipe=usb_sndctrlpipe(dev->udev, 0);
	51	memcpy(data, buf, len);
	52	}
	53
	54	if (tm6000_debug & V4L2_DEBUG_I2C) {
	55	if (!ini)
	56	last=ini=jiffies;
	57
	58	printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
	59
	60	printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
	61	(req_type & USB_DIR_IN)?" IN":"OUT",
	62	jiffies_to_msecs(jiffies-last),
	63	jiffies_to_msecs(jiffies-ini),
	64	req_type, req,value&0xff,value>>8, index&0xff, index>>8,
	65	len&0xff, len>>8);
	66	last=jiffies;
	67	n++;
	68
	69	if ( !(req_type & USB_DIR_IN) ) {
	70	printk(">>> ");
	71	for (i=0;i<len;i++) {
	72	printk(" %02x",buf[i]);
	73	}
	74	printk("\n");
	75	}
	76	}
	77
	78	ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
	79	len, USB_TIMEOUT);
	80
	81	if (req_type & USB_DIR_IN)
	82	memcpy(buf, data, len);
	83
	84	if (tm6000_debug & V4L2_DEBUG_I2C) {
	85	if (ret<0) {
	86	if (req_type & USB_DIR_IN)
	87	printk("<<< (len=%d)\n",len);
	88
	89	printk("%s: Error #%d\n", __FUNCTION__, ret);
	90	} else if (req_type & USB_DIR_IN) {
	91	printk("<<< ");
	92	for (i=0;i<len;i++) {
	93	printk(" %02x",buf[i]);
	94	}
	95	printk("\n");
	96	}
97	}
98
99	kfree(data);
100
a5adfbed ML	101	msleep(5);
a5adfbed ML	102
9701dc94 MCC	103	return ret;
	104	}
	105
	106	int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	107	{
	108	return
	109	tm6000_read_write_usb (dev, USB_DIR_OUT \| USB_TYPE_VENDOR,
	110	req, value, index, NULL, 0);
	111	}
	112
	113	int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	114	{
	115	int rc;
	116	u8 buf[1];
	117
	118	rc=tm6000_read_write_usb (dev, USB_DIR_IN \| USB_TYPE_VENDOR, req,
	119	value, index, buf, 1);
	120
	121	if (rc<0)
	122	return rc;
	123
	124	return *buf;
	125	}
	126
	127	int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	128	{
	129	int rc;
	130	u8 buf[2];
	131
	132	rc=tm6000_read_write_usb (dev, USB_DIR_IN \| USB_TYPE_VENDOR, req,
	133	value, index, buf, 2);
	134
	135	if (rc<0)
	136	return rc;
	137
	138	return buf[1]\|buf[0]<<8;
	139	}
	140
	141	void tm6000_set_fourcc_format(struct tm6000_core *dev)
	142	{
	143	if (dev->fourcc==V4L2_PIX_FMT_UYVY) {
	144	/* Sets driver to UYUV */
	145	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0);
	146	} else {
	147	/* Sets driver to YUV2 */
	148	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90);
	149	}
	150	}
	151
	152	int tm6000_init_analog_mode (struct tm6000_core *dev)
	153	{
29c389be MCC	154	if (dev->dev_type == TM6010) {
29c389be MCC	155	int val;
9701dc94	156
29c389be MCC	157	/* Enable video */
	158	val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
	159	val \|= 0x60;
	160	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
	161	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf);
9701dc94	162
9701dc94	163	} else {
29c389be MCC	164	/* Enables soft reset */
	165	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
	166
	167	if (dev->scaler) {
	168	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
	169	} else {
	170	/* Enable Hfilter and disable TS Drop err */
	171	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
	172	}
9701dc94	173
29c389be MCC	174	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
	175	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
	176	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
	177	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
	178	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
	179	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
9701dc94	180
29c389be MCC	181	/* AP Software reset */
	182	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
	183	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);
9701dc94	184
29c389be	185	tm6000_set_fourcc_format(dev);
9701dc94	186
29c389be MCC	187	/* Disables soft reset */
29c389be MCC	188	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
9701dc94	189
29c389be MCC	190	/* E3: Select input 0 - TV tuner */
	191	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
	192	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94	193
29c389be MCC	194	/* This controls input */
	195	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
	196	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
	197	}
9701dc94 MCC	198	msleep(20);
9701dc94 MCC	199
29c389be MCC	200	/* Tuner firmware can now be loaded */
29c389be MCC	201
9701dc94 MCC	202	/FIXME: Hack!!! /
	203	struct v4l2_frequency f;
	204	mutex_lock(&dev->lock);
	205	f.frequency=dev->freq;
	206	tm6000_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
	207	mutex_unlock(&dev->lock);
	208
	209	msleep(100);
	210	tm6000_set_standard (dev, &dev->norm);
	211	tm6000_set_audio_bitrate (dev,48000);
	212
9701dc94 MCC	213	return 0;
	214	}
	215
3169c9b2 ML	216	int tm6000_init_digital_mode (struct tm6000_core *dev)
	217	{
	218	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08);
	219	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00);
	220	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01);
	221	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08);
	222	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
	223	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
	224	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
	225	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40);
	226	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0);
	227	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09);
	228	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37);
	229	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8);
	230	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0);
	231	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60);
4386136d ML	232
	233	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
	234	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
	235	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
3169c9b2 ML	236	msleep(50);
	237
	238	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
4386136d	239	msleep(50);
3169c9b2	240	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
4386136d	241	msleep(50);
3169c9b2	242	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
3169c9b2 ML	243	msleep(100);
	244
	245	return 0;
	246	}
9701dc94	247
29c389be MCC	248	struct reg_init {
	249	u8 req;
	250	u8 reg;
	251	u8 val;
	252	};
	253
9701dc94	254	/* The meaning of those initializations are unknown */
29c389be	255	struct reg_init tm6000_init_tab[] = {
9701dc94	256	/* REG VALUE */
29c389be MCC	257	{ REQ_07_SET_GET_AVREG, 0xdf, 0x1f },
	258	{ REQ_07_SET_GET_AVREG, 0xff, 0x08 },
	259	{ REQ_07_SET_GET_AVREG, 0xff, 0x00 },
	260	{ REQ_07_SET_GET_AVREG, 0xd5, 0x4f },
	261	{ REQ_07_SET_GET_AVREG, 0xda, 0x23 },
	262	{ REQ_07_SET_GET_AVREG, 0xdb, 0x08 },
	263	{ REQ_07_SET_GET_AVREG, 0xe2, 0x00 },
	264	{ REQ_07_SET_GET_AVREG, 0xe3, 0x10 },
	265	{ REQ_07_SET_GET_AVREG, 0xe5, 0x00 },
	266	{ REQ_07_SET_GET_AVREG, 0xe8, 0x00 },
	267	{ REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
	268	{ REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
	269	{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, /* Start of soft reset */
	270	{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
	271	{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
	272	{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
	273	{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
	274	{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
	275	{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
	276	{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
	277	{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
	278	{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
	279	{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
	280	{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
	281	{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
	282	{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
	283	{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
	284	{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
	285	{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
	286	{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
	287	{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
	288	{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
	289	{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
	290	{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
	291	{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
	292	{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
	293	{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
	294	{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
	295	{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
	296	{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
	297	{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
	298	{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
	299	{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
	300	{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
	301	{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
	302	{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
	303	{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
	304	{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
	305	{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
	306	{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
	307	{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
	308	{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
	309	{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
	310	{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
	311	{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
	312	{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
	313	{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
	314	{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
	315	{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
	316	{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
	317	{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
	318	{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, /* End of the soft reset */
	319	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
	320	};
321
322	struct reg_init tm6010_init_tab[] = {
323	{ REQ_07_SET_GET_AVREG, 0xc0, 0x00 },
324	{ REQ_07_SET_GET_AVREG, 0xc4, 0xa0 },
325	{ REQ_07_SET_GET_AVREG, 0xc6, 0x40 },
326	{ REQ_07_SET_GET_AVREG, 0xca, 0x31 },
327	{ REQ_07_SET_GET_AVREG, 0xcc, 0xe1 },
328	{ REQ_07_SET_GET_AVREG, 0xe0, 0x03 },
329	{ REQ_07_SET_GET_AVREG, 0xfe, 0x7f },
330
331	{ REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 },
332	{ REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 },
333	{ REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 },
334	{ REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 },
335	{ REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 },
336	{ REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 },
337	{ REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 },
338	{ REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 },
339	{ REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc },
340
341	{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 },
342	{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
343	{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
344	{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
345	{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
346	{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
347	{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
348	{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
349	{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
350	{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
351	{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
352	{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
353	{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
354	{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
355	{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
356	{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
357	{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
358	{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
359	{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
360	{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
361	{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
362	{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
363	{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
364	{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
365	{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
366	{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
367	{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
368	{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
369	{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
370	{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
371	{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
372	{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
373	{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
374	{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
375	{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
376	{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
377	{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
378	{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
379	{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
380	{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
381	{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
382	{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
383	{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
384	{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
385	{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
386	{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
387	{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
388	{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
389	{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
390	{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 },
391
392	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
393
394	/* set remote wakeup key:any key wakeup */
395	{ REQ_07_SET_GET_AVREG, 0xe5, 0xfe },
396	{ REQ_07_SET_GET_AVREG, 0xda, 0xff },
9701dc94 MCC	397	};
	398
	399	int tm6000_init (struct tm6000_core *dev)
	400	{
29c389be MCC	401	int board, rc=0, i, size;
	402	struct reg_init *tab;
	403
	404	if (dev->dev_type == TM6010) {
	405	tab = tm6010_init_tab;
	406	size = ARRAY_SIZE(tm6010_init_tab);
	407	} else {
	408	tab = tm6000_init_tab;
	409	size = ARRAY_SIZE(tm6000_init_tab);
	410	}
9701dc94	411
9701dc94	412	/* Load board's initialization table */
29c389be MCC	413	for (i=0; i< size; i++) {
29c389be MCC	414	rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
9701dc94	415	if (rc<0) {
29c389be MCC	416	printk (KERN_ERR "Error %i while setting req %d, "
	417	"reg %d to value %d\n", rc,
	418	tab[i].req,tab[i].reg, tab[i].val);
9701dc94 MCC	419	return rc;
	420	}
	421	}
	422
29c389be MCC	423	msleep(5); /* Just to be conservative */
29c389be MCC	424
9701dc94 MCC	425	/* Check board version - maybe 10Moons specific */
	426	board=tm6000_get_reg16 (dev, 0x40, 0, 0);
	427	if (board >=0) {
	428	printk (KERN_INFO "Board version = 0x%04x\n",board);
	429	} else {
	430	printk (KERN_ERR "Error %i while retrieving board version\n",board);
	431	}
	432
29c389be MCC	433	if (dev->dev_type == TM6010) {
	434	/* Turn xceive 3028 on */
	435	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6010_GPIO_3, 0x01);
	436	msleep(11);
	437	}
9701dc94	438
a5adfbed ML	439	/* Reset GPIO1 and GPIO4. */
a5adfbed ML	440	for (i=0; i< 2; i++) {
29c389be MCC	441	rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
29c389be MCC	442	dev->tuner_reset_gpio, 0x00);
9701dc94 MCC	443	if (rc<0) {
	444	printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
	445	return rc;
	446	}
	447
	448	msleep(10); /* Just to be conservative */
29c389be MCC	449	rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
29c389be MCC	450	dev->tuner_reset_gpio, 0x01);
9701dc94 MCC	451	if (rc<0) {
	452	printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
	453	return rc;
	454	}
	455
a5adfbed ML	456	msleep(10);
	457	rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 0);
	458	if (rc<0) {
	459	printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
	460	return rc;
	461	}
	462
	463	msleep(10);
	464	rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_4, 1);
	465	if (rc<0) {
	466	printk (KERN_ERR "Error %i doing GPIO4 reset\n",rc);
	467	return rc;
	468	}
	469
29c389be	470	if (!i) {
9701dc94	471	rc=tm6000_get_reg16(dev, 0x40,0,0);
29c389be MCC	472	if (rc>=0) {
	473	printk ("board=%d\n", rc);
	474	}
	475	}
9701dc94	476	}
a5adfbed ML	477
	478	msleep(50);
	479
d544f2c3	480	return 0;
9701dc94 MCC	481	}
9701dc94 MCC	482
44351aa0	483	int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94 MCC	484	{
	485	int val;
	486
	487	val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
	488	printk("Original value=%d\n",val);
	489	if (val<0)
	490	return val;
	491
	492	val &= 0x0f; /* Preserve the audio input control bits */
	493	switch (bitrate) {
	494	case 44100:
	495	val\|=0xd0;
c13dd704	496	dev->audio_bitrate=bitrate;
9701dc94 MCC	497	break;
	498	case 48000:
	499	val\|=0x60;
c13dd704	500	dev->audio_bitrate=bitrate;
9701dc94 MCC	501	break;
	502	}
	503	val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);
	504
	505	return val;
	506	}
44351aa0	507	EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);