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Merge remote branch 'alsa/devel' into topic/misc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / tm6000 / tm6000-core.c
CommitLineData
9701dc94 1/*
e28f49b0 2 tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
9701dc94
MCC		 3
4 Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
5
3169c9b2
ML		 6 Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
7 - DVB-T support
8
9701dc94
MCC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation version 2
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
4ef09889 25#include <linux/slab.h>
9701dc94
MCC		 26#include <linux/usb.h>
27#include <linux/i2c.h>
9701dc94
MCC		 28#include "tm6000.h"
29#include "tm6000-regs.h"
30#include <media/v4l2-common.h>
31#include <media/tuner.h>
32
9701dc94
MCC		 33#define USB_TIMEOUT 5*HZ /* ms */
34
52e0a72a
TT		 35int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req,
36 u16 value, u16 index, u8 *buf, u16 len)
9701dc94
MCC		 37{
38 int ret, i;
39 unsigned int pipe;
52e0a72a
TT		 40 static int ini = 0, last = 0, n = 0;
41 u8 *data = NULL;
9701dc94
MCC		 42
43 if (len)
44 data = kzalloc(len, GFP_KERNEL);
45
46
47 if (req_type & USB_DIR_IN)
52e0a72a 48 pipe = usb_rcvctrlpipe(dev->udev, 0);
9701dc94 49 else {
52e0a72a 50 pipe = usb_sndctrlpipe(dev->udev, 0);
9701dc94
MCC		 51 memcpy(data, buf, len);
52 }
53
edecce0a 54 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94 55 if (!ini)
52e0a72a 56 last = ini = jiffies;
9701dc94
MCC		 57
58 printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
59
52e0a72a
TT		 60 printk("%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
61 (req_type & USB_DIR_IN) ? " IN" : "OUT",
9701dc94
MCC		 62 jiffies_to_msecs(jiffies-last),
63 jiffies_to_msecs(jiffies-ini),
52e0a72a
TT		 64 req_type, req, value&0xff, value>>8, index&0xff,
65 index>>8, len&0xff, len>>8);
66 last = jiffies;
9701dc94
MCC		 67 n++;
68
52e0a72a 69 if (!(req_type & USB_DIR_IN)) {
9701dc94 70 printk(">>> ");
52e0a72a
TT		 71 for (i = 0; i < len; i++)
72 printk(" %02x", buf[i]);
8ae1fc6e 73 printk("\n");
9701dc94
MCC		 74 }
75 }
76
52e0a72a
TT		 77 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index,
78 data, len, USB_TIMEOUT);
9701dc94
MCC		 79
80 if (req_type & USB_DIR_IN)
81 memcpy(buf, data, len);
82
edecce0a 83 if (tm6000_debug & V4L2_DEBUG_I2C) {
52e0a72a 84 if (ret < 0) {
9701dc94 85 if (req_type & USB_DIR_IN)
52e0a72a 86 printk("<<< (len=%d)\n", len);
9701dc94
MCC		 87
88 printk("%s: Error #%d\n", __FUNCTION__, ret);
89 } else if (req_type & USB_DIR_IN) {
90 printk("<<< ");
52e0a72a
TT		 91 for (i = 0; i < len; i++)
92 printk(" %02x", buf[i]);
9701dc94
MCC		 93 printk("\n");
94 }
95 }
96
97 kfree(data);
98
a5adfbed
ML		 99 msleep(5);
100
9701dc94
MCC		 101 return ret;
102}
103
52e0a72a 104int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 105{
106 return
52e0a72a
TT		 107 tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
108 req, value, index, NULL, 0);
9701dc94 109}
29ec15e9 110EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94 111
52e0a72a 112int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 113{
114 int rc;
115 u8 buf[1];
116
52e0a72a
TT		 117 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
118 value, index, buf, 1);
9701dc94 119
52e0a72a 120 if (rc < 0)
9701dc94
MCC		 121 return rc;
122
123 return *buf;
124}
29ec15e9 125EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94 126
52e0a72a 127int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index)
9701dc94
MCC		 128{
129 int rc;
130 u8 buf[2];
131
52e0a72a
TT		 132 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
133 value, index, buf, 2);
9701dc94 134
52e0a72a 135 if (rc < 0)
9701dc94
MCC		 136 return rc;
137
138 return buf[1]|buf[0]<<8;
139}
140
52e0a72a 141int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index)
2f790884
SR		 142{
143 int rc;
144 u8 buf[4];
145
52e0a72a
TT		 146 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
147 value, index, buf, 4);
2f790884 148
52e0a72a 149 if (rc < 0)
2f790884
SR		 150 return rc;
151
152 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
153}
154
2a15ac7a
DB		 155int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
156{
157 int rc;
158
159 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
160 if (rc < 0)
161 return rc;
162
163 msleep(tsleep);
164
165 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
166 msleep(tsleep);
167
168 return rc;
169}
170
9701dc94
MCC		 171void tm6000_set_fourcc_format(struct tm6000_core *dev)
172{
717ecd2b 173 if (dev->dev_type == TM6010) {
42238713
MCC		 174 int val;
175
176 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0) & 0xfc;
717ecd2b 177 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
42238713 178 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
717ecd2b 179 else
42238713 180 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val | 1);
9701dc94 181 } else {
717ecd2b 182 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493 183 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b 184 else
9afec493 185 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94
MCC		 186 }
187}
188
52e0a72a 189int tm6000_init_analog_mode(struct tm6000_core *dev)
9701dc94 190{
29c389be
MCC		 191 if (dev->dev_type == TM6010) {
192 int val;
9701dc94 193
29c389be 194 /* Enable video */
9afec493 195 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
29c389be 196 val |= 0x60;
9afec493 197 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
120756e1
SR		 198 val = tm6000_get_reg(dev,
199 TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
200 val &= ~0x40;
201 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
202
203 /* Init teletext */
204 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
205 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
206 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
207 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
208 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
209 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
210 tm6000_set_reg(dev,
211 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
212 tm6000_set_reg(dev,
213 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
214 tm6000_set_reg(dev,
215 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
216 tm6000_set_reg(dev,
217 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
218 tm6000_set_reg(dev,
219 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
220 tm6000_set_reg(dev,
221 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
222 tm6000_set_reg(dev,
223 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
224 tm6000_set_reg(dev,
225 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
226 tm6000_set_reg(dev,
227 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
228 tm6000_set_reg(dev,
229 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
230 tm6000_set_reg(dev,
231 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
232 tm6000_set_reg(dev,
233 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
234 tm6000_set_reg(dev,
235 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
236 tm6000_set_reg(dev,
237 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
238 tm6000_set_reg(dev,
239 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
240 tm6000_set_reg(dev,
241 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
242 tm6000_set_reg(dev,
243 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
244 tm6000_set_reg(dev,
245 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
246 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
247 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
248 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
249 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
250 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
251 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
252
253
254 /* Init audio */
255 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
256 tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04);
257 tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
258 tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0);
259 tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x05);
260 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x06);
261 tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00);
262 tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00);
263 tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08);
264 tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91);
265 tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20);
266 tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12);
267 tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20);
268 tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0);
269 tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80);
270 tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0);
271 tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80);
272 tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12);
273 tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe);
274 tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20);
275 tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14);
276 tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe);
277 tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01);
278 tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0);
279 tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32);
280 tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64);
281 tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20);
282 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00);
283 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00);
284 tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
285 tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
286 tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
287 tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
288 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
289 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
9701dc94 290
9701dc94 291 } else {
29c389be 292 /* Enables soft reset */
9afec493 293 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be 294
52e0a72a 295 if (dev->scaler)
9afec493 296 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
52e0a72a 297 else /* Enable Hfilter and disable TS Drop err */
9afec493 298 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
9701dc94 299
9afec493
MCC		 300 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
301 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
302 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
303 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
304 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
305 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
9701dc94 306
29c389be 307 /* AP Software reset */
9afec493
MCC		 308 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
309 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94 310
29c389be 311 tm6000_set_fourcc_format(dev);
9701dc94 312
29c389be 313 /* Disables soft reset */
9afec493 314 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
9701dc94 315
29c389be 316 /* E3: Select input 0 - TV tuner */
9afec493 317 tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
29c389be 318 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94 319
29c389be
MCC		 320 /* This controls input */
321 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
322 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
323 }
9701dc94
MCC		 324 msleep(20);
325
29c389be
MCC		 326 /* Tuner firmware can now be loaded */
327
9701dc94
MCC		 328 /*FIXME: Hack!!! */
329 struct v4l2_frequency f;
330 mutex_lock(&dev->lock);
52e0a72a 331 f.frequency = dev->freq;
427f7fac 332 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94
MCC		 333 mutex_unlock(&dev->lock);
334
335 msleep(100);
52e0a72a
TT		 336 tm6000_set_standard(dev, &dev->norm);
337 tm6000_set_audio_bitrate(dev, 48000);
9701dc94 338
f36cc034
SR		 339 /* switch dvb led off */
340 if (dev->gpio.dvb_led) {
341 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
342 dev->gpio.dvb_led, 0x01);
343 }
344
9701dc94
MCC		 345 return 0;
346}
347
52e0a72a 348int tm6000_init_digital_mode(struct tm6000_core *dev)
3169c9b2 349{
c733a4d5
SR		 350 if (dev->dev_type == TM6010) {
351 int val;
352 u8 buf[2];
3169c9b2 353
c733a4d5 354 /* digital init */
9afec493 355 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
c733a4d5 356 val &= ~0x60;
9afec493
MCC		 357 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
358 val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
c733a4d5 359 val |= 0x40;
9afec493
MCC		 360 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
361 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
362 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
363 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
364 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
52e0a72a
TT		 365 tm6000_read_write_usb(dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
366 printk(KERN_INFO"buf %#x %#x\n", buf[0], buf[1]);
c733a4d5 367 } else {
9afec493
MCC		 368 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
369 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
370 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
371 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
372 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
373 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
52e0a72a 374 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
9afec493
MCC		 375 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
376 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
377 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
378 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
379 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
380 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
381 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
382
383 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
384 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
52e0a72a 385 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
c733a4d5
SR		 386 msleep(50);
387
52e0a72a 388 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
c733a4d5 389 msleep(50);
52e0a72a 390 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
c733a4d5 391 msleep(50);
52e0a72a 392 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
c733a4d5
SR		 393 msleep(100);
394 }
f36cc034
SR		 395
396 /* switch dvb led on */
397 if (dev->gpio.dvb_led) {
398 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
399 dev->gpio.dvb_led, 0x00);
400 }
401
3169c9b2
ML		 402 return 0;
403}
cee3926f 404EXPORT_SYMBOL(tm6000_init_digital_mode);
9701dc94 405
29c389be
MCC		 406struct reg_init {
407 u8 req;
408 u8 reg;
409 u8 val;
410};
411
9701dc94 412/* The meaning of those initializations are unknown */
29c389be 413struct reg_init tm6000_init_tab[] = {
9701dc94 414 /* REG VALUE */
9afec493
MCC		 415 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
416 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
417 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
418 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
419 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
420 { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
421 { TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
422 { TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
423 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
424 { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
29c389be
MCC		 425 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
426 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
9afec493
MCC		 427 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
428 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
429 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
430 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
431 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
432 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
433 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
434 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
435 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
436 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
437 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
438 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
439 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
440 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
441 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
442 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
443 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
444 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
445 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
446 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
447 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
448 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
449 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
450 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
451 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
452 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
453 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
454 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
455 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
456 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
457 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
458 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
459 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
460 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
461 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
462 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
463 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
464 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
465 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
466 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
467 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
468 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
469 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
470 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
471 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
472 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
473 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
474 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
475 { TM6010_REQ07_RC3_HSTART1, 0x88 },
476 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
2415a2c1 477 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be
MCC		 478};
479
480struct reg_init tm6010_init_tab[] = {
9afec493
MCC		 481 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
482 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
483 { TM6010_REQ07_RC6_HEND0, 0x40 },
484 { TM6010_REQ07_RCA_VEND0, 0x31 },
485 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
486 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
487 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
488
489 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
490 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
491 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
492 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
493 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
494 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
495 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
496 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
497 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
498
499 { TM6010_REQ07_R3F_RESET, 0x01 },
500 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
501 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
502 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
503 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
504 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
505 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
506 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
507 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
508 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
509 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
510 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
511 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
512 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
513 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
514 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
515 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
516 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
517 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
518 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
519 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
520 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
521 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
522 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
523 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
524 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
525 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
526 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
527 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
528 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
529 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
530 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
531 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
532 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
533 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
534 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
535 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
536 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
537 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
538 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
539 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
540 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
541 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
542 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
543 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
544 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
545 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
546 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
547 { TM6010_REQ07_RC3_HSTART1, 0x88 },
548 { TM6010_REQ07_R3F_RESET, 0x00 },
29c389be 549
2415a2c1 550 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be 551
9afec493
MCC		 552 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
553 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
554 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
555 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932 556 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493 557 { TM6010_REQ07_RD8_IR, 0x2f },
d46ca932 558
29c389be 559 /* set remote wakeup key:any key wakeup */
9afec493
MCC		 560 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
561 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94
MCC		 562};
563
52e0a72a 564int tm6000_init(struct tm6000_core *dev)
9701dc94 565{
52e0a72a 566 int board, rc = 0, i, size;
29c389be
MCC		 567 struct reg_init *tab;
568
569 if (dev->dev_type == TM6010) {
570 tab = tm6010_init_tab;
571 size = ARRAY_SIZE(tm6010_init_tab);
572 } else {
573 tab = tm6000_init_tab;
574 size = ARRAY_SIZE(tm6000_init_tab);
575 }
9701dc94 576
9701dc94 577 /* Load board's initialization table */
52e0a72a
TT		 578 for (i = 0; i < size; i++) {
579 rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val);
580 if (rc < 0) {
581 printk(KERN_ERR "Error %i while setting req %d, "
582 "reg %d to value %d\n", rc,
583 tab[i].req, tab[i].reg, tab[i].val);
9701dc94
MCC		 584 return rc;
585 }
586 }
587
29c389be
MCC		 588 msleep(5); /* Just to be conservative */
589
9701dc94 590 /* Check board version - maybe 10Moons specific */
52e0a72a
TT		 591 board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0);
592 if (board >= 0)
593 printk(KERN_INFO "Board version = 0x%08x\n", board);
594 else
595 printk(KERN_ERR "Error %i while retrieving board version\n", board);
9701dc94 596
e3ee9e5e 597 rc = tm6000_cards_setup(dev);
a5adfbed 598
e3ee9e5e 599 return rc;
9701dc94
MCC		 600}
601
44351aa0 602int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94
MCC		 603{
604 int val;
605
a59bff37
MCC		 606 if (dev->dev_type == TM6010) {
607 val = tm6000_get_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0);
608 if (val < 0)
609 return val;
610 val = (val & 0xf0) | 0x1; /* 48 kHz, not muted */
611 val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, val);
612 if (val < 0)
613 return val;
614 }
615
52e0a72a 616 val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
52e0a72a 617 if (val < 0)
9701dc94
MCC		 618 return val;
619
620 val &= 0x0f; /* Preserve the audio input control bits */
621 switch (bitrate) {
622 case 44100:
52e0a72a
TT		 623 val |= 0xd0;
624 dev->audio_bitrate = bitrate;
9701dc94
MCC		 625 break;
626 case 48000:
52e0a72a
TT		 627 val |= 0x60;
628 dev->audio_bitrate = bitrate;
9701dc94
MCC		 629 break;
630 }
52e0a72a 631 val = tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, val);
9701dc94
MCC		 632
633 return val;
634}
44351aa0 635EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
0439db75
SR		 636
637static LIST_HEAD(tm6000_devlist);
638static DEFINE_MUTEX(tm6000_devlist_mutex);
639
640/*
641 * tm6000_realease_resource()
642 */
643
644void tm6000_remove_from_devlist(struct tm6000_core *dev)
645{
646 mutex_lock(&tm6000_devlist_mutex);
647 list_del(&dev->devlist);
648 mutex_unlock(&tm6000_devlist_mutex);
649};
650
651void tm6000_add_into_devlist(struct tm6000_core *dev)
652{
653 mutex_lock(&tm6000_devlist_mutex);
654 list_add_tail(&dev->devlist, &tm6000_devlist);
655 mutex_unlock(&tm6000_devlist_mutex);
656};
657
658/*
659 * Extension interface
660 */
661
662static LIST_HEAD(tm6000_extension_devlist);
663static DEFINE_MUTEX(tm6000_extension_devlist_lock);
664
b17b8699
MCC		 665int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type,
666 char *buf, int size)
667{
668 struct tm6000_ops *ops = NULL;
669
670 /* FIXME: tm6000_extension_devlist_lock should be a spinlock */
671
672 if (!list_empty(&tm6000_extension_devlist)) {
673 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
674 if (ops->fillbuf && ops->type == type)
675 ops->fillbuf(dev, buf, size);
676 }
677 }
678
679 return 0;
680}
681
0439db75
SR		 682int tm6000_register_extension(struct tm6000_ops *ops)
683{
684 struct tm6000_core *dev = NULL;
685
686 mutex_lock(&tm6000_devlist_mutex);
687 mutex_lock(&tm6000_extension_devlist_lock);
688 list_add_tail(&ops->next, &tm6000_extension_devlist);
689 list_for_each_entry(dev, &tm6000_devlist, devlist) {
3f23a81a
MCC		 690 ops->init(dev);
691 printk(KERN_INFO "%s: Initialized (%s) extension\n",
692 dev->name, ops->name);
0439db75 693 }
0439db75
SR		 694 mutex_unlock(&tm6000_extension_devlist_lock);
695 mutex_unlock(&tm6000_devlist_mutex);
696 return 0;
697}
698EXPORT_SYMBOL(tm6000_register_extension);
699
700void tm6000_unregister_extension(struct tm6000_ops *ops)
701{
702 struct tm6000_core *dev = NULL;
703
704 mutex_lock(&tm6000_devlist_mutex);
705 list_for_each_entry(dev, &tm6000_devlist, devlist) {
706 if (dev)
707 ops->fini(dev);
708 }
709
710 mutex_lock(&tm6000_extension_devlist_lock);
711 printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
712 list_del(&ops->next);
713 mutex_unlock(&tm6000_extension_devlist_lock);
714 mutex_unlock(&tm6000_devlist_mutex);
715}
716EXPORT_SYMBOL(tm6000_unregister_extension);
717
718void tm6000_init_extension(struct tm6000_core *dev)
719{
720 struct tm6000_ops *ops = NULL;
721
722 mutex_lock(&tm6000_extension_devlist_lock);
723 if (!list_empty(&tm6000_extension_devlist)) {
724 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
725 if (ops->init)
726 ops->init(dev);
727 }
728 }
729 mutex_unlock(&tm6000_extension_devlist_lock);
730}
731
732void tm6000_close_extension(struct tm6000_core *dev)
733{
734 struct tm6000_ops *ops = NULL;
735
736 mutex_lock(&tm6000_extension_devlist_lock);
737 if (!list_empty(&tm6000_extension_devlist)) {
738 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
739 if (ops->fini)
740 ops->fini(dev);
741 }
742 }
743 mutex_unlock(&tm6000_extension_devlist_lock);
744}
kernel source for telekom puls (alcatel/mediatek)