[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / tidspbridge / Kconfig

#
# DSP Bridge Driver Support
#

menuconfig TIDSPBRIDGE
	tristate "DSP Bridge driver"
	depends on ARCH_OMAP3
	select OMAP_MBOX_FWK
	help
	  DSP/BIOS Bridge is designed for platforms that contain a GPP and
	  one or more attached DSPs.  The GPP is considered the master or
	  "host" processor, and the attached DSPs are processing resources
	  that can be utilized by applications and drivers running on the GPP.

	  This driver depends on OMAP Mailbox (OMAP_MBOX_FWK).

config TIDSPBRIDGE_DVFS
	bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)"
	depends on TIDSPBRIDGE && OMAP_PM_SRF && CPU_FREQ
	help
	  DVFS allows DSP Bridge to initiate the operating point change to
	  scale the chip voltage and frequency in order to match the
	  performance and power consumption to the current processing
	  requirements.

config TIDSPBRIDGE_MEMPOOL_SIZE
	hex "Physical memory pool size (Byte)"
	depends on TIDSPBRIDGE
	default 0x600000
	help
	  Allocate specified size of memory at booting time to avoid allocation
	  failure under heavy memory fragmentation after some use time.

config TIDSPBRIDGE_DEBUG
	bool "Debug Support"
	depends on TIDSPBRIDGE
	help
	  Say Y to enable Bridge debugging capabilities

config TIDSPBRIDGE_RECOVERY
	bool "Recovery Support"
	depends on TIDSPBRIDGE
	default y
	help
	  In case of DSP fatal error, BRIDGE driver will try to
	  recover itself.

config TIDSPBRIDGE_CACHE_LINE_CHECK
	bool "Check buffers to be 128 byte aligned"
	depends on TIDSPBRIDGE
	help
	  When the DSP processes data, the DSP cache controller loads 128-Byte
	  chunks (lines) from SDRAM and writes the data back in 128-Byte chunks.
	  If a DMM buffer does not start and end on a 128-Byte boundary, the data
	  preceding the start address (SA) from the 128-Byte boundary to the SA
	  and the data at addresses trailing the end address (EA) from the EA to
	  the next 128-Byte boundary will be loaded and written back as well.
	  This can lead to heap corruption. Say Y, to enforce the check for 128
	  byte alignment, buffers failing this check will be rejected.

config TIDSPBRIDGE_WDT3
	bool "Enable watchdog timer"
	depends on TIDSPBRIDGE
	help
	  WTD3 is managed by DSP and once it is enabled, DSP side bridge is in
	  charge of refreshing the timer before overflow, if the DSP hangs MPU
	  will caught the interrupt and try to recover DSP.

config TIDSPBRIDGE_WDT_TIMEOUT
	int "Watchdog timer timeout (in secs)"
	depends on TIDSPBRIDGE && TIDSPBRIDGE_WDT3
	default 5
	help
	   Watchdog timer timeout value, after that time if the watchdog timer
	   counter is not reset the wdt overflow interrupt will be triggered

config TIDSPBRIDGE_NTFY_PWRERR
	bool "Notify power errors"
	depends on TIDSPBRIDGE
	help
	  Enable notifications to registered clients on the event of power errror
	  trying to suspend bridge driver. Say Y, to signal this event as a fatal
	  error, this will require a bridge restart to recover.

config TIDSPBRIDGE_BACKTRACE
	bool "Dump backtraces on fatal errors"
	depends on TIDSPBRIDGE
	help
	  Enable useful information to backtrace fatal errors. Say Y if you
	  want to dump information for testing purposes.
Commit	Line	Data
cbf05091 ORL	1	#
	2	# DSP Bridge Driver Support
	3	#
	4
	5	menuconfig TIDSPBRIDGE
	6	tristate "DSP Bridge driver"
	7	depends on ARCH_OMAP3
	8	select OMAP_MBOX_FWK
	9	help
	10	DSP/BIOS Bridge is designed for platforms that contain a GPP and
	11	one or more attached DSPs. The GPP is considered the master or
	12	"host" processor, and the attached DSPs are processing resources
	13	that can be utilized by applications and drivers running on the GPP.
	14
	15	This driver depends on OMAP Mailbox (OMAP_MBOX_FWK).
	16
b3d23688	17	config TIDSPBRIDGE_DVFS
cbf05091 ORL	18	bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)"
cbf05091 ORL	19	depends on TIDSPBRIDGE && OMAP_PM_SRF && CPU_FREQ
cbf05091 ORL	20	help
	21	DVFS allows DSP Bridge to initiate the operating point change to
	22	scale the chip voltage and frequency in order to match the
	23	performance and power consumption to the current processing
	24	requirements.
	25
b3d23688	26	config TIDSPBRIDGE_MEMPOOL_SIZE
cbf05091 ORL	27	hex "Physical memory pool size (Byte)"
	28	depends on TIDSPBRIDGE
	29	default 0x600000
	30	help
	31	Allocate specified size of memory at booting time to avoid allocation
	32	failure under heavy memory fragmentation after some use time.
	33
b3d23688	34	config TIDSPBRIDGE_DEBUG
ed9ff5d7	35	bool "Debug Support"
cbf05091 ORL	36	depends on TIDSPBRIDGE
	37	help
	38	Say Y to enable Bridge debugging capabilities
	39
b3d23688	40	config TIDSPBRIDGE_RECOVERY
ed9ff5d7	41	bool "Recovery Support"
cbf05091	42	depends on TIDSPBRIDGE
ed9ff5d7	43	default y
cbf05091 ORL	44	help
	45	In case of DSP fatal error, BRIDGE driver will try to
	46	recover itself.
	47
b3d23688	48	config TIDSPBRIDGE_CACHE_LINE_CHECK
cbf05091 ORL	49	bool "Check buffers to be 128 byte aligned"
cbf05091 ORL	50	depends on TIDSPBRIDGE
cbf05091 ORL	51	help
	52	When the DSP processes data, the DSP cache controller loads 128-Byte
	53	chunks (lines) from SDRAM and writes the data back in 128-Byte chunks.
	54	If a DMM buffer does not start and end on a 128-Byte boundary, the data
	55	preceding the start address (SA) from the 128-Byte boundary to the SA
	56	and the data at addresses trailing the end address (EA) from the EA to
	57	the next 128-Byte boundary will be loaded and written back as well.
	58	This can lead to heap corruption. Say Y, to enforce the check for 128
	59	byte alignment, buffers failing this check will be rejected.
	60
b3d23688	61	config TIDSPBRIDGE_WDT3
ed9ff5d7	62	bool "Enable watchdog timer"
cbf05091	63	depends on TIDSPBRIDGE
cbf05091 ORL	64	help
	65	WTD3 is managed by DSP and once it is enabled, DSP side bridge is in
	66	charge of refreshing the timer before overflow, if the DSP hangs MPU
	67	will caught the interrupt and try to recover DSP.
	68
b3d23688	69	config TIDSPBRIDGE_WDT_TIMEOUT
ed9ff5d7 FC	70	int "Watchdog timer timeout (in secs)"
ed9ff5d7 FC	71	depends on TIDSPBRIDGE && TIDSPBRIDGE_WDT3
cbf05091 ORL	72	default 5
	73	help
	74	Watchdog timer timeout value, after that time if the watchdog timer
	75	counter is not reset the wdt overflow interrupt will be triggered
	76
b3d23688	77	config TIDSPBRIDGE_NTFY_PWRERR
ed9ff5d7	78	bool "Notify power errors"
cbf05091 ORL	79	depends on TIDSPBRIDGE
	80	help
	81	Enable notifications to registered clients on the event of power errror
	82	trying to suspend bridge driver. Say Y, to signal this event as a fatal
	83	error, this will require a bridge restart to recover.
4f551c8f FC	84
	85	config TIDSPBRIDGE_BACKTRACE
	86	bool "Dump backtraces on fatal errors"
	87	depends on TIDSPBRIDGE
	88	help
	89	Enable useful information to backtrace fatal errors. Say Y if you
	90	want to dump information for testing purposes.