Staging: sep: Try and get kernel address and user address types right
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / sep / sep_dev.h
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1#ifndef __SEP_DEV_H__
2#define __SEP_DEV_H__
3
4/*
5 *
6 * sep_dev.h - Security Processor Device Structures
7 *
8 * Copyright(c) 2009 Intel Corporation. All rights reserved.
9 * Copyright(c) 2009 Discretix. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Alan Cox alan@linux.intel.com
28 *
29 */
30
31struct sep_device {
32 /* pointer to pci dev */
904290c0 33 struct pci_dev *pdev;
f5e3980f 34
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35 unsigned long io_bus;
36 unsigned long io_end_bus;
f5e3980f 37 unsigned long io_memory_size;
904290c0 38 void __iomem *io_addr;
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39
40 /* restricted access region */
790cf1b9 41 dma_addr_t rar_bus;
904290c0 42 void *rar_addr;
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43
44 /* shared memory region */
790cf1b9 45 dma_addr_t shared_bus;
904290c0 46 void *shared_addr;
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47
48 /* firmware regions */
790cf1b9 49 dma_addr_t cache_bus;
f5e3980f 50 unsigned long cache_size;
904290c0 51 void *cache_addr;
f5e3980f 52
790cf1b9 53 dma_addr_t resident_bus;
f5e3980f 54 unsigned long resident_size;
904290c0 55 void *resident_addr;
f5e3980f 56
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57 unsigned long rar_region_addr;
58
59 /* start address of the access to the SEP registers from driver */
904290c0 60 void __iomem *reg_addr;
f5e3980f 61 /* transaction counter that coordinates the transactions between SEP and HOST */
904290c0 62 unsigned long send_ct;
f5e3980f 63 /* counter for the messages from sep */
904290c0 64 unsigned long reply_ct;
f5e3980f 65 /* counter for the number of bytes allocated in the pool for the current
d19cf32f 66 transaction */
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67 unsigned long data_pool_bytes_allocated;
68
69 /* array of pointers to the pages that represent input data for the synchronic
d19cf32f 70 DMA action */
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71 struct page **in_page_array;
72
73 /* array of pointers to the pages that represent out data for the synchronic
d19cf32f 74 DMA action */
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75 struct page **out_page_array;
76
77 /* number of pages in the sep_in_page_array */
78 unsigned long in_num_pages;
79
80 /* number of pages in the sep_out_page_array */
81 unsigned long out_num_pages;
82
83 /* global data for every flow */
904290c0 84 struct sep_flow_context_t flows[SEP_DRIVER_NUM_FLOWS];
f5e3980f 85
f5e3980f 86 /* pointer to the workqueue that handles the flow done interrupts */
904290c0 87 struct workqueue_struct *flow_wq;
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88
89 /* address of the shared memory allocated during init for SEP driver */
790cf1b9 90 void *shared_area;
f5e3980f 91 /* the physical address of the shared area */
790cf1b9 92 dma_addr_t shared_area_bus;
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93
94 /* Message Shared Area start address - will be allocated during init */
790cf1b9 95 void *message_shared_area_addr;
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96};
97
b10b483e 98static struct sep_device *sep_dev;
f5e3980f 99
79de99e8 100static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
f5e3980f 101{
904290c0 102 void __iomem *addr = dev->reg_addr + reg;
79de99e8 103 writel(value, addr);
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104}
105
79de99e8 106static inline u32 sep_read_reg(struct sep_device *dev, int reg)
f5e3980f 107{
904290c0 108 void __iomem *addr = dev->reg_addr + reg;
79de99e8 109 return readl(addr);
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110}
111
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112/* wait for SRAM write complete(indirect write */
113static inline void sep_wait_sram_write(struct sep_device *dev)
114{
115 u32 reg_val;
116 do
117 reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
d19cf32f 118 while (!(reg_val & 1));
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119}
120
121
f5e3980f 122#endif