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Merge branch 'disintegrate-asm-generic' of git://git.infradead.org/users/dhowells...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rts5139 / rts51x_chip.h
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1dac4186 1/* Driver for Realtek RTS51xx USB card reader
2 * Header file
3 *
4 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2, or (at your option) any
9 * later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 * Author:
20 * wwang (wei_wang@realsil.com.cn)
21 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
22 * Maintainer:
23 * Edwin Rong (edwin_rong@realsil.com.cn)
24 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
25 */
26
27#ifndef __RTS51X_CHIP_H
28#define __RTS51X_CHIP_H
29
30#include <linux/usb.h>
31#include <linux/usb_usual.h>
32#include <linux/blkdev.h>
33#include <linux/completion.h>
34#include <linux/mutex.h>
35#include <scsi/scsi_host.h>
36
37#include "trace.h"
38
39#define SUPPORT_CPRM
40#define SUPPORT_MAGIC_GATE
41#define SUPPORT_MSXC
63bb174d 42#define USING_POLLING_CYCLE_DELINK
1dac4186 43
44#ifdef SUPPORT_MAGIC_GA
45/* Using NORMAL_WRITE instead of AUTO_WRITE to set ICVTE */
46#define MG_SET_ICV_SLOW
47#endif
48
49#ifdef SUPPORT_MSXC
50#define XC_POWERCLASS
51#define SUPPORT_PCGL_1P18
52#endif
53
54#define GET_CARD_STATUS_USING_EPC
55
56#define CLOSE_SSC_POWER
57
58#define SUPPORT_OCP
59
60#define MS_SPEEDUP
1dac4186 61
62#define SD_XD_IO_FOLLOW_PWR
63
64#define SD_NR 2
65#define MS_NR 3
66#define XD_NR 4
67#define SD_CARD (1 << SD_NR)
68#define MS_CARD (1 << MS_NR)
69#define XD_CARD (1 << XD_NR)
70
71#define SD_CD 0x01
72#define MS_CD 0x02
73#define XD_CD 0x04
74#define SD_WP 0x08
75
76#define MAX_ALLOWED_LUN_CNT 8
77#define CMD_BUF_LEN 1024
1dac4186 78#define POLLING_INTERVAL 50 /* 50ms */
79
80#define XD_FREE_TABLE_CNT 1200
81#define MS_FREE_TABLE_CNT 512
82
83/* Bit Operation */
84#define SET_BIT(data, idx) ((data) |= 1 << (idx))
85#define CLR_BIT(data, idx) ((data) &= ~(1 << (idx)))
86#define CHK_BIT(data, idx) ((data) & (1 << (idx)))
87
88/* Command type */
89#define READ_REG_CMD 0
90#define WRITE_REG_CMD 1
91#define CHECK_REG_CMD 2
92
93#define PACKET_TYPE 4
94#define CNT_H 5
95#define CNT_L 6
96#define STAGE_FLAG 7
97#define CMD_OFFSET 8
98
99/* Packet type */
100#define BATCH_CMD 0
101#define SEQ_READ 1
102#define SEQ_WRITE 2
103
104/* Stage flag */
105#define STAGE_R 0x01
106#define STAGE_DI 0x02
107#define STAGE_DO 0x04
108/* Return MS_TRANS_CFG, GET_INT */
109#define STAGE_MS_STATUS 0x08
110/* Return XD_CFG, XD_CTL, XD_PAGE_STATUS */
111#define STAGE_XD_STATUS 0x10
112/* Command stage mode */
113#define MODE_C 0x00
114#define MODE_CR (STAGE_R)
115#define MODE_CDIR (STAGE_R | STAGE_DI)
116#define MODE_CDOR (STAGE_R | STAGE_DO)
117
118/* Function return code */
119#ifndef STATUS_SUCCESS
120#define STATUS_SUCCESS 0
121#endif
122
123#define STATUS_FAIL 1
1dac4186 124#define STATUS_TIMEDOUT 4
125#define STATUS_NOMEM 5
126#define STATUS_TRANS_SHORT 6
127#define STATUS_TRANS_LONG 7
128#define STATUS_STALLED 8
129#define STATUS_ERROR 10
130
131#define IDLE_MAX_COUNT 10
132#define POLLING_WAIT_CNT 1
1dac4186 133#define LED_GPIO 0
134
135/* package */
136#define QFN24 0
137#define LQFP48 1
138
139#define USB_11 0
140#define USB_20 1
141
142/*
143 * Transport return codes
144 */
145/* Transport good, command good */
146#define TRANSPORT_GOOD 0
147/* Transport good, command failed */
148#define TRANSPORT_FAILED 1
1dac4186 149/* Transport bad (i.e. device dead) */
150#define TRANSPORT_ERROR 3
151
152/* Supported Clock */
153enum card_clock { CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, CLK_80, CLK_100 };
154
155#ifdef _MSG_TRACE
156
157#define TRACE_ITEM_CNT 64
158
159struct trace_msg_t {
160 u16 line;
161#define MSG_FUNC_LEN 64
162 char func[MSG_FUNC_LEN];
163#define MSG_FILE_LEN 32
164 char file[MSG_FILE_LEN];
165#define TIME_VAL_LEN 16
166 u8 timeval_buf[TIME_VAL_LEN];
167 u8 valid;
168};
169
170#endif /* _MSG_TRACE */
171
172/* Size of the autosense data buffer */
173#define SENSE_SIZE 18
174
175/* Sense type */
176#define SENSE_TYPE_NO_SENSE 0
177#define SENSE_TYPE_MEDIA_CHANGE 1
178#define SENSE_TYPE_MEDIA_NOT_PRESENT 2
179#define SENSE_TYPE_MEDIA_LBA_OVER_RANGE 3
180#define SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT 4
181#define SENSE_TYPE_MEDIA_WRITE_PROTECT 5
182#define SENSE_TYPE_MEDIA_INVALID_CMD_FIELD 6
183#define SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR 7
184#define SENSE_TYPE_MEDIA_WRITE_ERR 8
1dac4186 185#define SENSE_TYPE_FORMAT_CMD_FAILED 10
186#ifdef SUPPORT_MAGIC_GATE
187/* COPY PROTECTION KEY EXCHANGE FAILURE - KEY NOT ESTABLISHED */
188#define SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB 0x0b
189/* COPY PROTECTION KEY EXCHANGE FAILURE - AUTHENTICATION FAILURE */
190#define SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN 0x0c
191/* INCOMPATIBLE MEDIUM INSTALLED */
192#define SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM 0x0d
193/* WRITE ERROR */
194#define SENSE_TYPE_MG_WRITE_ERR 0x0e
195#endif
1dac4186 196
197/*---- sense key ----*/
1dac4186 198#define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */
1dac4186 199
200/*-----------------------------------
201 SENSE_DATA
202-----------------------------------*/
1dac4186 203
204/*---- error code ----*/
205#define CUR_ERR 0x70 /* current error */
1dac4186 206
0cf5755f 207/*---- sense key Information ----*/
1dac4186 208
209#define SKSV 0x80
210#define CDB_ILLEGAL 0x40
1dac4186 211
212/*---- ASC ----*/
1dac4186 213#define ASC_INVLD_CDB 0x24
1dac4186 214
215/*---- ASQC ----*/
1dac4186 216#define ASCQ_INVLD_CDB 0x00
1dac4186 217
218struct sense_data_t {
219 unsigned char err_code; /* error code */
220 /* bit7 : valid */
221 /* (1 : SCSI2) */
222 /* (0 : Vendor specific) */
223 /* bit6-0 : error code */
224 /* (0x70 : current error) */
225 /* (0x71 : specific command error) */
226 unsigned char seg_no; /* segment No. */
227 unsigned char sense_key; /* byte5 : ILI */
228 /* bit3-0 : sense key */
feb5680e 229 unsigned char info[4]; /* information */
1dac4186 230 unsigned char ad_sense_len; /* additional sense data length */
feb5680e 231 unsigned char cmd_info[4]; /* command specific information */
1dac4186 232 unsigned char asc; /* ASC */
233 unsigned char ascq; /* ASCQ */
234 unsigned char rfu; /* FRU */
feb5680e 235 unsigned char sns_key_info[3]; /* sense key specific information */
1dac4186 236};
237
238/* sd_ctl bit map */
239/* SD push point control, bit 0, 1 */
240#define SD_PUSH_POINT_CTL_MASK 0x03
241#define SD_PUSH_POINT_DELAY 0x01
242#define SD_PUSH_POINT_AUTO 0x02
243/* SD sample point control, bit 2, 3 */
244#define SD_SAMPLE_POINT_CTL_MASK 0x0C
245#define SD_SAMPLE_POINT_DELAY 0x04
246#define SD_SAMPLE_POINT_AUTO 0x08
247/* SD DDR Tx phase set by user, bit 4 */
248#define SD_DDR_TX_PHASE_SET_BY_USER 0x10
249/* MMC DDR Tx phase set by user, bit 5 */
250#define MMC_DDR_TX_PHASE_SET_BY_USER 0x20
251/* Support MMC DDR mode, bit 6 */
252/*#define SUPPORT_MMC_DDR_MODE 0x40 */
253#define SUPPORT_UHS50_MMC44 0x40
254
255struct rts51x_option {
1dac4186 256 int mspro_formatter_enable;
257
258 /* card clock expected by user for fpga platform */
259 int fpga_sd_sdr104_clk;
260 int fpga_sd_ddr50_clk;
261 int fpga_sd_sdr50_clk;
262 int fpga_sd_hs_clk;
263 int fpga_mmc_52m_clk;
264 int fpga_ms_hg_clk;
265 int fpga_ms_4bit_clk;
266
267 /* card clock expected by user for asic platform */
268 int asic_sd_sdr104_clk;
269 int asic_sd_ddr50_clk;
270 int asic_sd_sdr50_clk;
271 int asic_sd_hs_clk;
272 int asic_mmc_52m_clk;
273 int asic_ms_hg_clk;
274 int asic_ms_4bit_clk;
275
276 u8 ssc_depth_sd_sdr104; /* sw */
277 u8 ssc_depth_sd_ddr50; /* sw */
278 u8 ssc_depth_sd_sdr50; /* sw */
279 u8 ssc_depth_sd_hs; /* sw */
280 u8 ssc_depth_mmc_52m; /* sw */
281 u8 ssc_depth_ms_hg; /* sw */
282 u8 ssc_depth_ms_4bit; /* sw */
283 u8 ssc_depth_low_speed; /* sw */
284
285 /* SD/MMC Tx phase */
286 int sd_ddr_tx_phase; /* Enabled by bit 4 of sd_ctl */
287 int mmc_ddr_tx_phase; /* Enabled by bit 5 of sd_ctl */
288
289 /* priority of choosing sd speed funciton */
290 u32 sd_speed_prior;
291
292 /* sd card control */
293 u32 sd_ctl;
294
295 /* Enable Selective Suspend */
296 int ss_en;
297 /* Interval to enter SS from IDLE state (second) */
298 int ss_delay;
1dac4186 299
300 /* Enable SSC clock */
301 int ssc_en;
302
303 int auto_delink_en;
304
305 /* sangdy2010-07-13:add FT2 fast mode */
306 int FT2_fast_mode;
307 /* sangdy2010-07-15:
308 * add for config delay between 1/4 PMOS and 3/4 PMOS */
309 int pwr_delay;
310
311 int xd_rw_step; /* add to tune xd tRP */
312 int D3318_off_delay; /* add to tune D3318 off delay time */
313 int delink_delay; /* add to tune delink delay time */
314 /* add for rts5129 to enable/disable D3318 off */
315 u8 rts5129_D3318_off_enable;
316 u8 sd20_pad_drive; /* add to config SD20 PAD drive */
317 u8 sd30_pad_drive; /* add to config SD30 pad drive */
318 /*if reset or rw fail,then set SD20 pad drive again */
319 u8 reset_or_rw_fail_set_pad_drive;
320
1dac4186 321 u8 debounce_num; /* debounce number */
1dac4186 322 u8 led_toggle_interval; /* used to control led toggle speed */
323 int xd_rwn_step;
324 u8 sd_send_status_en;
325 /* used to store default phase which is
326 * used when phase tune all pass. */
327 u8 ddr50_tx_phase;
328 u8 ddr50_rx_phase;
329 u8 sdr50_tx_phase;
330 u8 sdr50_rx_phase;
7086e6e5 331 /* used to enable select sdr50 tx phase according to proportion. */
1dac4186 332 u8 sdr50_phase_sel;
333 u8 ms_errreg_fix;
334 u8 reset_mmc_first;
335 u8 speed_mmc; /* when set, then try CMD55 only twice */
336 u8 led_always_on; /* if set, then led always on when card exist */
337 u8 dv18_voltage; /* add to tune dv18 voltage */
338};
339
340#define MS_FORMATTER_ENABLED(chip) ((chip)->option.mspro_formatter_enable)
341
342struct rts51x_chip;
343
344typedef int (*card_rw_func) (struct scsi_cmnd *srb, struct rts51x_chip *chip,
345 u32 sec_addr, u16 sec_cnt);
346
347/* For MS Card */
348#define MAX_DEFECTIVE_BLOCK 10
349
350struct zone_entry {
351 u16 *l2p_table;
352 u16 *free_table;
353 u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */
354 int set_index;
355 int get_index;
356 int unused_blk_cnt;
357 int disable_count;
358 /* To indicate whether the L2P table of this zone has been built. */
359 int build_flag;
360};
361
362struct xd_delay_write_tag {
363 u32 old_phyblock;
364 u32 new_phyblock;
365 u32 logblock;
366 u8 pageoff;
367 u8 delay_write_flag;
368};
369
370struct xd_info {
371 u8 maker_code;
372 u8 device_code;
373 u8 block_shift;
374 u8 page_off;
375 u8 addr_cycle;
376 u16 cis_block;
377 u8 multi_flag;
378 u8 err_code;
379 u32 capacity;
380
381 struct zone_entry *zone;
382 int zone_cnt;
383
384 struct xd_delay_write_tag delay_write;
385
386 int counter;
387
388 int xd_clock;
389};
390
391#define TYPE_SD 0x0000
392#define TYPE_MMC 0x0001
393
394/* TYPE_SD */
395#define SD_HS 0x0100
396#define SD_SDR50 0x0200
397#define SD_DDR50 0x0400
398#define SD_SDR104 0x0800
399#define SD_HCXC 0x1000
400
401/* TYPE_MMC */
402#define MMC_26M 0x0100
403#define MMC_52M 0x0200
404#define MMC_4BIT 0x0400
405#define MMC_8BIT 0x0800
406#define MMC_SECTOR_MODE 0x1000
407#define MMC_DDR52 0x2000
408
409/* SD card */
410#define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD)
411#define CHK_SD_HS(sd_card) \
412 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS))
413#define CHK_SD_SDR50(sd_card) \
414 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50))
415#define CHK_SD_DDR50(sd_card) \
416 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50))
417#define CHK_SD_SDR104(sd_card) \
418 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104))
419#define CHK_SD_HCXC(sd_card) \
420 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC))
421#define CHK_SD30_SPEED(sd_card) \
422 (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) ||\
423 CHK_SD_SDR104(sd_card))
424
425#define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD)
426#define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS)
427#define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50)
428#define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50)
429#define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104)
430#define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC)
431
432#define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS)
433#define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50)
434#define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50)
435#define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104)
436#define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC)
437#define CLR_SD30_SPEED(sd_card) \
438 ((sd_card)->sd_type &= ~(SD_SDR50|SD_DDR50|SD_SDR104))
439
440/* MMC card */
441#define CHK_MMC(sd_card) \
442 (((sd_card)->sd_type & 0xFF) == TYPE_MMC)
443#define CHK_MMC_26M(sd_card) \
444 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M))
445#define CHK_MMC_52M(sd_card) \
446 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M))
447#define CHK_MMC_4BIT(sd_card) \
448 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT))
449#define CHK_MMC_8BIT(sd_card) \
450 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT))
451#define CHK_MMC_SECTOR_MODE(sd_card)\
452 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE))
453#define CHK_MMC_DDR52(sd_card) \
454 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52))
455
456#define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC)
457#define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M)
458#define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M)
459#define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT)
460#define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT)
461#define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE)
462#define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52)
463
464#define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M)
465#define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M)
466#define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT)
467#define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT)
468#define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
469#define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52)
470
471#define CHK_MMC_HS(sd_card) \
472 (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card))
473#define CLR_MMC_HS(sd_card) \
474do { \
475 CLR_MMC_DDR52(sd_card); \
476 CLR_MMC_52M(sd_card); \
477 CLR_MMC_26M(sd_card); \
478} while (0)
479
480#define SD_SUPPORT_CLASS_TEN 0x01
481#define SD_SUPPORT_1V8 0x02
482
483#define SD_SET_CLASS_TEN(sd_card) \
484 ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN)
485#define SD_CHK_CLASS_TEN(sd_card) \
486 ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN)
487#define SD_CLR_CLASS_TEN(sd_card) \
488 ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN)
489#define SD_SET_1V8(sd_card) \
490 ((sd_card)->sd_setting |= SD_SUPPORT_1V8)
491#define SD_CHK_1V8(sd_card) \
492 ((sd_card)->sd_setting & SD_SUPPORT_1V8)
493#define SD_CLR_1V8(sd_card) \
494 ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8)
495#define CLR_RETRY_SD20_MODE(sd_card) \
496 ((sd_card)->retry_SD20_mode = 0)
497#define SET_RETRY_SD20_MODE(sd_card) \
498 ((sd_card)->retry_SD20_mode = 1)
499#define CHK_RETRY_SD20_MODE(sd_card) \
500 ((sd_card)->retry_SD20_mode == 1)
501
502struct sd_info {
503 u16 sd_type;
504 u8 err_code;
505 u8 sd_data_buf_ready;
506 u32 sd_addr;
507 u32 capacity;
508
509 u8 raw_csd[16];
510 u8 raw_scr[8];
511
512 /* Sequential RW */
513 int seq_mode;
514 enum dma_data_direction pre_dir;
515 u32 pre_sec_addr;
516 u16 pre_sec_cnt;
517
518 int counter;
519
520 int sd_clock;
521
522#ifdef SUPPORT_CPRM
523 int sd_pass_thru_en;
524 int pre_cmd_err;
525 u8 last_rsp_type;
526 u8 rsp[17];
527#endif
528
529 u8 func_group1_mask;
530 u8 func_group2_mask;
531 u8 func_group3_mask;
532 u8 func_group4_mask;
533
534 u8 sd_switch_fail;
535 u8 sd_read_phase;
536 u8 retry_SD20_mode; /* sangdy2010-06-10 */
537 u8 sd_reset_fail; /* sangdy2010-07-01 */
538 u8 sd_send_status_en;
539
1dac4186 540};
541
542#define MODE_512_SEQ 0x01
543#define MODE_2K_SEQ 0x02
544
545#define TYPE_MS 0x0000
546#define TYPE_MSPRO 0x0001
547
548#define MS_4BIT 0x0100
549#define MS_8BIT 0x0200
550#define MS_HG 0x0400
551#define MS_XC 0x0800
552
553#define HG8BIT (MS_HG | MS_8BIT)
554
555#define CHK_MSPRO(ms_card) \
556 (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
557#define CHK_HG8BIT(ms_card) \
558 (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT))
559#define CHK_MSXC(ms_card) \
560 (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC))
561#define CHK_MSHG(ms_card) \
562 (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG))
563
564#define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT))
565#define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT))
566
567struct ms_delay_write_tag {
568 u16 old_phyblock;
569 u16 new_phyblock;
570 u16 logblock;
571 u8 pageoff;
572 u8 delay_write_flag;
573};
574
575struct ms_info {
576 u16 ms_type;
577 u8 block_shift;
578 u8 page_off;
579 u16 total_block;
580 u16 boot_block;
581 u32 capacity;
582
583 u8 check_ms_flow;
584 u8 switch_8bit_fail;
585 u8 err_code;
586
587 struct zone_entry *segment;
588 int segment_cnt;
589
590 int pro_under_formatting;
591 int format_status;
592 u16 progress;
593 u8 raw_sys_info[96];
594#ifdef SUPPORT_PCGL_1P18
595 u8 raw_model_name[48];
596#endif
597
598 u8 multi_flag;
599
600 /* Sequential RW */
601 u8 seq_mode;
602 enum dma_data_direction pre_dir;
603 u32 pre_sec_addr;
604 u16 pre_sec_cnt;
605 u32 total_sec_cnt;
606 u8 last_rw_int;
607
608 struct ms_delay_write_tag delay_write;
609
610 int counter;
611
612 int ms_clock;
613
614#ifdef SUPPORT_MAGIC_GATE
615 u8 magic_gate_id[16];
616 u8 mg_entry_num;
617 int mg_auth; /* flag to indicate authentication process */
618#endif
619};
620
621#define PRO_UNDER_FORMATTING(ms_card) \
622 ((ms_card)->pro_under_formatting)
623#define SET_FORMAT_STATUS(ms_card, status) \
624 ((ms_card)->format_status = (status))
625#define CHK_FORMAT_STATUS(ms_card, status) \
626 ((ms_card)->format_status == (status))
627
628struct scsi_cmnd;
629
630enum CHIP_STAT { STAT_INIT, STAT_IDLE, STAT_RUN, STAT_SS_PRE, STAT_SS,
631 STAT_SUSPEND };
632
633struct rts51x_chip {
634 u16 vendor_id;
635 u16 product_id;
636 char max_lun;
637
638 struct scsi_cmnd *srb;
639 struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT];
640
1dac4186 641 int led_toggle_counter;
3d2b3aac 642
1dac4186 643 int ss_counter;
644 int idle_counter;
645 int auto_delink_counter;
646 enum CHIP_STAT chip_stat;
647
648 int resume_from_scsi;
649
650 /* Card information */
651 struct xd_info xd_card;
652 struct sd_info sd_card;
653 struct ms_info ms_card;
654
655 int cur_clk; /* current card clock */
656 int cur_card; /* Current card module */
657
658 u8 card_exist; /* card exist bit map (physical exist) */
659 u8 card_ready; /* card ready bit map (reset successfully) */
660 u8 card_fail; /* card reset fail bit map */
661 u8 card_ejected; /* card ejected bit map */
662 u8 card_wp; /* card write protected bit map */
663
664 u8 fake_card_ready;
665 /* flag to indicate whether to answer MediaChange */
666 unsigned long lun_mc;
667
668 /* card bus width */
669 u8 card_bus_width[MAX_ALLOWED_LUN_CNT];
670 /* card capacity */
671 u32 capacity[MAX_ALLOWED_LUN_CNT];
672
673 /* read/write card function pointer */
674 card_rw_func rw_card[MAX_ALLOWED_LUN_CNT];
675 /* read/write capacity, used for GPIO Toggle */
676 u32 rw_cap[MAX_ALLOWED_LUN_CNT];
677 /* card to lun mapping table */
678 u8 card2lun[32];
679 /* lun to card mapping table */
680 u8 lun2card[MAX_ALLOWED_LUN_CNT];
681
682#ifdef _MSG_TRACE
683 struct trace_msg_t trace_msg[TRACE_ITEM_CNT];
684 int msg_idx;
685#endif
686
687 int rw_need_retry;
688
689 /* ASIC or FPGA */
690 int asic_code;
691
692 /* QFN24 or LQFP48 */
693 int package;
694
695 /* Full Speed or High Speed */
696 int usb_speed;
697
698 /*sangdy:enable or disable UHS50 and MMC4.4 */
699 int uhs50_mmc44_en;
700
701 u8 ic_version;
702
703 /* Command buffer */
704 u8 *cmd_buf;
705 unsigned int cmd_idx;
706 /* Response buffer */
707 u8 *rsp_buf;
708
709 u16 card_status;
710
711#ifdef SUPPORT_OCP
712 u16 ocp_stat;
713#endif
714
715 struct rts51x_option option;
716 struct rts51x_usb *usb;
717
718 u8 rcc_read_response;
719 int reset_need_retry;
720 u8 rts5179;
721};
722
723#define UHS50_EN 0x0001
724#define UHS50_DIS 0x0000
725#define SET_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_EN)
726#define CLEAR_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_DIS)
727#define CHECK_UHS50(chip) (((chip)->uhs50_mmc44_en&0xff) == UHS50_EN)
728
729#define RTS51X_GET_VID(chip) ((chip)->vendor_id)
730#define RTS51X_GET_PID(chip) ((chip)->product_id)
731
732#define RTS51X_SET_STAT(chip, stat) \
733do { \
734 if ((stat) != STAT_IDLE) { \
735 (chip)->idle_counter = 0; \
736 } \
737 (chip)->chip_stat = (enum CHIP_STAT)(stat); \
738} while (0)
739#define RTS51X_CHK_STAT(chip, stat) ((chip)->chip_stat == (stat))
740#define RTS51X_GET_STAT(chip) ((chip)->chip_stat)
741
742#define CHECK_PID(chip, pid) (RTS51X_GET_PID(chip) == (pid))
743#define CHECK_PKG(chip, pkg) ((chip)->package == (pkg))
744#define CHECK_USB(chip, speed) ((chip)->usb_speed == (speed))
745
746int rts51x_reset_chip(struct rts51x_chip *chip);
747int rts51x_init_chip(struct rts51x_chip *chip);
748int rts51x_release_chip(struct rts51x_chip *chip);
749void rts51x_polling_func(struct rts51x_chip *chip);
750
751static inline void rts51x_init_cmd(struct rts51x_chip *chip)
752{
753 chip->cmd_idx = 0;
754 chip->cmd_buf[0] = 'R';
755 chip->cmd_buf[1] = 'T';
756 chip->cmd_buf[2] = 'C';
757 chip->cmd_buf[3] = 'R';
758 chip->cmd_buf[PACKET_TYPE] = BATCH_CMD;
759}
760
761void rts51x_add_cmd(struct rts51x_chip *chip,
762 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
763int rts51x_send_cmd(struct rts51x_chip *chip, u8 flag, int timeout);
764int rts51x_get_rsp(struct rts51x_chip *chip, int rsp_len, int timeout);
765
766static inline void rts51x_read_rsp_buf(struct rts51x_chip *chip, int offset,
767 u8 *buf, int buf_len)
768{
769 memcpy(buf, chip->rsp_buf + offset, buf_len);
770}
771
772static inline u8 *rts51x_get_rsp_data(struct rts51x_chip *chip)
773{
774 return chip->rsp_buf;
775}
776
aa2f92ae 777int rts51x_get_card_status(struct rts51x_chip *chip, u16 *status);
1dac4186 778int rts51x_write_register(struct rts51x_chip *chip, u16 addr, u8 mask, u8 data);
aa2f92ae 779int rts51x_read_register(struct rts51x_chip *chip, u16 addr, u8 *data);
1dac4186 780int rts51x_ep0_write_register(struct rts51x_chip *chip, u16 addr, u8 mask,
781 u8 data);
aa2f92ae 782int rts51x_ep0_read_register(struct rts51x_chip *chip, u16 addr, u8 *data);
1dac4186 783int rts51x_seq_write_register(struct rts51x_chip *chip, u16 addr, u16 len,
784 u8 *data);
785int rts51x_seq_read_register(struct rts51x_chip *chip, u16 addr, u16 len,
786 u8 *data);
787int rts51x_read_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len);
788int rts51x_write_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len);
789int rts51x_write_phy_register(struct rts51x_chip *chip, u8 addr, u8 val);
790int rts51x_read_phy_register(struct rts51x_chip *chip, u8 addr, u8 *val);
791void rts51x_do_before_power_down(struct rts51x_chip *chip);
792void rts51x_clear_hw_error(struct rts51x_chip *chip);
793void rts51x_prepare_run(struct rts51x_chip *chip);
794void rts51x_trace_msg(struct rts51x_chip *chip, unsigned char *buf, int clear);
795void rts51x_pp_status(struct rts51x_chip *chip, unsigned int lun, u8 *status,
796 u8 status_len);
797void rts51x_read_status(struct rts51x_chip *chip, unsigned int lun,
798 u8 *rts51x_status, u8 status_len);
799int rts51x_transfer_data_rcc(struct rts51x_chip *chip, unsigned int pipe,
800 void *buf, unsigned int len, int use_sg,
801 unsigned int *act_len, int timeout, u8 stage_flag);
802
803#define RTS51X_WRITE_REG(chip, addr, mask, data) \
804do { \
805 int _retval = rts51x_write_register((chip), \
806 (addr), (mask), (data)); \
807 if (_retval != STATUS_SUCCESS) { \
808 TRACE_RET((chip), _retval); \
809 } \
810} while (0)
811
812#define RTS51X_READ_REG(chip, addr, data) \
813do { \
814 int _retval = rts51x_read_register((chip), \
815 (addr), (data)); \
816 if (_retval != STATUS_SUCCESS) { \
817 TRACE_RET((chip), _retval); \
818 } \
819} while (0)
820
821#endif /* __RTS51X_CHIP_H */
kernel source for telekom puls (alcatel/mediatek)