[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rtl8192u / r8190_rtl8256.c

/*
  This is part of the rtl8192 driver
  released under the GPL (See file COPYING for details).

  This files contains programming code for the rtl8256
  radio frontend.

  *Many* thanks to Realtek Corp. for their great support!

*/

#include "r8192U.h"
#include "r8192U_hw.h"
#include "r819xU_phyreg.h"
#include "r819xU_phy.h"
#include "r8190_rtl8256.h"

/*--------------------------------------------------------------------------
 * Overview:   	set RF band width (20M or 40M)
 * Input:       struct net_device*	dev
 * 		WIRELESS_BANDWIDTH_E	Bandwidth	//20M or 40M
 * Output:      NONE
 * Return:      NONE
 * Note:	8226 support both 20M  and 40 MHz
 *---------------------------------------------------------------------------*/
void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)	//20M or 40M
{
	u8	eRFPath;
	struct r8192_priv *priv = ieee80211_priv(dev);

	//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
	for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
	{
		if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
				continue;

		switch(Bandwidth)
		{
			case HT_CHANNEL_WIDTH_20:
				if(priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
				{
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);

					//cosa add for sd3's request 01/23/2008
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
				}
				else
				{
					RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
				}

				break;
			case HT_CHANNEL_WIDTH_20_40:
				if(priv->card_8192_version == VERSION_819xU_A ||priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
				{
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);

					//cosa add for sd3's request 01/23/2008
					if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes
						rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
					else
						rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
				}
				else
				{
					RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
				}


				break;
			default:
				RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
				break;

		}
	}
	return;
}
/*--------------------------------------------------------------------------
 * Overview:    Interface to config 8256
 * Input:       struct net_device*	dev
 * Output:      NONE
 * Return:      NONE
 *---------------------------------------------------------------------------*/
void PHY_RF8256_Config(struct net_device* dev)
{
	struct r8192_priv *priv = ieee80211_priv(dev);
	// Initialize general global value
	//
	// TODO: Extend RF_PATH_C and RF_PATH_D in the future
	priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
	// Config BB and RF
	phy_RF8256_Config_ParaFile(dev);

	return;
}
/*--------------------------------------------------------------------------
 * Overview:    Interface to config 8256
 * Input:       struct net_device*	dev
 * Output:      NONE
 * Return:      NONE
 *---------------------------------------------------------------------------*/
void phy_RF8256_Config_ParaFile(struct net_device* dev)
{
	u32 	u4RegValue = 0;
	//static s1Byte				szRadioAFile[] = RTL819X_PHY_RADIO_A;
	//static s1Byte				szRadioBFile[] = RTL819X_PHY_RADIO_B;
	//static s1Byte				szRadioCFile[] = RTL819X_PHY_RADIO_C;
	//static s1Byte				szRadioDFile[] = RTL819X_PHY_RADIO_D;
	u8 	eRFPath;
	BB_REGISTER_DEFINITION_T	*pPhyReg;
	struct r8192_priv *priv = ieee80211_priv(dev);
	u32	RegOffSetToBeCheck = 0x3;
	u32 	RegValueToBeCheck = 0x7f1;
	u32	RF3_Final_Value = 0;
	u8	ConstRetryTimes = 5, RetryTimes = 5;
	u8 ret = 0;
	//3//-----------------------------------------------------------------
	//3// <2> Initialize RF
	//3//-----------------------------------------------------------------
	for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
	{
		if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
				continue;

		pPhyReg = &priv->PHYRegDef[eRFPath];

		// Joseph test for shorten RF config
	//	pHalData->RfReg0Value[eRFPath] =  rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);

		/*----Store original RFENV control type----*/
		switch(eRFPath)
		{
		case RF90_PATH_A:
		case RF90_PATH_C:
			u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
			break;
		case RF90_PATH_B :
		case RF90_PATH_D:
			u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
			break;
		}

		/*----Set RF_ENV enable----*/
		rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);

		/*----Set RF_ENV output high----*/
		rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);

		/* Set bit number of Address and Data for RF register */
		rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); 	// Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
		rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	// Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???

		rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);

		/*----Check RF block (for FPGA platform only)----*/
		// TODO: this function should be removed on ASIC , Emily 2007.2.2
		if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath))
		{
			RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
			goto phy_RF8256_Config_ParaFile_Fail;
		}

		RetryTimes = ConstRetryTimes;
		RF3_Final_Value = 0;
		/*----Initialize RF fom connfiguration file----*/
		switch(eRFPath)
		{
		case RF90_PATH_A:
			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
			{
				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
				RetryTimes--;
			}
			break;
		case RF90_PATH_B:
			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
			{
				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
				RetryTimes--;
			}
			break;
		case RF90_PATH_C:
			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
			{
				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
				RetryTimes--;
			}
			break;
		case RF90_PATH_D:
			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
			{
				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
				RetryTimes--;
			}
			break;
		}

		/*----Restore RFENV control type----*/;
		switch(eRFPath)
		{
		case RF90_PATH_A:
		case RF90_PATH_C:
			rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
			break;
		case RF90_PATH_B :
		case RF90_PATH_D:
			rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
			break;
		}

		if(ret){
			RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
			goto phy_RF8256_Config_ParaFile_Fail;
		}

	}

	RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
	return ;

phy_RF8256_Config_ParaFile_Fail:
	RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
	return ;
}


void PHY_SetRF8256CCKTxPower(struct net_device*	dev, u8	powerlevel)
{
	u32	TxAGC=0;
	struct r8192_priv *priv = ieee80211_priv(dev);
	//modified by vivi, 20080109
	TxAGC = powerlevel;

	if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan
	{
		if(priv->CustomerID == RT_CID_819x_Netcore)
			TxAGC = 0x22;
		else
		TxAGC += priv->CckPwEnl;
	}

	if(TxAGC > 0x24)
		TxAGC = 0x24;
	rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
}


void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
{
	struct r8192_priv *priv = ieee80211_priv(dev);
	//Joseph TxPower for 8192 testing
	u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
	u8 index = 0;
	u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
	u8 byte0, byte1, byte2, byte3;

	powerBase0 = powerlevel + priv->TxPowerDiff;	//OFDM rates
	powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
	powerBase1 = powerlevel;							//MCS rates
	powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;

	for(index=0; index<6; index++)
	{
		writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
		byte0 = (u8)(writeVal & 0x7f);
		byte1 = (u8)((writeVal & 0x7f00)>>8);
		byte2 = (u8)((writeVal & 0x7f0000)>>16);
		byte3 = (u8)((writeVal & 0x7f000000)>>24);
		if(byte0 > 0x24)	// Max power index = 0x24
			byte0 = 0x24;
		if(byte1 > 0x24)
			byte1 = 0x24;
		if(byte2 > 0x24)
			byte2 = 0x24;
		if(byte3 > 0x24)
			byte3 = 0x24;

		//for tx power track
		if(index == 3)
		{
			writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
			priv->Pwr_Track = writeVal_tmp;
		}

		if(priv->bDynamicTxHighPower == TRUE)     //Add by Jacken 2008/03/06
		{
			// Emily, 20080613. Set low tx power for both MCS and legacy OFDM
			writeVal = 0x03030303;
		}
		else
		{
			writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
		}
		rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
	}
	return;

}
Commit	Line	Data
8fc8598e JC	1	/*
	2	This is part of the rtl8192 driver
	3	released under the GPL (See file COPYING for details).
	4
	5	This files contains programming code for the rtl8256
	6	radio frontend.
	7
	8	Many thanks to Realtek Corp. for their great support!
	9
	10	*/
	11
	12	#include "r8192U.h"
	13	#include "r8192U_hw.h"
	14	#include "r819xU_phyreg.h"
	15	#include "r819xU_phy.h"
	16	#include "r8190_rtl8256.h"
	17
	18	/*--------------------------------------------------------------------------
	19	* Overview: set RF band width (20M or 40M)
	20	* Input: struct net_device* dev
	21	* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
	22	* Output: NONE
	23	* Return: NONE
	24	* Note: 8226 support both 20M and 40 MHz
	25	---------------------------------------------------------------------------/
	26	void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
	27	{
	28	u8 eRFPath;
	29	struct r8192_priv *priv = ieee80211_priv(dev);
	30
	31	//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
	32	for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
	33	{
	34	if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
	35	continue;
	36
	37	switch(Bandwidth)
	38	{
	39	case HT_CHANNEL_WIDTH_20:
	40	if(priv->card_8192_version == VERSION_819xU_A \|\| priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
	41	{
	42	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
	43	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
	44	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
	45
	46	//cosa add for sd3's request 01/23/2008
	47	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
	48	}
	49	else
	50	{
	51	RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
	52	}
	53
	54	break;
	55	case HT_CHANNEL_WIDTH_20_40:
	56	if(priv->card_8192_version == VERSION_819xU_A \|\|priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
	57	{
	58	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
	59	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
	60	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
	61
	62	//cosa add for sd3's request 01/23/2008
	63	if(priv->chan == 3 \|\| priv->chan == 9) //I need to set priv->chan whenever current channel changes
	64	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
65	else
66	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
67	}
68	else
69	{
70	RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
71	}
72
73
74	break;
75	default:
76	RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
77	break;
78
79	}
80	}
81	return;
82	}
83	/*--------------------------------------------------------------------------
84	* Overview: Interface to config 8256
85	* Input: struct net_device* dev
86	* Output: NONE
87	* Return: NONE
88	---------------------------------------------------------------------------/
89	void PHY_RF8256_Config(struct net_device* dev)
90	{
91	struct r8192_priv *priv = ieee80211_priv(dev);
92	// Initialize general global value
93	//
94	// TODO: Extend RF_PATH_C and RF_PATH_D in the future
95	priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
96	// Config BB and RF
97	phy_RF8256_Config_ParaFile(dev);
98
99	return;
100	}
101	/*--------------------------------------------------------------------------
102	* Overview: Interface to config 8256
103	* Input: struct net_device* dev
104	* Output: NONE
105	* Return: NONE
106	---------------------------------------------------------------------------/
107	void phy_RF8256_Config_ParaFile(struct net_device* dev)
108	{
109	u32 u4RegValue = 0;
110	//static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
111	//static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
112	//static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C;
113	//static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D;
114	u8 eRFPath;
115	BB_REGISTER_DEFINITION_T *pPhyReg;
116	struct r8192_priv *priv = ieee80211_priv(dev);
117	u32 RegOffSetToBeCheck = 0x3;
118	u32 RegValueToBeCheck = 0x7f1;
119	u32 RF3_Final_Value = 0;
120	u8 ConstRetryTimes = 5, RetryTimes = 5;
121	u8 ret = 0;
122	//3//-----------------------------------------------------------------
123	//3// <2> Initialize RF
124	//3//-----------------------------------------------------------------
125	for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
126	{
127	if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
128	continue;
129
130	pPhyReg = &priv->PHYRegDef[eRFPath];
131
132	// Joseph test for shorten RF config
133	// pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
134
135	/----Store original RFENV control type----/
136	switch(eRFPath)
137	{
138	case RF90_PATH_A:
139	case RF90_PATH_C:
140	u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
141	break;
142	case RF90_PATH_B :
143	case RF90_PATH_D:
144	u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
145	break;
146	}
147
148	/----Set RF_ENV enable----/
149	rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
150
151	/----Set RF_ENV output high----/
152	rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
153
154	/* Set bit number of Address and Data for RF register */
155	rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
156	rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
157
158	rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
159
160	/----Check RF block (for FPGA platform only)----/
161	// TODO: this function should be removed on ASIC , Emily 2007.2.2
162	if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath))
163	{
164	RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
165	goto phy_RF8256_Config_ParaFile_Fail;
166	}
167
168	RetryTimes = ConstRetryTimes;
169	RF3_Final_Value = 0;
170	/----Initialize RF fom connfiguration file----/
171	switch(eRFPath)
172	{
173	case RF90_PATH_A:
174	while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
175	{
176	ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
177	RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
178	RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
179	RetryTimes--;
180	}
181	break;
182	case RF90_PATH_B:
183	while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
184	{
185	ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
186	RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
187	RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
188	RetryTimes--;
189	}
190	break;
191	case RF90_PATH_C:
192	while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
193	{
194	ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
195	RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
196	RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
197	RetryTimes--;
198	}
199	break;
200	case RF90_PATH_D:
201	while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
202	{
203	ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
204	RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
205	RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
206	RetryTimes--;
207	}
208	break;
209	}
210
211	/----Restore RFENV control type----/;
212	switch(eRFPath)
213	{
214	case RF90_PATH_A:
215	case RF90_PATH_C:
216	rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
217	break;
218	case RF90_PATH_B :
219	case RF90_PATH_D:
220	rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
221	break;
222	}
223
224	if(ret){
225	RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
226	goto phy_RF8256_Config_ParaFile_Fail;
227	}
228
229	}
230
231	RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
232	return ;
233
234	phy_RF8256_Config_ParaFile_Fail:
235	RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
236	return ;
237	}
238
239
240	void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
241	{
242	u32 TxAGC=0;
243	struct r8192_priv *priv = ieee80211_priv(dev);
244	//modified by vivi, 20080109
245	TxAGC = powerlevel;
246
247	if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan
248	{
249	if(priv->CustomerID == RT_CID_819x_Netcore)
250	TxAGC = 0x22;
251	else
252	TxAGC += priv->CckPwEnl;
253	}
254
255	if(TxAGC > 0x24)
256	TxAGC = 0x24;
257	rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
258	}
259
260
261	void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
262	{
263	struct r8192_priv *priv = ieee80211_priv(dev);
264	//Joseph TxPower for 8192 testing
265	u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
266	u8 index = 0;
267	u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
268	u8 byte0, byte1, byte2, byte3;
269
270	powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates
271	powerBase0 = (powerBase0<<24) \| (powerBase0<<16) \|(powerBase0<<8) \|powerBase0;
272	powerBase1 = powerlevel; //MCS rates
273	powerBase1 = (powerBase1<<24) \| (powerBase1<<16) \|(powerBase1<<8) \|powerBase1;
274
275	for(index=0; index<6; index++)
276	{
277	writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
278	byte0 = (u8)(writeVal & 0x7f);
279	byte1 = (u8)((writeVal & 0x7f00)>>8);
280	byte2 = (u8)((writeVal & 0x7f0000)>>16);
281	byte3 = (u8)((writeVal & 0x7f000000)>>24);
282	if(byte0 > 0x24) // Max power index = 0x24
283	byte0 = 0x24;
284	if(byte1 > 0x24)
285	byte1 = 0x24;
286	if(byte2 > 0x24)
287	byte2 = 0x24;
288	if(byte3 > 0x24)
289	byte3 = 0x24;
290
291	//for tx power track
292	if(index == 3)
293	{
294	writeVal_tmp = (byte3<<24) \| (byte2<<16) \|(byte1<<8) \|byte0;
295	priv->Pwr_Track = writeVal_tmp;
296	}
297
298	if(priv->bDynamicTxHighPower == TRUE) //Add by Jacken 2008/03/06
299	{
300	// Emily, 20080613. Set low tx power for both MCS and legacy OFDM
301	writeVal = 0x03030303;
302	}
303	else
304	{
305	writeVal = (byte3<<24) \| (byte2<<16) \|(byte1<<8) \|byte0;
306	}
307	rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
308	}
309	return;
310
311	}
312