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1 | /****************************************************************************** |
2 | * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. | |
5f53d8ca | 3 | * |
653e99e3 FS |
4 | * This program is distributed in the hope that it will be useful, but WITHOUT |
5 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
6 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
7 | * more details. | |
5f53d8ca | 8 | * |
653e99e3 FS |
9 | * You should have received a copy of the GNU General Public License along with |
10 | * this program; if not, write to the Free Software Foundation, Inc., | |
11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
5f53d8ca | 12 | * |
653e99e3 FS |
13 | * The full GNU General Public License is included in this distribution in the |
14 | * file called LICENSE. | |
5f53d8ca | 15 | * |
653e99e3 FS |
16 | * Contact Information: |
17 | * wlanfae <wlanfae@realtek.com> | |
18 | ******************************************************************************/ | |
19 | ||
5f53d8ca JC |
20 | #ifndef R8192S_HW |
21 | #define R8192S_HW | |
22 | ||
23 | typedef enum _VERSION_8192S{ | |
24 | VERSION_8192S_ACUT, | |
25 | VERSION_8192S_BCUT, | |
26 | VERSION_8192S_CCUT | |
27 | }VERSION_8192S,*PVERSION_8192S; | |
28 | ||
5f53d8ca JC |
29 | typedef enum _VERSION_8192SUsb{ |
30 | VERSION_8192SU_A, //A-Cut | |
31 | VERSION_8192SU_B, //B-Cut | |
32 | VERSION_8192SU_C, //C-Cut | |
33 | }VERSION_8192SUsb, *PVERSION_8192SUsb; | |
c6813185 FS |
34 | |
35 | ||
36 | /* RF type. */ | |
5f53d8ca JC |
37 | typedef enum _RT_RF_TYPE_DEFINITION |
38 | { | |
39 | RF_1T2R = 0, | |
40 | RF_2T4R, | |
41 | RF_2T2R, | |
5f53d8ca JC |
42 | RF_1T1R, |
43 | RF_2T2R_GREEN, | |
5f53d8ca JC |
44 | RF_819X_MAX_TYPE |
45 | }RT_RF_TYPE_DEF_E; | |
46 | ||
47 | typedef enum _BaseBand_Config_Type{ | |
48 | BaseBand_Config_PHY_REG = 0, //Radio Path A | |
49 | BaseBand_Config_AGC_TAB = 1, //Radio Path B | |
50 | }BaseBand_Config_Type, *PBaseBand_Config_Type; | |
51 | ||
5f53d8ca JC |
52 | #define RTL8187_REQT_READ 0xc0 |
53 | #define RTL8187_REQT_WRITE 0x40 | |
54 | #define RTL8187_REQ_GET_REGS 0x05 | |
55 | #define RTL8187_REQ_SET_REGS 0x05 | |
56 | ||
57 | #define MAX_TX_URB 5 | |
653e99e3 | 58 | #define MAX_RX_URB 8 |
5f53d8ca JC |
59 | |
60 | #define R8180_MAX_RETRY 255 | |
653e99e3 | 61 | #define RX_URB_SIZE 0x4000 |
5f53d8ca JC |
62 | |
63 | #define BB_ANTATTEN_CHAN14 0x0c | |
64 | #define BB_ANTENNA_B 0x40 | |
65 | ||
66 | #define BB_HOST_BANG (1<<30) | |
67 | #define BB_HOST_BANG_EN (1<<2) | |
68 | #define BB_HOST_BANG_CLK (1<<1) | |
69 | #define BB_HOST_BANG_RW (1<<3) | |
70 | #define BB_HOST_BANG_DATA 1 | |
71 | ||
72 | ||
73 | //============================================================ | |
74 | // 8192S Regsiter bit | |
75 | //============================================================ | |
76 | #define BB_GLOBAL_RESET_BIT 0x1 | |
77 | ||
78 | #define CR_RST 0x10 | |
79 | #define CR_RE 0x08 | |
80 | #define CR_TE 0x04 | |
81 | #define CR_MulRW 0x01 | |
82 | ||
83 | #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ | |
84 | (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) | |
85 | ||
86 | #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) | |
87 | #define RX_FIFO_THRESHOLD_SHIFT 13 | |
88 | #define RX_FIFO_THRESHOLD_128 3 | |
89 | #define RX_FIFO_THRESHOLD_256 4 | |
90 | #define RX_FIFO_THRESHOLD_512 5 | |
91 | #define RX_FIFO_THRESHOLD_1024 6 | |
92 | #define RX_FIFO_THRESHOLD_NONE 7 | |
93 | ||
94 | #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) | |
95 | ||
96 | //---------------------------------------------------------------------------- | |
97 | // 8190 CPU General Register (offset 0x100, 4 byte) | |
98 | //---------------------------------------------------------------------------- | |
99 | #define CPU_CCK_LOOPBACK 0x00030000 | |
100 | #define CPU_GEN_SYSTEM_RESET 0x00000001 | |
101 | #define CPU_GEN_FIRMWARE_RESET 0x00000008 | |
102 | #define CPU_GEN_BOOT_RDY 0x00000010 | |
103 | #define CPU_GEN_FIRM_RDY 0x00000020 | |
104 | #define CPU_GEN_PUT_CODE_OK 0x00000080 | |
105 | #define CPU_GEN_BB_RST 0x00000100 | |
106 | #define CPU_GEN_PWR_STB_CPU 0x00000004 | |
107 | #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 | |
108 | #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 | |
109 | //---------------------------------------------------------------------------- | |
110 | //// | |
111 | //// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) | |
112 | ////---------------------------------------------------------------------------- | |
113 | #define MSR_LINK_MASK ((1<<0)|(1<<1)) | |
114 | #define MSR_LINK_MANAGED 2 | |
115 | #define MSR_LINK_NONE 0 | |
116 | #define MSR_LINK_SHIFT 0 | |
117 | #define MSR_LINK_ADHOC 1 | |
118 | #define MSR_LINK_MASTER 3 | |
119 | #define MSR_LINK_ENEDCA (1<<4) | |
120 | ||
121 | ||
5f53d8ca JC |
122 | #define EPROM_CMD_RESERVED_MASK (1<<5) |
123 | #define EPROM_CMD_OPERATING_MODE_SHIFT 6 | |
124 | #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) | |
125 | #define EPROM_CMD_CONFIG 0x3 | |
126 | #define EPROM_CMD_NORMAL 0 | |
127 | #define EPROM_CMD_LOAD 1 | |
128 | #define EPROM_CMD_PROGRAM 2 | |
129 | #define EPROM_CS_SHIFT 3 | |
130 | #define EPROM_CK_SHIFT 2 | |
131 | #define EPROM_W_SHIFT 1 | |
132 | #define EPROM_R_SHIFT 0 | |
133 | ||
5f53d8ca JC |
134 | //============================================================ |
135 | // 8192S Regsiter offset definition | |
136 | //============================================================ | |
137 | ||
138 | // | |
139 | // MAC register 0x0 - 0x5xx | |
140 | // 1. System configuration registers. | |
141 | // 2. Command Control Registers | |
142 | // 3. MACID Setting Registers | |
143 | // 4. Timing Control Registers | |
144 | // 5. FIFO Control Registers | |
145 | // 6. Adaptive Control Registers | |
146 | // 7. EDCA Setting Registers | |
147 | // 8. WMAC, BA and CCX related Register. | |
148 | // 9. Security Control Registers | |
149 | // 10. Power Save Control Registers | |
150 | // 11. General Purpose Registers | |
151 | // 12. Host Interrupt Status Registers | |
152 | // 13. Test Mode and Debug Control Registers | |
153 | // 14. PCIE config register | |
154 | // | |
155 | ||
156 | ||
157 | // | |
158 | // 1. System Configuration Registers (Offset: 0x0000 - 0x003F) | |
159 | // | |
160 | #define SYS_ISO_CTRL 0x0000 // System Isolation Interface Control. | |
161 | #define SYS_FUNC_EN 0x0002 // System Function Enable. | |
162 | #define PMC_FSM 0x0004 // Power Sequence Control. | |
163 | #define SYS_CLKR 0x0008 // System Clock. | |
164 | #define EPROM_CMD 0x000A // 93C46/93C56 Command Register. (win CR93C46) | |
165 | #define EE_VPD 0x000C // EEPROM VPD Data. | |
166 | #define AFE_MISC 0x0010 // AFE Misc. | |
167 | #define SPS0_CTRL 0x0011 // Switching Power Supply 0 Control. | |
168 | #define SPS1_CTRL 0x0018 // Switching Power Supply 1 Control. | |
169 | #define RF_CTRL 0x001F // RF Block Control. | |
170 | #define LDOA15_CTRL 0x0020 // V15 Digital LDO Control. | |
171 | #define LDOV12D_CTRL 0x0021 // V12 Digital LDO Control. | |
172 | #define LDOHCI12_CTRL 0x0022 // V12 Digital LDO Control. | |
173 | #define LDO_USB_SDIO 0x0023 // LDO USB Control. | |
174 | #define LPLDO_CTRL 0x0024 // Low Power LDO Control. | |
175 | #define AFE_XTAL_CTRL 0x0026 // AFE Crystal Control. | |
176 | #define AFE_PLL_CTRL 0x0028 // System Function Enable. | |
177 | #define EFUSE_CTRL 0x0030 // E-Fuse Control. | |
178 | #define EFUSE_TEST 0x0034 // E-Fuse Test. | |
179 | #define PWR_DATA 0x0038 // Power on date. | |
180 | #define DBG_PORT 0x003A // MAC debug port select | |
181 | #define DPS_TIMER 0x003C // Deep Power Save Timer Register. | |
182 | #define RCLK_MON 0x003E // Retention Clock Monitor. | |
183 | ||
184 | // | |
185 | // 2. Command Control Registers (Offset: 0x0040 - 0x004F) | |
186 | // | |
187 | #define CMDR 0x0040 // MAC Command Register. | |
188 | #define TXPAUSE 0x0042 // Transmission Pause Register. | |
189 | #define LBKMD_SEL 0x0043 // Loopback Mode Select Register. | |
190 | #define TCR 0x0044 // Transmit Configuration Register | |
191 | #define RCR 0x0048 // Receive Configuration Register | |
192 | #define MSR 0x004C // Media Status register | |
193 | #define SYSF_CFG 0x004D // System Function Configuration. | |
194 | #define RX_PKY_LIMIT 0x004E // RX packet length limit | |
195 | #define MBIDCTRL 0x004F // MBSSID Control. | |
196 | ||
197 | // | |
198 | // 3. MACID Setting Registers (Offset: 0x0050 - 0x007F) | |
199 | // | |
200 | #define MACIDR 0x0050 // MAC ID Register, Offset 0x0050-0x0055 | |
201 | #define MACIDR0 0x0050 // MAC ID Register, Offset 0x0050-0x0053 | |
202 | #define MACIDR4 0x0054 // MAC ID Register, Offset 0x0054-0x0055 | |
203 | #define BSSIDR 0x0058 // BSSID Register, Offset 0x0058-0x005D | |
204 | #define HWVID 0x005E // HW Version ID. | |
205 | #define MAR 0x0060 // Multicase Address. | |
206 | #define MBIDCAMCONTENT 0x0068 // MBSSID CAM Content. | |
207 | #define MBIDCAMCFG 0x0070 // MBSSID CAM Configuration. | |
208 | #define BUILDTIME 0x0074 // Build Time Register. | |
209 | #define BUILDUSER 0x0078 // Build User Register. | |
210 | ||
211 | // Redifine MACID register, to compatible prior ICs. | |
212 | #define IDR0 MACIDR0 | |
213 | #define IDR4 MACIDR4 | |
214 | ||
215 | // | |
216 | // 4. Timing Control Registers (Offset: 0x0080 - 0x009F) | |
217 | // | |
218 | #define TSFR 0x0080 // Timing Sync Function Timer Register. | |
219 | #define SLOT_TIME 0x0089 // Slot Time Register, in us. | |
220 | #define USTIME 0x008A // EDCA/TSF clock unit time us unit. | |
221 | #define SIFS_CCK 0x008C // SIFS for CCK, in us. | |
222 | #define SIFS_OFDM 0x008E // SIFS for OFDM, in us. | |
223 | #define PIFS_TIME 0x0090 // PIFS time register. | |
224 | #define ACK_TIMEOUT 0x0091 // Ack Timeout Register | |
225 | #define EIFSTR 0x0092 // EIFS time regiser. | |
226 | #define BCN_INTERVAL 0x0094 // Beacon Interval, in TU. | |
227 | #define ATIMWND 0x0096 // ATIM Window width, in TU. | |
228 | #define BCN_DRV_EARLY_INT 0x0098 // Driver Early Interrupt. | |
229 | #define BCN_DMATIME 0x009A // Beacon DMA and ATIM INT Time. | |
230 | #define BCN_ERR_THRESH 0x009C // Beacon Error Threshold. | |
231 | #define MLT 0x009D // MSDU Lifetime. | |
232 | #define RSVD_MAC_TUNE_US 0x009E // MAC Internal USE. | |
233 | ||
234 | // | |
235 | // 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F) | |
236 | // | |
237 | #define RQPN 0x00A0 | |
238 | #define RQPN1 0x00A0 // Reserved Queue Page Number for BK | |
239 | #define RQPN2 0x00A1 // Reserved Queue Page Number for BE | |
240 | #define RQPN3 0x00A2 // Reserved Queue Page Number for VI | |
241 | #define RQPN4 0x00A3 // Reserved Queue Page Number for VO | |
242 | #define RQPN5 0x00A4 // Reserved Queue Page Number for HCCA | |
243 | #define RQPN6 0x00A5 // Reserved Queue Page Number for CMD | |
244 | #define RQPN7 0x00A6 // Reserved Queue Page Number for MGNT | |
245 | #define RQPN8 0x00A7 // Reserved Queue Page Number for HIGH | |
246 | #define RQPN9 0x00A8 // Reserved Queue Page Number for Beacon | |
247 | #define RQPN10 0x00A9 // Reserved Queue Page Number for Public | |
248 | #define LD_RQPN 0x00AB // | |
249 | #define RXFF_BNDY 0x00AC // | |
250 | #define RXRPT_BNDY 0x00B0 // | |
251 | #define TXPKTBUF_PGBNDY 0x00B4 // | |
252 | #define PBP 0x00B5 // | |
253 | #define RXDRVINFO_SZ 0x00B6 // | |
254 | #define TXFF_STATUS 0x00B7 // | |
255 | #define RXFF_STATUS 0x00B8 // | |
256 | #define TXFF_EMPTY_TH 0x00B9 // | |
257 | #define SDIO_RX_BLKSZ 0x00BC // | |
258 | #define RXDMA 0x00BD // | |
259 | #define RXPKT_NUM 0x00BE // | |
260 | #define C2HCMD_UDT_SIZE 0x00C0 // | |
261 | #define C2HCMD_UDT_ADDR 0x00C2 // | |
262 | #define FIFOPAGE1 0x00C4 // Available public queue page number | |
263 | #define FIFOPAGE2 0x00C8 // | |
264 | #define FIFOPAGE3 0x00CC // | |
265 | #define FIFOPAGE4 0x00D0 // | |
266 | #define FIFOPAGE5 0x00D4 // | |
267 | #define FW_RSVD_PG_CRTL 0x00D8 // | |
268 | #define RXDMA_AGG_PG_TH 0x00D9 // | |
269 | #define TXRPTFF_RDPTR 0x00E0 // | |
270 | #define TXRPTFF_WTPTR 0x00E4 // | |
271 | #define C2HFF_RDPTR 0x00E8 //FIFO Read pointer register. | |
272 | #define C2HFF_WTPTR 0x00EC //FIFO Write pointer register. | |
273 | #define RXFF0_RDPTR 0x00F0 // | |
274 | #define RXFF0_WTPTR 0x00F4 // | |
275 | #define RXFF1_RDPTR 0x00F8 // | |
276 | #define RXFF1_WTPTR 0x00FC // | |
277 | #define RXRPT0_RDPTR 0x0100 // | |
278 | #define RXRPT0_WTPTR 0x0104 // | |
279 | #define RXRPT1_RDPTR 0x0108 // | |
280 | #define RXRPT1_WTPTR 0x010C // | |
281 | #define RX0_UDT_SIZE 0x0110 // | |
282 | #define RX1PKTNUM 0x0114 // | |
283 | #define RXFILTERMAP 0x0116 // | |
284 | #define RXFILTERMAP_GP1 0x0118 // | |
285 | #define RXFILTERMAP_GP2 0x011A // | |
286 | #define RXFILTERMAP_GP3 0x011C // | |
287 | #define BCNQ_CTRL 0x0120 // | |
288 | #define MGTQ_CTRL 0x0124 // | |
289 | #define HIQ_CTRL 0x0128 // | |
290 | #define VOTID7_CTRL 0x012c // | |
291 | #define VOTID6_CTRL 0x0130 // | |
292 | #define VITID5_CTRL 0x0134 // | |
293 | #define VITID4_CTRL 0x0138 // | |
294 | #define BETID3_CTRL 0x013c // | |
295 | #define BETID0_CTRL 0x0140 // | |
296 | #define BKTID2_CTRL 0x0144 // | |
297 | #define BKTID1_CTRL 0x0148 // | |
298 | #define CMDQ_CTRL 0x014c // | |
299 | #define TXPKT_NUM_CTRL 0x0150 // | |
300 | #define TXQ_PGADD 0x0152 // | |
301 | #define TXFF_PG_NUM 0x0154 // | |
302 | #define TRXDMA_STATUS 0x0156 // | |
303 | ||
304 | // | |
305 | // 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) | |
306 | // | |
307 | #define INIMCS_SEL 0x0160 // Init MCSrate for 32 MACID 0x160-17f | |
308 | #define TX_RATE_REG INIMCS_SEL //Current Tx rate register | |
309 | #define INIRTSMCS_SEL 0x0180 // Init RTSMCSrate | |
310 | #define RRSR 0x0181 // Response rate setting. | |
311 | #define ARFR0 0x0184 // Auto Rate Fallback 0 Register. | |
312 | #define ARFR1 0x0188 // | |
313 | #define ARFR2 0x018C // | |
314 | #define ARFR3 0x0190 // | |
315 | #define ARFR4 0x0194 // | |
316 | #define ARFR5 0x0198 // | |
317 | #define ARFR6 0x019C // | |
318 | #define ARFR7 0x01A0 // | |
319 | #define AGGLEN_LMT_H 0x01A7 // Aggregation Length Limit for High-MCS | |
320 | #define AGGLEN_LMT_L 0x01A8 // Aggregation Length Limit for Low-MCS. | |
321 | #define DARFRC 0x01B0 // Data Auto Rate Fallback Retry Count. | |
322 | #define RARFRC 0x01B8 // Response Auto Rate Fallback Count. | |
323 | #define MCS_TXAGC 0x01C0 | |
324 | #define CCK_TXAGC 0x01C8 | |
325 | ||
326 | // | |
327 | // 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF) | |
328 | // | |
329 | #define EDCAPARA_VO 0x01D0 // EDCA Parameter Register for VO queue. | |
330 | #define EDCAPARA_VI 0x01D4 // EDCA Parameter Register for VI queue. | |
331 | #define EDCAPARA_BE 0x01D8 // EDCA Parameter Register for BE queue. | |
332 | #define EDCAPARA_BK 0x01DC // EDCA Parameter Register for BK queue. | |
333 | #define BCNTCFG 0x01E0 // Beacon Time Configuration Register. | |
334 | #define CWRR 0x01E2 // Contention Window Report Register. | |
335 | #define ACMAVG 0x01E4 // ACM Average Register. | |
336 | #define AcmHwCtrl 0x01E7 | |
337 | #define VO_ADMTM 0x01E8 // Admission Time Register. | |
338 | #define VI_ADMTM 0x01EC | |
339 | #define BE_ADMTM 0x01F0 | |
340 | #define RETRY_LIMIT 0x01F4 // Retry Limit Registers[15:8]-short, [7:0]-long | |
341 | #define SG_RATE 0x01F6 // Max MCS Rate Available Register, which we Set the hightst SG rate. | |
342 | ||
343 | // | |
344 | // 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F) | |
345 | // | |
346 | #define NAV_CTRL 0x0200 | |
347 | #define BW_OPMODE 0x0203 | |
348 | #define BACAMCMD 0x0204 | |
349 | #define BACAMCONTENT 0x0208 // Block ACK CAM R/W Register. | |
350 | ||
351 | // Roger had defined the 0x2xx register WMAC definition | |
352 | #define LBDLY 0x0210 // Loopback Delay Register. | |
353 | #define FWDLY 0x0211 // FW Delay Register. | |
354 | #define HWPC_RX_CTRL 0x0218 // HW Packet Conversion RX Control Reg | |
355 | #define MQIR 0x0220 // Mesh Qos Type Indication Register. | |
356 | #define MAIR 0x0222 // Mesh ACK. | |
357 | #define MSIR 0x0224 // Mesh HW Security Requirement Indication Reg | |
358 | #define CLM_RESULT 0x0227 // CCA Busy Fraction(Channel Load) | |
359 | #define NHM_RPI_CNT 0x0228 // Noise Histogram Measurement (NHM) RPI Report. | |
360 | #define RXERR_RPT 0x0230 // Rx Error Report. | |
361 | #define NAV_PROT_LEN 0x0234 // NAV Protection Length. | |
362 | #define CFEND_TH 0x0236 // CF-End Threshold. | |
363 | #define AMPDU_MIN_SPACE 0x0237 // AMPDU Min Space. | |
364 | #define TXOP_STALL_CTRL 0x0238 | |
365 | ||
366 | // | |
367 | // 9. Security Control Registers (Offset: 0x0240 - 0x025F) | |
368 | // | |
369 | #define RWCAM 0x0240 //IN 8190 Data Sheet is called CAMcmd | |
370 | #define WCAMI 0x0244 // Software write CAM input content | |
371 | #define RCAMO 0x0248 // Software read/write CAM config | |
372 | #define CAMDBG 0x024C | |
373 | #define SECR 0x0250 //Security Configuration Register | |
374 | ||
375 | // | |
376 | // 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) | |
377 | // | |
378 | #define WOW_CTRL 0x0260 //Wake On WLAN Control. | |
379 | #define PSSTATUS 0x0261 // Power Save Status. | |
380 | #define PSSWITCH 0x0262 // Power Save Switch. | |
381 | #define MIMOPS_WAIT_PERIOD 0x0263 | |
382 | #define LPNAV_CTRL 0x0264 | |
383 | #define WFM0 0x0270 // Wakeup Frame Mask. | |
384 | #define WFM1 0x0280 // | |
385 | #define WFM2 0x0290 // | |
386 | #define WFM3 0x02A0 // | |
387 | #define WFM4 0x02B0 // | |
388 | #define WFM5 0x02C0 // FW Control register. | |
389 | #define WFCRC 0x02D0 // Wakeup Frame CRC. | |
390 | #define RPWM 0x02DC // Host Request Power Mode. | |
391 | #define CPWM 0x02DD // Current Power Mode. | |
392 | #define FW_RPT_REG 0x02c4 | |
393 | ||
394 | // | |
395 | // 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF) | |
396 | // | |
397 | #define PSTIME 0x02E0 // Power Save Timer Register | |
398 | #define TIMER0 0x02E4 // | |
399 | #define TIMER1 0x02E8 // | |
400 | #define GPIO_CTRL 0x02EC // GPIO Control Register | |
401 | #define GPIO_IN 0x02EC // GPIO pins input value | |
402 | #define GPIO_OUT 0x02ED // GPIO pins output value | |
403 | #define GPIO_IO_SEL 0x02EE // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. | |
404 | #define GPIO_MOD 0x02EF // | |
405 | #define GPIO_INTCTRL 0x02F0 // GPIO Interrupt Control Register[7:0] | |
406 | #define MAC_PINMUX_CFG 0x02F1 // MAC PINMUX Configuration Reg[7:0] | |
407 | #define LEDCFG 0x02F2 // System PINMUX Configuration Reg[7:0] | |
408 | #define PHY_REG 0x02F3 // RPT: PHY REG Access Report Reg[7:0] | |
409 | #define PHY_REG_DATA 0x02F4 // PHY REG Read DATA Register [31:0] | |
410 | #define EFUSE_CLK 0x02F8 // CTRL: E-FUSE Clock Control Reg[7:0] | |
411 | //#define GPIO_INTCTRL 0x02F9 // GPIO Interrupt Control Register[7:0] | |
412 | ||
413 | // | |
414 | // 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) | |
415 | // | |
416 | #define IMR 0x0300 // Interrupt Mask Register | |
417 | #define ISR 0x0308 // Interrupt Status Register | |
418 | ||
419 | // | |
420 | // 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F) | |
421 | // | |
422 | #define DBG_PORT_SWITCH 0x003A | |
423 | #define BIST 0x0310 // Bist reg definition | |
424 | #define DBS 0x0314 // Debug Select ??? | |
425 | #define CPUINST 0x0318 // CPU Instruction Read Register | |
426 | #define CPUCAUSE 0x031C // CPU Cause Register | |
427 | #define LBUS_ERR_ADDR 0x0320 // Lexra Bus Error Address Register | |
428 | #define LBUS_ERR_CMD 0x0324 // Lexra Bus Error Command Register | |
429 | #define LBUS_ERR_DATA_L 0x0328 // Lexra Bus Error Data Low DW Register | |
430 | #define LBUS_ERR_DATA_H 0x032C // | |
431 | #define LX_EXCEPTION_ADDR 0x0330 // Lexra Bus Exception Address Register | |
432 | #define WDG_CTRL 0x0334 // Watch Dog Control Register | |
433 | #define INTMTU 0x0338 // Interrupt Mitigation Time Unit Reg | |
434 | #define INTM 0x033A // Interrupt Mitigation Register | |
435 | #define FDLOCKTURN0 0x033C // FW/DRV Lock Turn 0 Register | |
436 | #define FDLOCKTURN1 0x033D // FW/DRV Lock Turn 1 Register | |
437 | #define TRXPKTBUF_DBG_DATA 0x0340 // TRX Packet Buffer Debug Data Register | |
438 | #define TRXPKTBUF_DBG_CTRL 0x0348 // TRX Packet Buffer Debug Control Reg | |
439 | #define DPLL 0x034A // DPLL Monitor Register [15:0] | |
440 | #define CBUS_ERR_ADDR 0x0350 // CPU Bus Error Address Register | |
441 | #define CBUS_ERR_CMD 0x0354 // CPU Bus Error Command Register | |
442 | #define CBUS_ERR_DATA_L 0x0358 // CPU Bus Error Data Low DW Register | |
443 | #define CBUS_ERR_DATA_H 0x035C // | |
444 | #define USB_SIE_INTF_ADDR 0x0360 // USB SIE Access Interface Address Reg | |
445 | #define USB_SIE_INTF_WD 0x0361 // USB SIE Access Interface WData Reg | |
446 | #define USB_SIE_INTF_RD 0x0362 // USB SIE Access Interface RData Reg | |
447 | #define USB_SIE_INTF_CTRL 0x0363 // USB SIE Access Interface Control Reg | |
448 | ||
449 | // Boundary is 0x37F | |
450 | ||
451 | // | |
452 | // 14. PCIE config register (Offset 0x500-) | |
453 | // | |
454 | #define TPPoll 0x0500 // Transmit Polling | |
455 | #define PM_CTRL 0x0502 // PCIE power management control Register | |
456 | #define PCIF 0x0503 // PCI Function Register 0x0009h~0x000bh | |
457 | ||
458 | #define THPDA 0x0514 // Transmit High Priority Desc Addr | |
459 | #define TMDA 0x0518 // Transmit Management Desc Addr | |
460 | #define TCDA 0x051C // Transmit Command Desc Addr | |
461 | #define HDA 0x0520 // HCCA Desc Addr | |
462 | #define TVODA 0x0524 // Transmit VO Desc Addr | |
463 | #define TVIDA 0x0528 // Transmit VI Desc Addr | |
464 | #define TBEDA 0x052C // Transmit BE Desc Addr | |
465 | #define TBKDA 0x0530 // Transmit BK Desc Addr | |
466 | #define TBDA 0x0534 // Transmit Beacon Desc Addr | |
467 | #define RCDA 0x0538 // Receive Command Desc Addr | |
468 | #define RDSA 0x053C // Receive Desc Starting Addr | |
469 | #define DBI_WDATA 0x0540 // DBI write data Register | |
470 | #define DBI_RDATA 0x0544 // DBI read data Register | |
471 | #define DBI_CTRL 0x0548 // PCIE DBI control Register | |
472 | #define MDIO_DATA 0x0550 // PCIE MDIO data Register | |
473 | #define MDIO_CTRL 0x0554 // PCIE MDIO control Register | |
474 | #define PCI_RPWM 0x0561 // PCIE RPWM register | |
475 | #define PCI_CPWM 0x0563 // Current Power Mode. | |
476 | ||
477 | // | |
478 | // Config register (Offset 0x800-) | |
479 | // | |
480 | #define PHY_CCA 0x803 // CCA related register | |
481 | ||
482 | //============================================================================ | |
483 | // 8192S USB specific Regsiter Offset and Content definition, | |
484 | // 2008.08.28, added by Roger. | |
485 | //============================================================================ | |
486 | // Rx Aggregation time-out reg. | |
487 | #define USB_RX_AGG_TIMEOUT 0xFE5B | |
488 | ||
489 | // Firware reserved Tx page control. | |
490 | #define FW_OFFLOAD_EN BIT7 | |
491 | ||
492 | // Min Spacing related settings. | |
493 | #define MAX_MSS_DENSITY 0x13 | |
494 | #define MAX_MSS_DENSITY_2T 0x13 | |
495 | #define MAX_MSS_DENSITY_1T 0x0A | |
496 | ||
497 | // Rx DMA Control related settings | |
498 | #define RXDMA_AGG_EN BIT7 | |
499 | ||
500 | // USB Rx Aggregation TimeOut settings | |
501 | #define RXDMA_AGG_TIMEOUT_DISABLE 0x00 | |
502 | #define RXDMA_AGG_TIMEOUT_17MS 0x01 | |
503 | #define RXDMA_AGG_TIMEOUT_17_2_MS 0x02 | |
504 | #define RXDMA_AGG_TIMEOUT_17_4_MS 0x04 | |
505 | #define RXDMA_AGG_TIMEOUT_17_10_MS 0x0A | |
506 | // USB RPWM register | |
507 | #define USB_RPWM 0xFE58 | |
508 | ||
5f53d8ca JC |
509 | //============================================================================ |
510 | // 8190 Regsiter offset definition | |
511 | //============================================================================ | |
512 | #if 1 // Delete the register later | |
513 | #define AFR 0x010 // AutoLoad Function Register | |
514 | #define BCN_TCFG 0x062 // Beacon Time Configuration | |
515 | #define RATR0 0x320 // Rate Adaptive Table register1 | |
516 | #endif | |
517 | // TODO: Remove unused register, We must declare backward compatiable | |
518 | //Undefined register set in 8192S. 0x320/350 DW is useless | |
519 | #define UnusedRegister 0x0320 | |
520 | #define PSR UnusedRegister // Page Select Register | |
521 | //Security Related | |
522 | #define DCAM UnusedRegister // Debug CAM Interface | |
523 | //PHY Configuration related | |
524 | #define BBAddr UnusedRegister // Phy register address register | |
525 | #define PhyDataR UnusedRegister // Phy register data read | |
526 | #define UFWP UnusedRegister | |
527 | ||
528 | ||
529 | //============================================================================ | |
530 | // 8192S Regsiter Bit and Content definition | |
531 | //============================================================================ | |
532 | ||
533 | // | |
534 | // 1. System Configuration Registers (Offset: 0x0000 - 0x003F) | |
535 | // | |
536 | //---------------------------------------------------------------------------- | |
537 | // 8192S SYS_ISO_CTRL bits (Offset 0x0, 16bit) | |
538 | //---------------------------------------------------------------------------- | |
539 | #define ISO_MD2PP BIT0 // MACTOP/BB/PCIe Digital to Power On. | |
540 | #define ISO_PA2PCIE BIT3 // PCIe Analog 1.2V to PCIe 3.3V | |
541 | #define ISO_PLL2MD BIT4 // AFE PLL to MACTOP/BB/PCIe Digital. | |
542 | #define ISO_PWC_DV2RP BIT11 // Digital Vdd to Retention Path | |
543 | #define ISO_PWC_RV2RP BIT12 // LPLDOR12 to Retenrion Path, 1: isolation, 0: attach. | |
544 | ||
545 | //---------------------------------------------------------------------------- | |
546 | // 8192S SYS_FUNC_EN bits (Offset 0x2, 16bit) | |
547 | //---------------------------------------------------------------------------- | |
548 | #define FEN_MREGEN BIT15 // MAC I/O Registers Enable. | |
549 | #define FEN_DCORE BIT11 // Enable Core Digital. | |
550 | #define FEN_CPUEN BIT10 // Enable CPU Core Digital. | |
551 | // 8192S PMC_FSM bits (Offset 0x4, 32bit) | |
552 | //---------------------------------------------------------------------------- | |
553 | #define PAD_HWPD_IDN BIT22 // HWPDN PAD status Indicator | |
554 | ||
555 | //---------------------------------------------------------------------------- | |
556 | ||
557 | //---------------------------------------------------------------------------- | |
558 | // 8192S SYS_CLKR bits (Offset 0x8, 16bit) | |
559 | //---------------------------------------------------------------------------- | |
560 | #define SYS_CLKSEL_80M BIT0 // System Clock 80MHz | |
561 | #define SYS_PS_CLKSEL BIT1 //System power save clock select. | |
562 | #define SYS_CPU_CLKSEL BIT2 // System Clock select, 1: AFE source, 0: System clock(L-Bus) | |
563 | #define SYS_MAC_CLK_EN BIT11 // MAC Clock Enable. | |
564 | #define SYS_SWHW_SEL BIT14 // Load done, control path seitch. | |
565 | #define SYS_FWHW_SEL BIT15 // Sleep exit, control path swith. | |
566 | ||
567 | ||
568 | //---------------------------------------------------------------------------- | |
569 | // 8192S Cmd9346CR bits (Offset 0xA, 16bit) | |
570 | //---------------------------------------------------------------------------- | |
571 | #define CmdEEPROM_En BIT5 // EEPROM enable when set 1 | |
572 | #define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 | |
573 | #define Cmd9346CR_9356SEL BIT4 | |
574 | #define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) | |
575 | #define AutoLoadEFUSE CmdEEPROM_En | |
576 | ||
577 | ||
578 | //---------------------------------------------------------------------------- | |
579 | // 8192S AFE_MISC bits AFE Misc (Offset 0x10, 8bits) | |
580 | //---------------------------------------------------------------------------- | |
581 | #define AFE_MBEN BIT1 // Enable AFE Macro Block's Mbias. | |
582 | #define AFE_BGEN BIT0 // Enable AFE Macro Block's Bandgap. | |
583 | ||
584 | //---------------------------------------------------------------------------- | |
585 | // 8192S SPS1_CTRL bits (Offset 0x18-1E, 56bits) | |
586 | //---------------------------------------------------------------------------- | |
587 | #define SPS1_SWEN BIT1 // Enable vsps18 SW Macro Block. | |
588 | #define SPS1_LDEN BIT0 // Enable VSPS12 LDO Macro block. | |
589 | ||
590 | //---------------------------------------------------------------------------- | |
591 | // 8192S RF_CTRL bits (Offset 0x1F, 8bits) | |
592 | //---------------------------------------------------------------------------- | |
593 | #define RF_EN BIT0 // Enable RF module. | |
594 | #define RF_RSTB BIT1 // Reset RF module. | |
595 | #define RF_SDMRSTB BIT2 // Reset RF SDM module. | |
596 | ||
597 | //---------------------------------------------------------------------------- | |
598 | // 8192S LDOA15_CTRL bits (Offset 0x20, 8bits) | |
599 | //---------------------------------------------------------------------------- | |
600 | #define LDA15_EN BIT0 // Enable LDOA15 Macro Block | |
601 | ||
602 | //---------------------------------------------------------------------------- | |
603 | // 8192S LDOV12D_CTRL bits (Offset 0x21, 8bits) | |
604 | //---------------------------------------------------------------------------- | |
605 | #define LDV12_EN BIT0 // Enable LDOVD12 Macro Block | |
606 | #define LDV12_SDBY BIT1 // LDOVD12 standby mode | |
607 | ||
608 | //---------------------------------------------------------------------------- | |
609 | // 8192S AFE_XTAL_CTRL bits AFE Crystal Control. (Offset 0x26,16bits) | |
610 | //---------------------------------------------------------------------------- | |
611 | #define XTAL_GATE_AFE BIT10 | |
612 | // Gated Control. 1: AFE Clock source gated, 0: Clock enable. | |
613 | ||
614 | //---------------------------------------------------------------------------- | |
615 | // 8192S AFE_PLL_CTRL bits System Function Enable (Offset 0x28,64bits) | |
616 | //---------------------------------------------------------------------------- | |
617 | #define APLL_EN BIT0 // Enable AFE PLL Macro Block. | |
618 | ||
619 | // Find which card bus type | |
620 | #define AFR_CardBEn BIT0 | |
621 | #define AFR_CLKRUN_SEL BIT1 | |
622 | #define AFR_FuncRegEn BIT2 | |
623 | ||
624 | // | |
625 | // 2. Command Control Registers (Offset: 0x0040 - 0x004F) | |
626 | // | |
627 | //---------------------------------------------------------------------------- | |
628 | // 8192S (CMD) command register bits (Offset 0x40, 16 bits) | |
629 | //---------------------------------------------------------------------------- | |
630 | #define APSDOFF_STATUS BIT15 // | |
631 | #define APSDOFF BIT14 // | |
632 | #define BBRSTn BIT13 //Enable OFDM/CCK | |
633 | #define BB_GLB_RSTn BIT12 //Enable BB | |
634 | #define SCHEDULE_EN BIT10 //Enable MAC scheduler | |
635 | #define MACRXEN BIT9 // | |
636 | #define MACTXEN BIT8 // | |
637 | #define DDMA_EN BIT7 //FW off load function enable | |
638 | #define FW2HW_EN BIT6 //MAC every module reset as below | |
639 | #define RXDMA_EN BIT5 // | |
640 | #define TXDMA_EN BIT4 // | |
641 | #define HCI_RXDMA_EN BIT3 // | |
642 | #define HCI_TXDMA_EN BIT2 // | |
643 | ||
644 | //---------------------------------------------------------------------------- | |
645 | // 8192S (TXPAUSE) transmission pause (Offset 0x42, 8 bits) | |
646 | //---------------------------------------------------------------------------- | |
647 | #define StopHCCA BIT6 | |
648 | #define StopHigh BIT5 | |
649 | #define StopMgt BIT4 | |
650 | #define StopVO BIT3 | |
651 | #define StopVI BIT2 | |
652 | #define StopBE BIT1 | |
653 | #define StopBK BIT0 | |
654 | ||
655 | //---------------------------------------------------------------------------- | |
656 | // 8192S (LBKMD) LoopBack Mode Select (Offset 0x43, 8 bits) | |
657 | //---------------------------------------------------------------------------- | |
658 | // | |
659 | // [3] no buffer, 1: no delay, 0: delay; [2] dmalbk, [1] no_txphy, [0] diglbk. | |
660 | // 0000: Normal | |
661 | // 1011: MAC loopback (involving CPU) | |
662 | // 0011: MAC Delay Loopback | |
663 | // 0001: PHY loopback (not yet implemented) | |
664 | // 0111: DMA loopback (only uses TxPktBuffer and DMA engine) | |
665 | // All other combinations are reserved. | |
666 | // Default: 0000b. | |
667 | // | |
668 | #define LBK_NORMAL 0x00 | |
669 | #define LBK_MAC_LB (BIT0|BIT1|BIT3) | |
670 | #define LBK_MAC_DLB (BIT0|BIT1) | |
671 | #define LBK_DMA_LB (BIT0|BIT1|BIT2) | |
672 | ||
673 | //---------------------------------------------------------------------------- | |
674 | // 8192S (TCR) transmission Configuration Register (Offset 0x44, 32 bits) | |
675 | //---------------------------------------------------------------------------- | |
676 | #define TCP_OFDL_EN BIT25 //For CE packet conversion | |
677 | #define HWPC_TX_EN BIT24 //"" | |
678 | #define TXDMAPRE2FULL BIT23 //TXDMA enable pre2full sync | |
679 | #define DISCW BIT20 //CW disable | |
680 | #define TCRICV BIT19 //Append ICV or not | |
681 | #define CfendForm BIT17 //AP mode | |
682 | #define TCRCRC BIT16 //Append CRC32 | |
683 | #define FAKE_IMEM_EN BIT15 // | |
684 | #define TSFRST BIT9 // | |
685 | #define TSFEN BIT8 // | |
686 | // For TCR FW download ready --> write by FW Bit0-7 must all one | |
687 | #define FWALLRDY (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7) | |
688 | #define FWRDY BIT7 | |
689 | #define BASECHG BIT6 | |
690 | #define IMEM BIT5 | |
691 | #define DMEM_CODE_DONE BIT4 | |
692 | #define EXT_IMEM_CHK_RPT BIT3 | |
693 | #define EXT_IMEM_CODE_DONE BIT2 | |
694 | #define IMEM_CHK_RPT BIT1 | |
695 | #define IMEM_CODE_DONE BIT0 | |
696 | // Copy fomr 92SU definition | |
697 | #define IMEM_CODE_DONE BIT0 | |
698 | #define IMEM_CHK_RPT BIT1 | |
699 | #define EMEM_CODE_DONE BIT2 | |
700 | #define EMEM_CHK_RPT BIT3 | |
701 | #define DMEM_CODE_DONE BIT4 | |
702 | #define IMEM_RDY BIT5 | |
703 | #define BASECHG BIT6 | |
704 | #define FWRDY BIT7 | |
705 | #define LOAD_FW_READY (IMEM_CODE_DONE|IMEM_CHK_RPT|EMEM_CODE_DONE|\ | |
706 | EMEM_CHK_RPT|DMEM_CODE_DONE|IMEM_RDY|BASECHG|\ | |
707 | FWRDY) | |
708 | #define TCR_TSFEN BIT8 // TSF function on or off. | |
709 | #define TCR_TSFRST BIT9 // Reset TSF function to zero. | |
710 | #define TCR_FAKE_IMEM_EN BIT15 | |
711 | #define TCR_CRC BIT16 | |
712 | #define TCR_ICV BIT19 // Integrity Check Value. | |
713 | #define TCR_DISCW BIT20 // Disable Contention Windows Backoff. | |
714 | #define TCR_HWPC_TX_EN BIT24 | |
715 | #define TCR_TCP_OFDL_EN BIT25 | |
716 | #define TXDMA_INIT_VALUE (IMEM_CHK_RPT|EXT_IMEM_CHK_RPT) | |
717 | //---------------------------------------------------------------------------- | |
718 | // 8192S (RCR) Receive Configuration Register (Offset 0x48, 32 bits) | |
719 | //---------------------------------------------------------------------------- | |
720 | #define RCR_APPFCS BIT31 //WMAC append FCS after pauload | |
721 | #define RCR_DIS_ENC_2BYTE BIT30 //HW encrypt 2 or 1 byte mode | |
722 | #define RCR_DIS_AES_2BYTE BIT29 // | |
723 | #define RCR_HTC_LOC_CTRL BIT28 //MFC<--HTC=1 MFC-->HTC=0 | |
724 | #define RCR_ENMBID BIT27 //Enable Multiple BssId. | |
725 | #define RCR_RX_TCPOFDL_EN BIT26 // | |
726 | #define RCR_APP_PHYST_RXFF BIT25 // | |
727 | #define RCR_APP_PHYST_STAFF BIT24 // | |
728 | #define RCR_CBSSID BIT23 //Accept BSSID match packet | |
729 | #define RCR_APWRMGT BIT22 //Accept power management packet | |
730 | #define RCR_ADD3 BIT21 //Accept address 3 match packet | |
731 | #define RCR_AMF BIT20 //Accept management type frame | |
732 | #define RCR_ACF BIT19 //Accept control type frame | |
733 | #define RCR_ADF BIT18 //Accept data type frame | |
734 | #define RCR_APP_MIC BIT17 // | |
735 | #define RCR_APP_ICV BIT16 // | |
736 | #define RCR_RXFTH BIT13 //Rx FIFO Threshold Bot 13 - 15 | |
737 | #define RCR_AICV BIT12 //Accept ICV error packet | |
738 | #define RCR_RXDESC_LK_EN BIT11 //Accept to update rx desc length | |
739 | #define RCR_APP_BA_SSN BIT6 //Accept BA SSN | |
740 | #define RCR_ACRC32 BIT5 //Accept CRC32 error packet | |
741 | #define RCR_RXSHFT_EN BIT4 //Accept broadcast packet | |
742 | #define RCR_AB BIT3 //Accept broadcast packet | |
743 | #define RCR_AM BIT2 //Accept multicast packet | |
744 | #define RCR_APM BIT1 //Accept physical match packet | |
745 | #define RCR_AAP BIT0 //Accept all unicast packet | |
746 | #define RCR_MXDMA_OFFSET 8 | |
747 | #define RCR_FIFO_OFFSET 13 | |
748 | ||
5f53d8ca JC |
749 | #define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. |
750 | #define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 | |
751 | #define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 | |
752 | #define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames | |
c6813185 | 753 | |
5f53d8ca JC |
754 | //---------------------------------------------------------------------------- |
755 | // 8192S (MSR) Media Status Register (Offset 0x4C, 8 bits) | |
756 | //---------------------------------------------------------------------------- | |
757 | /* | |
758 | Network Type | |
759 | 00: No link | |
760 | 01: Link in ad hoc network | |
761 | 10: Link in infrastructure network | |
762 | 11: AP mode | |
763 | Default: 00b. | |
764 | */ | |
765 | #define MSR_NOLINK 0x00 | |
766 | #define MSR_ADHOC 0x01 | |
767 | #define MSR_INFRA 0x02 | |
768 | #define MSR_AP 0x03 | |
769 | ||
770 | //---------------------------------------------------------------------------- | |
771 | // 8192S (SYSF_CFG) system Fucntion Config Reg (Offset 0x4D, 8 bits) | |
772 | //---------------------------------------------------------------------------- | |
773 | #define ENUART BIT7 | |
774 | #define ENJTAG BIT3 | |
775 | #define BTMODE (BIT2|BIT1) | |
776 | #define ENBT BIT0 | |
777 | ||
778 | //---------------------------------------------------------------------------- | |
779 | // 8192S (MBIDCTRL) MBSSID Control Register (Offset 0x4F, 8 bits) | |
780 | //---------------------------------------------------------------------------- | |
781 | #define ENMBID BIT7 | |
782 | #define BCNUM (BIT6|BIT5|BIT4) | |
783 | ||
784 | // | |
785 | // 3. MACID Setting Registers (Offset: 0x0050 - 0x007F) | |
786 | // | |
787 | ||
788 | // | |
789 | // 4. Timing Control Registers (Offset: 0x0080 - 0x009F) | |
790 | // | |
791 | //---------------------------------------------------------------------------- | |
792 | // 8192S (USTIME) US Time Tunning Register (Offset 0x8A, 16 bits) | |
793 | //---------------------------------------------------------------------------- | |
794 | #define USTIME_EDCA 0xFF00 | |
795 | #define USTIME_TSF 0x00FF | |
796 | ||
797 | //---------------------------------------------------------------------------- | |
798 | // 8192S (SIFS_CCK/OFDM) US Time Tunning Register (Offset 0x8C/8E,16 bits) | |
799 | //---------------------------------------------------------------------------- | |
800 | #define SIFS_TRX 0xFF00 | |
801 | #define SIFS_CTX 0x00FF | |
802 | ||
803 | //---------------------------------------------------------------------------- | |
804 | // 8192S (DRVERLYINT) Driver Early Interrupt Reg (Offset 0x98, 16bit) | |
805 | //---------------------------------------------------------------------------- | |
806 | #define ENSWBCN BIT15 | |
807 | #define DRVERLY_TU 0x0FF0 | |
808 | #define DRVERLY_US 0x000F | |
809 | #define BCN_TCFG_CW_SHIFT 8 | |
810 | #define BCN_TCFG_IFS 0 | |
811 | ||
812 | // | |
813 | // 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F) | |
814 | // | |
815 | ||
816 | // | |
817 | // 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) | |
818 | // | |
819 | //---------------------------------------------------------------------------- | |
820 | // 8192S Response Rate Set Register (offset 0x181, 24bits) | |
821 | //---------------------------------------------------------------------------- | |
822 | #define RRSR_RSC_OFFSET 21 | |
823 | #define RRSR_SHORT_OFFSET 23 | |
824 | #define RRSR_RSC_BW_40M 0x600000 | |
825 | #define RRSR_RSC_UPSUBCHNL 0x400000 | |
826 | #define RRSR_RSC_LOWSUBCHNL 0x200000 | |
827 | #define RRSR_SHORT 0x800000 | |
828 | #define RRSR_1M BIT0 | |
829 | #define RRSR_2M BIT1 | |
830 | #define RRSR_5_5M BIT2 | |
831 | #define RRSR_11M BIT3 | |
832 | #define RRSR_6M BIT4 | |
833 | #define RRSR_9M BIT5 | |
834 | #define RRSR_12M BIT6 | |
835 | #define RRSR_18M BIT7 | |
836 | #define RRSR_24M BIT8 | |
837 | #define RRSR_36M BIT9 | |
838 | #define RRSR_48M BIT10 | |
839 | #define RRSR_54M BIT11 | |
840 | #define RRSR_MCS0 BIT12 | |
841 | #define RRSR_MCS1 BIT13 | |
842 | #define RRSR_MCS2 BIT14 | |
843 | #define RRSR_MCS3 BIT15 | |
844 | #define RRSR_MCS4 BIT16 | |
845 | #define RRSR_MCS5 BIT17 | |
846 | #define RRSR_MCS6 BIT18 | |
847 | #define RRSR_MCS7 BIT19 | |
848 | #define BRSR_AckShortPmb BIT23 | |
849 | ||
850 | #define RRSR_RSC_UPSUBCHANL 0x200000 | |
851 | // CCK ACK: use Short Preamble or not | |
852 | ||
853 | //---------------------------------------------------------------------------- | |
854 | // 8192S Rate Definition | |
855 | //---------------------------------------------------------------------------- | |
856 | //CCK | |
857 | #define RATR_1M 0x00000001 | |
858 | #define RATR_2M 0x00000002 | |
859 | #define RATR_55M 0x00000004 | |
860 | #define RATR_11M 0x00000008 | |
861 | //OFDM | |
862 | #define RATR_6M 0x00000010 | |
863 | #define RATR_9M 0x00000020 | |
864 | #define RATR_12M 0x00000040 | |
865 | #define RATR_18M 0x00000080 | |
866 | #define RATR_24M 0x00000100 | |
867 | #define RATR_36M 0x00000200 | |
868 | #define RATR_48M 0x00000400 | |
869 | #define RATR_54M 0x00000800 | |
870 | //MCS 1 Spatial Stream | |
871 | #define RATR_MCS0 0x00001000 | |
872 | #define RATR_MCS1 0x00002000 | |
873 | #define RATR_MCS2 0x00004000 | |
874 | #define RATR_MCS3 0x00008000 | |
875 | #define RATR_MCS4 0x00010000 | |
876 | #define RATR_MCS5 0x00020000 | |
877 | #define RATR_MCS6 0x00040000 | |
878 | #define RATR_MCS7 0x00080000 | |
879 | //MCS 2 Spatial Stream | |
880 | #define RATR_MCS8 0x00100000 | |
881 | #define RATR_MCS9 0x00200000 | |
882 | #define RATR_MCS10 0x00400000 | |
883 | #define RATR_MCS11 0x00800000 | |
884 | #define RATR_MCS12 0x01000000 | |
885 | #define RATR_MCS13 0x02000000 | |
886 | #define RATR_MCS14 0x04000000 | |
887 | #define RATR_MCS15 0x08000000 | |
888 | // ALL CCK Rate | |
889 | #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M | |
890 | #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ | |
891 | RATR_36M|RATR_48M|RATR_54M | |
892 | #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ | |
893 | RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 | |
894 | #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ | |
895 | RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 | |
896 | ||
897 | // | |
898 | // 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF) | |
899 | // | |
900 | //---------------------------------------------------------------------------- | |
901 | // 8192S EDCA Setting (offset 0x1D0-1DF, 4DW VO/VI/BE/BK) | |
902 | //---------------------------------------------------------------------------- | |
903 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | |
904 | #define AC_PARAM_ECW_MAX_OFFSET 12 | |
905 | #define AC_PARAM_ECW_MIN_OFFSET 8 | |
906 | #define AC_PARAM_AIFS_OFFSET 0 | |
907 | ||
908 | //---------------------------------------------------------------------------- | |
909 | // 8192S AcmHwCtrl bits (offset 0x1E7, 1 byte) | |
910 | //---------------------------------------------------------------------------- | |
911 | #define AcmHw_HwEn BIT0 | |
912 | #define AcmHw_BeqEn BIT1 | |
913 | #define AcmHw_ViqEn BIT2 | |
914 | #define AcmHw_VoqEn BIT3 | |
915 | #define AcmHw_BeqStatus BIT4 | |
916 | #define AcmHw_ViqStatus BIT5 | |
917 | #define AcmHw_VoqStatus BIT6 | |
918 | ||
919 | //---------------------------------------------------------------------------- | |
920 | // 8192S Retry Limit (Offset 0x1F4, 16bit) | |
921 | //---------------------------------------------------------------------------- | |
922 | #define RETRY_LIMIT_SHORT_SHIFT 8 | |
923 | #define RETRY_LIMIT_LONG_SHIFT 0 | |
924 | ||
925 | // | |
926 | // 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F) | |
927 | // | |
928 | //---------------------------------------------------------------------------- | |
929 | // 8192S NAV_CTRL bits (Offset 0x200, 24bit) | |
930 | //---------------------------------------------------------------------------- | |
931 | #define NAV_UPPER_EN BIT16 | |
932 | #define NAV_UPPER 0xFF00 | |
933 | #define NAV_RTSRST 0xFF | |
934 | //---------------------------------------------------------------------------- | |
935 | // 8192S BW_OPMODE bits (Offset 0x203, 8bit) | |
936 | //---------------------------------------------------------------------------- | |
937 | #define BW_OPMODE_20MHZ BIT2 | |
938 | #define BW_OPMODE_5G BIT1 | |
939 | #define BW_OPMODE_11J BIT0 | |
940 | //---------------------------------------------------------------------------- | |
941 | // 8192S BW_OPMODE bits (Offset 0x230, 4 Byte) | |
942 | //---------------------------------------------------------------------------- | |
943 | #define RXERR_RPT_RST BIT27 // Write "one" to set the counter to zero. | |
944 | // RXERR_RPT_SEL | |
945 | #define RXERR_OFDM_PPDU 0 | |
946 | #define RXERR_OFDM_FALSE_ALARM 1 | |
947 | #define RXERR_OFDM_MPDU_OK 2 | |
948 | #define RXERR_OFDM_MPDU_FAIL 3 | |
949 | #define RXERR_CCK_PPDU 4 | |
950 | #define RXERR_CCK_FALSE_ALARM 5 | |
951 | #define RXERR_CCK_MPDU_OK 6 | |
952 | #define RXERR_CCK_MPDU_FAIL 7 | |
953 | #define RXERR_HT_PPDU 8 | |
954 | #define RXERR_HT_FALSE_ALARM 9 | |
955 | #define RXERR_HT_MPDU_TOTAL 10 | |
956 | #define RXERR_HT_MPDU_OK 11 | |
957 | #define RXERR_HT_MPDU_FAIL 12 | |
958 | #define RXERR_RX_FULL_DROP 15 | |
959 | ||
960 | // | |
961 | // 9. Security Control Registers (Offset: 0x0240 - 0x025F) | |
962 | // | |
963 | //---------------------------------------------------------------------------- | |
964 | // 8192S RWCAM CAM Command Register (offset 0x240, 4 byte) | |
965 | //---------------------------------------------------------------------------- | |
966 | #define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling | |
967 | #define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM | |
968 | #define CAM_CM_SecCAMWE BIT16 //Security CAM enable | |
969 | #define CAM_ADDR 0xFF //CAM Address Offset | |
970 | ||
971 | //---------------------------------------------------------------------------- | |
972 | // 8192S CAMDBG Debug CAM Register (offset 0x24C, 4 byte) | |
973 | //---------------------------------------------------------------------------- | |
974 | #define Dbg_CAM_TXSecCAMInfo BIT31 //Retrieve lastest Tx Info | |
975 | #define Dbg_CAM_SecKeyFound BIT30 //Security KEY Found | |
976 | ||
977 | ||
978 | //---------------------------------------------------------------------------- | |
979 | // 8192S SECR Security Configuration Register (offset 0x250, 1 byte) | |
980 | //---------------------------------------------------------------------------- | |
981 | #define SCR_TxUseDK BIT0 //Force Tx Use Default Key | |
982 | #define SCR_RxUseDK BIT1 //Force Rx Use Default Key | |
983 | #define SCR_TxEncEnable BIT2 //Enable Tx Encryption | |
984 | #define SCR_RxDecEnable BIT3 //Enable Rx Decryption | |
985 | #define SCR_SKByA2 BIT4 //Search kEY BY A2 | |
986 | #define SCR_NoSKMC BIT5 //No Key Search Multicast | |
987 | //---------------------------------------------------------------------------- | |
988 | // 8192S CAM Config Setting (offset 0x250, 1 byte) | |
989 | //---------------------------------------------------------------------------- | |
990 | #define CAM_VALID BIT15 | |
991 | #define CAM_NOTVALID 0x0000 | |
992 | #define CAM_USEDK BIT5 | |
993 | ||
994 | #define CAM_NONE 0x0 | |
995 | #define CAM_WEP40 0x01 | |
996 | #define CAM_TKIP 0x02 | |
997 | #define CAM_AES 0x04 | |
998 | #define CAM_WEP104 0x05 | |
999 | ||
1000 | #define TOTAL_CAM_ENTRY 32 | |
1001 | ||
1002 | #define CAM_CONFIG_USEDK TRUE | |
1003 | #define CAM_CONFIG_NO_USEDK FALSE | |
1004 | ||
1005 | #define CAM_WRITE BIT16 | |
1006 | #define CAM_READ 0x00000000 | |
1007 | #define CAM_POLLINIG BIT31 | |
1008 | ||
1009 | #define SCR_UseDK 0x01 | |
1010 | #define SCR_TxSecEnable 0x02 | |
1011 | #define SCR_RxSecEnable 0x04 | |
1012 | ||
1013 | // | |
1014 | // 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) | |
1015 | // | |
1016 | #define WOW_PMEN BIT0 // Power management Enable. | |
1017 | #define WOW_WOMEN BIT1 // WoW function on or off. | |
1018 | #define WOW_MAGIC BIT2 // Magic packet | |
1019 | #define WOW_UWF BIT3 // Unicast Wakeup frame. | |
1020 | ||
1021 | // | |
1022 | // 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF) | |
1023 | // 8192S GPIO Config Setting (offset 0x2F1, 1 byte) | |
1024 | //---------------------------------------------------------------------------- | |
1025 | #define GPIOMUX_EN BIT3 // When this bit is set to "1", GPIO PINs will switch to MAC GPIO Function | |
1026 | #define GPIOSEL_GPIO 0 // UART or JTAG or pure GPIO | |
1027 | #define GPIOSEL_PHYDBG 1 // PHYDBG | |
1028 | #define GPIOSEL_BT 2 // BT_coex | |
1029 | #define GPIOSEL_WLANDBG 3 // WLANDBG | |
1030 | #define GPIOSEL_GPIO_MASK ~(BIT0|BIT1) | |
1031 | ||
1032 | //---------------------------------------------------------------------------- | |
1033 | ||
1034 | //---------------------------------------------------------------------------- | |
1035 | // PHY REG Access Report Register definition | |
1036 | //---------------------------------------------------------------------------- | |
1037 | #define HST_RDBUSY BIT0 | |
1038 | #define CPU_WTBUSY BIT1 | |
1039 | ||
1040 | // | |
1041 | // 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) | |
1042 | // | |
1043 | //---------------------------------------------------------------------------- | |
1044 | // 8190 IMR/ISR bits (offset 0xfd, 8bits) | |
1045 | //---------------------------------------------------------------------------- | |
1046 | #define IMR8190_DISABLED 0x0 | |
1047 | ||
1048 | // IMR DW1 Bit 0-31 | |
1049 | #define IMR_CPUERR BIT5 // CPU error interrupt | |
1050 | #define IMR_ATIMEND BIT4 // ATIM Window End Interrupt | |
1051 | #define IMR_TBDOK BIT3 // Transmit Beacon OK Interrupt | |
1052 | #define IMR_TBDER BIT2 // Transmit Beacon Error Interrupt | |
1053 | #define IMR_BCNDMAINT8 BIT1 // Beacon DMA Interrupt 8 | |
1054 | #define IMR_BCNDMAINT7 BIT0 // Beacon DMA Interrupt 7 | |
1055 | // IMR DW0 Bit 0-31 | |
1056 | ||
1057 | #define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 | |
1058 | #define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 | |
1059 | #define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 | |
1060 | #define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 | |
1061 | #define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 | |
1062 | #define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 | |
1063 | #define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 | |
1064 | #define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 | |
1065 | #define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 | |
1066 | #define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 | |
1067 | #define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 | |
1068 | #define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 | |
1069 | #define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 | |
1070 | #define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 | |
1071 | #define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 | |
1072 | #define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 | |
1073 | #define IMR_TXFOVW BIT15 // Transmit FIFO Overflow | |
1074 | #define IMR_PSTIMEOUT BIT14 // Power save time out interrupt | |
1075 | #define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 | |
1076 | #define IMR_RXFOVW BIT12 // Receive FIFO Overflow | |
1077 | #define IMR_RDU BIT11 // Receive Descriptor Unavailable | |
1078 | #define IMR_RXCMDOK BIT10 // Receive Command Packet OK | |
1079 | #define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup | |
1080 | #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt | |
1081 | #define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt | |
1082 | #define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt | |
1083 | #define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt | |
1084 | #define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt | |
1085 | #define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt | |
1086 | #define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt | |
1087 | #define IMR_VODOK BIT1 // AC_VO DMA Interrupt | |
1088 | #define IMR_ROK BIT0 // Receive DMA OK Interrupt | |
1089 | ||
1090 | // | |
1091 | // 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F) | |
1092 | // | |
1093 | ||
1094 | // | |
1095 | // 14. PCIE config register (Offset 0x500-) | |
1096 | // | |
1097 | //---------------------------------------------------------------------------- | |
1098 | // 8190 TPPool bits (offset 0xd9, 2 byte) | |
1099 | //---------------------------------------------------------------------------- | |
1100 | #define TPPoll_BKQ BIT0 // BK queue polling | |
1101 | #define TPPoll_BEQ BIT1 // BE queue polling | |
1102 | #define TPPoll_VIQ BIT2 // VI queue polling | |
1103 | #define TPPoll_VOQ BIT3 // VO queue polling | |
1104 | #define TPPoll_BQ BIT4 // Beacon queue polling | |
1105 | #define TPPoll_CQ BIT5 // Command queue polling | |
1106 | #define TPPoll_MQ BIT6 // Management queue polling | |
1107 | #define TPPoll_HQ BIT7 // High queue polling | |
1108 | #define TPPoll_HCCAQ BIT8 // HCCA queue polling | |
1109 | #define TPPoll_StopBK BIT9 // Stop BK queue | |
1110 | #define TPPoll_StopBE BIT10 // Stop BE queue | |
1111 | #define TPPoll_StopVI BIT11 // Stop VI queue | |
1112 | #define TPPoll_StopVO BIT12 // Stop VO queue | |
1113 | #define TPPoll_StopMgt BIT13 // Stop Mgnt queue | |
1114 | #define TPPoll_StopHigh BIT14 // Stop High queue | |
1115 | #define TPPoll_StopHCCA BIT15 // Stop HCCA queue | |
1116 | #define TPPoll_SHIFT 8 // Queue ID mapping | |
1117 | ||
1118 | //---------------------------------------------------------------------------- | |
1119 | // 8192S PCIF (Offset 0x500, 32bit) | |
1120 | //---------------------------------------------------------------------------- | |
1121 | #define MXDMA2_16bytes 0x000 | |
1122 | #define MXDMA2_32bytes 0x001 | |
1123 | #define MXDMA2_64bytes 0x010 | |
1124 | #define MXDMA2_128bytes 0x011 | |
1125 | #define MXDMA2_256bytes 0x100 | |
1126 | #define MXDMA2_512bytes 0x101 | |
1127 | #define MXDMA2_1024bytes 0x110 | |
1128 | #define MXDMA2_NoLimit 0x7 | |
1129 | ||
1130 | #define MULRW_SHIFT 3 | |
1131 | #define MXDMA2_RX_SHIFT 4 | |
1132 | #define MXDMA2_TX_SHIFT 0 | |
1133 | ||
1134 | //---------------------------------------------------------------------------- | |
1135 | // 8190 CCX_COMMAND_REG Setting (offset 0x25A, 1 byte) | |
1136 | //---------------------------------------------------------------------------- | |
1137 | #define CCX_CMD_CLM_ENABLE BIT0 // Enable Channel Load | |
1138 | #define CCX_CMD_NHM_ENABLE BIT1 // Enable Noise Histogram | |
1139 | #define CCX_CMD_FUNCTION_ENABLE BIT8 | |
1140 | // CCX function (Channel Load/RPI/Noise Histogram). | |
1141 | #define CCX_CMD_IGNORE_CCA BIT9 | |
1142 | // Treat CCA period as IDLE time for NHM. | |
1143 | #define CCX_CMD_IGNORE_TXON BIT10 | |
1144 | // Treat TXON period as IDLE time for NHM. | |
1145 | #define CCX_CLM_RESULT_READY BIT16 | |
1146 | // 1: Indicate the result of Channel Load is ready. | |
1147 | #define CCX_NHM_RESULT_READY BIT16 | |
1148 | // 1: Indicate the result of Noise histogram is ready. | |
1149 | #define CCX_CMD_RESET 0x0 | |
1150 | // Clear all the result of CCX measurement and disable the CCX function. | |
1151 | ||
1152 | ||
1153 | //---------------------------------------------------------------------------- | |
1154 | // 8192S EFUSE | |
1155 | //---------------------------------------------------------------------------- | |
1156 | //#define HWSET_MAX_SIZE_92S 128 | |
1157 | ||
1158 | ||
1159 | //---------------------------------------------------------------------------- | |
1160 | // 8192S EEPROM/EFUSE share register definition. | |
1161 | //---------------------------------------------------------------------------- | |
1162 | ||
5f53d8ca JC |
1163 | //---------------------------------------------------------------------------- |
1164 | // 8192S EEROM and Compatible E-Fuse definition. Added by Roger, 2008.10.21. | |
1165 | //---------------------------------------------------------------------------- | |
1166 | #define RTL8190_EEPROM_ID 0x8129 | |
1167 | #define EEPROM_HPON 0x02 // LDO settings. | |
1168 | #define EEPROM_VID 0x08 // USB Vendor ID. | |
1169 | #define EEPROM_PID 0x0A // USB Product ID. | |
1170 | #define EEPROM_USB_OPTIONAL 0x0C // For optional function. | |
1171 | #define EEPROM_USB_PHY_PARA1 0x0D // For fine tune USB PHY. | |
1172 | #define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address. | |
1173 | #define EEPROM_TxPowerDiff 0x1F | |
1174 | ||
1175 | #define EEPROM_Version 0x50 | |
1176 | #define EEPROM_ChannelPlan 0x51 // Map of supported channels. | |
1177 | #define EEPROM_CustomID 0x52 | |
1178 | #define EEPROM_SubCustomID 0x53 // Reserved for customer use. | |
1179 | ||
1180 | ||
1181 | // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22. | |
5f53d8ca JC |
1182 | #define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU |
1183 | #define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index. | |
1184 | #define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM. | |
1185 | #define EEPROM_ThermalMeter 0x68 // Thermal meter default value. | |
1186 | #define EEPROM_CrystalCap 0x69 // Crystal Cap. | |
1187 | #define EEPROM_TxPowerBase 0x6a // Tx Power of serving station. | |
1188 | #define EEPROM_TSSI_A 0x6b //TSSI value of path A. | |
1189 | #define EEPROM_TSSI_B 0x6c //TSSI value of path B. | |
1190 | #define EEPROM_TxPwTkMode 0x6d //Tx Power tracking mode. | |
1191 | //#define EEPROM_Reserved 0x6e //0x6e-0x7f, reserved. | |
1192 | ||
1193 | // 2009/02/09 Cosa Add for SD3 requirement | |
1194 | #define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference | |
1195 | #define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference | |
1196 | #define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference | |
1197 | #define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel | |
1198 | #define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled | |
5f53d8ca JC |
1199 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 |
1200 | #define EEPROM_USB_Default_OPTIONAL_FUNC 0x8 | |
1201 | #define EEPROM_USB_Default_PHY_PARAM 0x0 | |
1202 | #define EEPROM_Default_TSSI 0x0 | |
1203 | #define EEPROM_Default_TxPwrTkMode 0x0 | |
1204 | #define EEPROM_Default_TxPowerDiff 0x0 | |
1205 | #define EEPROM_Default_TxPowerBase 0x0 | |
1206 | #define EEPROM_Default_ThermalMeter 0x7 | |
1207 | #define EEPROM_Default_PwDiff 0x4 | |
1208 | #define EEPROM_Default_CrystalCap 0x5 | |
1209 | #define EEPROM_Default_TxPower 0x1010 | |
1210 | #define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SU(QFPN68) | |
1211 | #define EEPROM_Default_HT2T_TxPwr 0x10 | |
1212 | #define EEPROM_USB_SN BIT0 | |
1213 | #define EEPROM_USB_REMOTE_WAKEUP BIT1 | |
1214 | #define EEPROM_USB_DEVICE_PWR BIT2 | |
1215 | #define EEPROM_EP_NUMBER (BIT3|BIT4) | |
1216 | ||
1217 | #define EEPROM_CHANNEL_PLAN_FCC 0x0 | |
1218 | #define EEPROM_CHANNEL_PLAN_IC 0x1 | |
1219 | #define EEPROM_CHANNEL_PLAN_ETSI 0x2 | |
1220 | #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 | |
1221 | #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 | |
1222 | #define EEPROM_CHANNEL_PLAN_MKK 0x5 | |
1223 | #define EEPROM_CHANNEL_PLAN_MKK1 0x6 | |
1224 | #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 | |
1225 | #define EEPROM_CHANNEL_PLAN_TELEC 0x8 | |
1226 | #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 | |
1227 | #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA | |
1228 | #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 | |
653e99e3 FS |
1229 | #define EEPROM_CID_DEFAULT 0x0 |
1230 | #define EEPROM_CID_ALPHA 0x1 | |
1231 | #define EEPROM_CID_Senao 0x3 | |
1232 | #define EEPROM_CID_CAMEO 0X8 | |
1233 | #define EEPROM_CID_SITECOM 0x9 | |
1234 | #define EEPROM_CID_COREGA 0xB | |
1235 | #define EEPROM_CID_EDIMAX_BELKIN 0xC | |
1236 | #define EEPROM_CID_SERCOMM_BELKIN 0xE | |
1237 | #define EEPROM_CID_CAMEO1 0xF | |
1238 | #define EEPROM_CID_WHQL 0xFE | |
1239 | #define EEPROM_CID_NetCore 0x5 | |
5f53d8ca | 1240 | |
5f53d8ca JC |
1241 | |
1242 | //----------------------------------------------------------------- | |
1243 | // 0x2c0 FW Command Control register definition, added by Roger, 2008.11.27. | |
1244 | //----------------------------------------------------------------- | |
1245 | #define FW_DIG_DISABLE 0xfd00cc00 | |
1246 | #define FW_DIG_ENABLE 0xfd000000 | |
1247 | #define FW_DIG_HALT 0xfd000001 | |
1248 | #define FW_DIG_RESUME 0xfd000002 | |
1249 | #define FW_HIGH_PWR_DISABLE 0xfd000008 | |
1250 | #define FW_HIGH_PWR_ENABLE 0xfd000009 | |
1251 | #define FW_TXPWR_TRACK_ENABLE 0xfd000017 | |
1252 | #define FW_TXPWR_TRACK_DISABLE 0xfd000018 | |
653e99e3 FS |
1253 | #define FW_TXPWR_TRACK_THERMAL 0xfd000019 |
1254 | #define FW_RA_INIT 0xfd000026 | |
1255 | #define FW_RA_IOT_BG_COMB 0xfd000030 | |
1256 | #define FW_RA_IOT_N_COMB 0xfd000031 | |
5f53d8ca | 1257 | #define FW_RA_REFRESH 0xfd0000a0 |
653e99e3 FS |
1258 | #define FW_RA_DISABLE 0xfd0000a4 |
1259 | #define FW_RA_ACTIVE 0xfd0000a6 | |
1260 | #define FW_RA_DISABLE_RSSI_MASK 0xfd0000ac | |
1261 | #define FW_RA_ENABLE_RSSI_MASK 0xfd0000ad | |
1262 | #define FW_RA_RESET 0xfd0000af | |
1263 | #define FW_DM_DISABLE 0xfd00aa00 | |
5f53d8ca JC |
1264 | #define FW_IQK_ENABLE 0xf0000020 |
1265 | #define FW_IQK_SUCCESS 0x0000dddd | |
1266 | #define FW_IQK_FAIL 0x0000ffff | |
1267 | #define FW_OP_FAILURE 0xffffffff | |
653e99e3 FS |
1268 | #define FW_TX_FEEDBACK_NONE 0xfb000000 |
1269 | #define FW_TX_FEEDBACK_DTM_ENABLE (FW_TX_FEEDBACK_NONE | 0x1) | |
1270 | #define FW_TX_FEEDBACK_CCX_ENABLE (FW_TX_FEEDBACK_NONE | 0x2) | |
5f53d8ca JC |
1271 | #define FW_BB_RESET_ENABLE 0xff00000d |
1272 | #define FW_BB_RESET_DISABLE 0xff00000e | |
653e99e3 FS |
1273 | #define FW_LPS_ENTER 0xfe000010 |
1274 | #define FW_LPS_LEAVE 0xfe000011 | |
1275 | #define FW_INDIRECT_READ 0xf2000000 | |
1276 | #define FW_INDIRECT_WRITE 0xf2000001 | |
1277 | #define FW_TXANT_SWITCH_ENABLE 0xfd000023 | |
1278 | #define FW_TXANT_SWITCH_DISABLE 0xfd000024 | |
5f53d8ca JC |
1279 | // |
1280 | //--------------92SU require delete or move to other place later | |
1281 | // | |
1282 | ||
1283 | ||
1284 | ||
1285 | // | |
1286 | // | |
1287 | // 2008/08/06 MH For share the same 92S source/header files, we copy some | |
1288 | // definition to pass 92SU compiler. But we must delete thm later. | |
1289 | // | |
1290 | // | |
1291 | ||
1292 | //============================================================================ | |
1293 | // 819xUsb Regsiter offset definition | |
1294 | //============================================================================ | |
1295 | ||
1296 | //2 define it temp!!! | |
1297 | #define RFPC 0x5F // Rx FIFO Packet Count | |
1298 | #define RCR_9356SEL BIT6 | |
1299 | #define TCR_LRL_OFFSET 0 | |
1300 | #define TCR_SRL_OFFSET 8 | |
1301 | #define TCR_MXDMA_OFFSET 21 | |
1302 | #define TCR_MXDMA_2048 7 | |
1303 | #define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer | |
1304 | #define RCR_MXDMA_OFFSET 8 | |
1305 | #define RCR_FIFO_OFFSET 13 | |
1306 | #define RCR_OnlyErlPkt BIT31 // Rx Early mode is performed for packet size greater than 1536 | |
1307 | #define CWR 0xDC // Contention window register | |
1308 | #define RetryCTR 0xDE // Retry Count register | |
1309 | ||
1310 | ||
1311 | // For backward compatible for 9xUSB | |
1312 | #define LED1Cfg UnusedRegister // LED1 Configuration Register | |
1313 | #define LED0Cfg UnusedRegister // LED0 Configuration Register | |
1314 | #define GPI UnusedRegister // LED0 Configuration Register | |
1315 | #define BRSR UnusedRegister // LED0 Configuration Register | |
1316 | #define CPU_GEN UnusedRegister // LED0 Configuration Register | |
1317 | #define SIFS UnusedRegister // LED0 Configuration Register | |
1318 | ||
1319 | //---------------------------------------------------------------------------- | |
1320 | // 8190 CPU General Register (offset 0x100, 4 byte) | |
1321 | //---------------------------------------------------------------------------- | |
1322 | //#define CPU_CCK_LOOPBACK 0x00030000 | |
1323 | #define CPU_GEN_SYSTEM_RESET 0x00000001 | |
1324 | //#define CPU_GEN_FIRMWARE_RESET 0x00000008 | |
1325 | //#define CPU_GEN_BOOT_RDY 0x00000010 | |
1326 | //#define CPU_GEN_FIRM_RDY 0x00000020 | |
1327 | //#define CPU_GEN_PUT_CODE_OK 0x00000080 | |
1328 | //#define CPU_GEN_BB_RST 0x00000100 | |
1329 | //#define CPU_GEN_PWR_STB_CPU 0x00000004 | |
1330 | //#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 | |
1331 | //#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 | |
1332 | ||
1333 | //---------------------------------------------------------------------------- | |
1334 | // 8192S EEROM | |
1335 | //---------------------------------------------------------------------------- | |
1336 | ||
1337 | //#define RTL8190_EEPROM_ID 0x8129 | |
1338 | //#define EEPROM_VID 0x08 | |
1339 | //#define EEPROM_PID 0x0A | |
1340 | //#define EEPROM_USB_OPTIONAL 0x0C | |
1341 | //#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 | |
1342 | // | |
1343 | //#define EEPROM_TxPowerDiff 0x1F | |
1344 | //#define EEPROM_ThermalMeter 0x20 | |
1345 | //#define EEPROM_PwDiff 0x21 //0x21 | |
1346 | //#define EEPROM_CrystalCap 0x22 //0x22 | |
1347 | // | |
1348 | //#define EEPROM_TxPwIndex_CCK 0x23 //0x23 | |
1349 | //#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 | |
1350 | #define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B | |
1351 | #define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E | |
1352 | #define EEPROM_TxPwIndex_Ver 0x27 //0x27 | |
1353 | // | |
1354 | //#define EEPROM_Default_TxPowerDiff 0x0 | |
1355 | //#define EEPROM_Default_ThermalMeter 0x7 | |
1356 | //#define EEPROM_Default_PwDiff 0x4 | |
1357 | //#define EEPROM_Default_CrystalCap 0x5 | |
1358 | //#define EEPROM_Default_TxPower 0x1010 | |
1359 | //#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID | |
1360 | //#define EEPROM_Version 0x50 // 0x50 | |
1361 | //#define EEPROM_CustomID 0x52 | |
1362 | //#define EEPROM_ChannelPlan 0x7c //0x7C | |
1363 | //#define EEPROM_IC_VER 0x7d //0x7D | |
1364 | //#define EEPROM_CRC 0x7e //0x7E~0x7F | |
1365 | // | |
1366 | // | |
1367 | //#define EEPROM_CID_DEFAULT 0x0 | |
1368 | //#define EEPROM_CID_CAMEO 0x1 | |
1369 | //#define EEPROM_CID_RUNTOP 0x2 | |
1370 | //#define EEPROM_CID_Senao 0x3 | |
1371 | //#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 | |
1372 | //#define EEPROM_CID_NetCore 0x5 | |
1373 | ||
1374 | ||
1375 | // | |
1376 | //--------------92SU require delete or move to other place later | |
1377 | // | |
1378 | ||
1379 | //============================================================ | |
1380 | // CCX Related Register | |
1381 | //============================================================ | |
1382 | #define CCX_COMMAND_REG 0x890 | |
1383 | // CCX Measurement Command Register. 4 Bytes. | |
1384 | // Bit[0]: R_CLM_En, 1=enable, 0=disable. Enable or disable "Channel Load | |
1385 | // Measurement (CLM)". | |
1386 | // Bit[1]: R_NHM_En, 1=enable, 0=disable. Enable or disalbe "Noise Histogram | |
1387 | // Measurement (NHM)". | |
1388 | // Bit[2~7]: Reserved | |
1389 | // Bit[8]: R_CCX_En: 1=enable, 0=disable. Enable or disable CCX function. | |
1390 | // Note: After clearing this bit, all the result of all NHM_Result and CLM_ | |
1391 | // Result are cleared concurrently. | |
1392 | // Bit[9]: R_Ignore_CCA: 1=enable, 0=disable. Enable means that treat CCA | |
1393 | // period as idle time for NHM. | |
1394 | // Bit[10]: R_Ignore_TXON: 1=enable, 0=disable. Enable means that treat TXON | |
1395 | // period as idle time for NHM. | |
1396 | // Bit[11~31]: Reserved. | |
1397 | #define CLM_PERIOD_REG 0x894 | |
1398 | // CCX Measurement Period Register, in unit of 4us. 2 Bytes. | |
1399 | #define NHM_PERIOD_REG 0x896 | |
1400 | // Noise Histogram Measurement Period Register, in unit of 4us. 2Bytes. | |
1401 | #define NHM_THRESHOLD0 0x898 // Noise Histogram Meashorement0 | |
1402 | #define NHM_THRESHOLD1 0x899 // Noise Histogram Meashorement1 | |
1403 | #define NHM_THRESHOLD2 0x89A // Noise Histogram Meashorement2 | |
1404 | #define NHM_THRESHOLD3 0x89B // Noise Histogram Meashorement3 | |
1405 | #define NHM_THRESHOLD4 0x89C // Noise Histogram Meashorement4 | |
1406 | #define NHM_THRESHOLD5 0x89D // Noise Histogram Meashorement5 | |
1407 | #define NHM_THRESHOLD6 0x89E // Noise Histogram Meashorement6 | |
1408 | #define CLM_RESULT_REG 0x8D0 | |
1409 | // Channel Load result register. 4 Bytes. | |
1410 | // Bit[0~15]: Total measured duration of CLM. The CCA busy fraction is caculate | |
1411 | // by CLM_RESULT_REG/CLM_PERIOD_REG. | |
1412 | // Bit[16]: Indicate the CLM result is ready. | |
1413 | // Bit[17~31]: Reserved. | |
1414 | #define NHM_RESULT_REG 0x8D4 | |
1415 | // Noise Histogram result register. 4 Bytes. | |
1416 | // Bit[0~15]: Total measured duration of NHM. If R_Ignore_CCA=1 or | |
1417 | // R_Ignore_TXON=1, this value will be less than NHM_PERIOD_REG. | |
1418 | // Bit[16]: Indicate the NHM result is ready. | |
1419 | // Bit[17~31]: Reserved. | |
1420 | #define NHM_RPI_COUNTER0 0x8D8 | |
1421 | // NHM RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. | |
1422 | #define NHM_RPI_COUNTER1 0x8D9 | |
1423 | // NHM RPI counter1, the fraction of signal stren in NHM_THRESH0, NHM_THRESH1 | |
1424 | #define NHM_RPI_COUNTER2 0x8DA | |
1425 | // NHM RPI counter2, the fraction of signal stren in NHM_THRESH2, NHM_THRESH3 | |
1426 | #define NHM_RPI_COUNTER3 0x8DB | |
1427 | // NHM RPI counter3, the fraction of signal stren in NHM_THRESH4, NHM_THRESH5 | |
1428 | #define NHM_RPI_COUNTER4 0x8DC | |
1429 | // NHM RPI counter4, the fraction of signal stren in NHM_THRESH6, NHM_THRESH7 | |
1430 | #define NHM_RPI_COUNTER5 0x8DD | |
1431 | // NHM RPI counter5, the fraction of signal stren in NHM_THRESH8, NHM_THRESH9 | |
1432 | #define NHM_RPI_COUNTER6 0x8DE | |
1433 | // NHM RPI counter6, the fraction of signal stren in NHM_THRESH10, NHM_THRESH11 | |
1434 | #define NHM_RPI_COUNTER7 0x8DF | |
1435 | // NHM RPI counter7, the fraction of signal stren in NHM_THRESH12, NHM_THRESH13 | |
1436 | ||
1437 | #define HAL_RETRY_LIMIT_INFRA 48 | |
1438 | #define HAL_RETRY_LIMIT_AP_ADHOC 7 | |
1439 | ||
1440 | // HW Readio OFF switch (GPIO BIT) | |
1441 | #define HAL_8192S_HW_GPIO_OFF_BIT BIT3 | |
1442 | #define HAL_8192S_HW_GPIO_OFF_MASK 0xF7 | |
1443 | #define HAL_8192S_HW_GPIO_WPS_BIT BIT4 | |
1444 | ||
c6813185 | 1445 | #endif |