Commit | Line | Data |
---|---|---|
5f53d8ca JC |
1 | #ifndef __INC_FIRMWARE_H |
2 | #define __INC_FIRMWARE_H | |
3 | ||
4 | ||
5 | //#define RTL8190_CPU_START_OFFSET 0x80 | |
6 | /* TODO: this definition is TBD */ | |
7 | //#define USB_HWDESC_HEADER_LEN 0 | |
8 | ||
9 | /* It should be double word alignment */ | |
10 | //#if DEV_BUS_TYPE==PCI_INTERFACE | |
11 | //#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 | |
12 | //#else | |
13 | //#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) | |
14 | //#endif | |
15 | ||
16 | //typedef enum _firmware_init_step{ | |
17 | // FW_INIT_STEP0_BOOT = 0, | |
18 | // FW_INIT_STEP1_MAIN = 1, | |
19 | // FW_INIT_STEP2_DATA = 2, | |
20 | //}firmware_init_step_e; | |
21 | ||
22 | //typedef enum _DESC_PACKET_TYPE{ | |
23 | // DESC_PACKET_TYPE_INIT = 0, | |
24 | // DESC_PACKET_TYPE_NORMAL = 1, | |
25 | //}DESC_PACKET_TYPE; | |
26 | #define RTL8192S_FW_PKT_FRAG_SIZE 0xFF00 // 64K | |
27 | ||
28 | ||
29 | #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k | |
30 | #define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size. | |
31 | #define RTL8190_CPU_START_OFFSET 0x80 | |
32 | ||
5f53d8ca | 33 | #define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) |
5f53d8ca JC |
34 | |
35 | //typedef enum _DESC_PACKET_TYPE{ | |
36 | // DESC_PACKET_TYPE_INIT = 0, | |
37 | // DESC_PACKET_TYPE_NORMAL = 1, | |
38 | //}DESC_PACKET_TYPE; | |
39 | ||
40 | // Forward declaration. | |
41 | //typedef struct _ADAPTER ADAPTER, *PADAPTER; | |
42 | #ifdef RTL8192S | |
43 | typedef enum _firmware_init_step{ | |
44 | FW_INIT_STEP0_IMEM = 0, | |
45 | FW_INIT_STEP1_MAIN = 1, | |
46 | FW_INIT_STEP2_DATA = 2, | |
47 | }firmware_init_step_e; | |
48 | #else | |
49 | typedef enum _firmware_init_step{ | |
50 | FW_INIT_STEP0_BOOT = 0, | |
51 | FW_INIT_STEP1_MAIN = 1, | |
52 | FW_INIT_STEP2_DATA = 2, | |
53 | }firmware_init_step_e; | |
54 | #endif | |
55 | ||
56 | /* due to rtl8192 firmware */ | |
57 | typedef enum _desc_packet_type_e{ | |
58 | DESC_PACKET_TYPE_INIT = 0, | |
59 | DESC_PACKET_TYPE_NORMAL = 1, | |
60 | }desc_packet_type_e; | |
61 | ||
5f53d8ca JC |
62 | typedef enum _opt_rst_type{ |
63 | OPT_SYSTEM_RESET = 0, | |
64 | OPT_FIRMWARE_RESET = 1, | |
65 | }opt_rst_type_e; | |
66 | ||
67 | /*typedef enum _FIRMWARE_STATUS{ | |
68 | FW_STATUS_0_INIT = 0, | |
69 | FW_STATUS_1_MOVE_BOOT_CODE = 1, | |
70 | FW_STATUS_2_MOVE_MAIN_CODE = 2, | |
71 | FW_STATUS_3_TURNON_CPU = 3, | |
72 | FW_STATUS_4_MOVE_DATA_CODE = 4, | |
73 | FW_STATUS_5_READY = 5, | |
74 | }FIRMWARE_STATUS; | |
75 | */ | |
76 | //-------------------------------------------------------------------------------- | |
77 | // RTL8192S Firmware related, Revised by Roger, 2008.12.18. | |
78 | //-------------------------------------------------------------------------------- | |
79 | typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required | |
80 | ||
81 | //--- long word 0 ---- | |
82 | u8 signature_0; //0x12: CE product, 0x92: IT product | |
83 | u8 signature_1; //0x87: CE product, 0x81: IT product | |
84 | u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO | |
85 | u8 chip_version; //the same value as reigster value | |
86 | u8 customer_ID_0; //customer ID low byte | |
87 | u8 customer_ID_1; //customer ID high byte | |
88 | u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R | |
89 | u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP | |
90 | ||
91 | //--- long word 1 ---- | |
92 | u8 regulatory_class_0; //regulatory class bit map 0 | |
93 | u8 regulatory_class_1; //regulatory class bit map 1 | |
94 | u8 regulatory_class_2; //regulatory class bit map 2 | |
95 | u8 regulatory_class_3; //regulatory class bit map 3 | |
96 | u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI | |
97 | u8 def_nettype; | |
98 | u8 rsvd010; | |
99 | u8 rsvd011; | |
100 | ||
101 | ||
102 | //--- long word 2 ---- | |
103 | u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK | |
104 | u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed) | |
105 | u8 rsvd020; | |
106 | u8 rsvd021; | |
107 | u8 rsvd022; | |
108 | u8 rsvd023; | |
109 | u8 rsvd024; | |
110 | u8 rsvd025; | |
111 | ||
112 | //--- long word 3 ---- | |
113 | u8 qos_en; // QoS enable | |
114 | u8 bw_40MHz_en; // 40MHz BW enable | |
115 | u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable | |
116 | u8 AMPDU_en; // 11n AMPDU enable | |
117 | u8 rate_control_offload;//FW offloads, 0: driver handles | |
118 | u8 aggregation_offload; // FW offloads, 0: driver handles | |
119 | u8 rsvd030; | |
120 | u8 rsvd031; | |
121 | ||
122 | ||
123 | //--- long word 4 ---- | |
124 | unsigned char beacon_offload; // 1. FW offloads, 0: driver handles | |
125 | unsigned char MLME_offload; // 2. FW offloads, 0: driver handles | |
126 | unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles | |
127 | unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles | |
128 | unsigned char tcp_offload; // 5. FW offloads, 0: driver handles | |
129 | unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles | |
130 | unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles | |
131 | unsigned char rsvd040; | |
132 | ||
133 | //--- long word 5 ---- | |
134 | u8 tcp_tx_frame_len_L; //tcp tx packet length low byte | |
135 | u8 tcp_tx_frame_len_H; //tcp tx packet length high byte | |
136 | u8 tcp_rx_frame_len_L; //tcp rx packet length low byte | |
137 | u8 tcp_rx_frame_len_H; //tcp rx packet length high byte | |
138 | u8 rsvd050; | |
139 | u8 rsvd051; | |
140 | u8 rsvd052; | |
141 | u8 rsvd053; | |
142 | }RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV; | |
143 | ||
144 | typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required | |
145 | ||
146 | //--- LONG WORD 0 ---- | |
147 | u16 Signature; | |
148 | u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version, | |
149 | u32 DMEMSize; //define the size of boot loader | |
150 | ||
151 | ||
152 | //--- LONG WORD 1 ---- | |
153 | u32 IMG_IMEM_SIZE; //define the size of FW in IMEM | |
154 | u32 IMG_SRAM_SIZE; //define the size of FW in SRAM | |
155 | ||
156 | //--- LONG WORD 2 ---- | |
157 | u32 FW_PRIV_SIZE; //define the size of DMEM variable | |
158 | u32 Rsvd0; | |
159 | ||
160 | //--- LONG WORD 3 ---- | |
161 | u32 Rsvd1; | |
162 | u32 Rsvd2; | |
163 | ||
164 | RT_8192S_FIRMWARE_PRIV FWPriv; | |
165 | ||
166 | }RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR; | |
167 | ||
168 | #define RT_8192S_FIRMWARE_HDR_SIZE 80 | |
169 | #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32 | |
170 | ||
171 | typedef enum _FIRMWARE_8192S_STATUS{ | |
172 | FW_STATUS_INIT = 0, | |
173 | FW_STATUS_LOAD_IMEM = 1, | |
174 | FW_STATUS_LOAD_EMEM = 2, | |
175 | FW_STATUS_LOAD_DMEM = 3, | |
176 | FW_STATUS_READY = 4, | |
177 | }FIRMWARE_8192S_STATUS; | |
178 | ||
179 | #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k | |
180 | ||
181 | typedef struct _rt_firmware{ | |
5f53d8ca JC |
182 | PRT_8192S_FIRMWARE_HDR pFwHeader; |
183 | FIRMWARE_8192S_STATUS FWStatus; | |
184 | u16 FirmwareVersion; | |
185 | u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE]; | |
186 | u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE]; | |
187 | u32 FwIMEMLen; | |
188 | u32 FwEMEMLen; | |
189 | u8 szFwTmpBuffer[164000]; | |
190 | u32 szFwTmpBufferLen; | |
191 | u16 CmdPacketFragThresold; | |
192 | }rt_firmware, *prt_firmware; | |
193 | ||
194 | //typedef struct _RT_FIRMWARE_INFO_8192SU{ | |
195 | // u8 szInfo[16]; | |
196 | //}RT_FIRMWARE_INFO_8192SU, *PRT_FIRMWARE_INFO_8192SU; | |
197 | bool FirmwareDownload92S(struct net_device *dev); | |
198 | ||
199 | #endif | |
200 |