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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rtl8192e / r819xE_phy.h
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GKH		 1#ifndef _R819XU_PHY_H
2#define _R819XU_PHY_H
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RV		 3
4/* Channel switch: the size of command tables for switch channel */
ecdfa446
GKH		 5#define MAX_PRECMD_CNT 16
6#define MAX_RFDEPENDCMD_CNT 16
7#define MAX_POSTCMD_CNT 16
8
9#ifdef RTL8190P
10#define MACPHY_Array_PGLength 21
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RV		 11#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
12#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
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GKH		 13#define RadioC_ArrayLength 246
14#define RadioD_ArrayLength 78
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RV		 15#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
16#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
17#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
18#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
19#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
20#define PHY_REGArrayLength 280
21#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
22#define PHY_REG_1T2RArrayLength 280
23#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
24#endif
25
26
27#ifdef RTL8192E
28#define MACPHY_Array_PGLength 30
29#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
30#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
31#define RadioC_ArrayLength 1
32#define RadioD_ArrayLength 1
33#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
34#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
35#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
36#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
37#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
38#define PHY_REGArrayLength 1
39#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
40#define PHY_REG_1T2RArrayLength 296
41#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
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GKH		 42#endif
43
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GKH		 44#define AGCTAB_ArrayLength 384
45#define MACPHY_ArrayLength 18
46
47#define RadioA_ArrayLength 246
48#define RadioB_ArrayLength 78
49
50
4db3d5e4 51typedef enum _SwChnlCmdID {
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GKH		 52 CmdID_End,
53 CmdID_SetTxPowerLevel,
54 CmdID_BBRegWrite10,
55 CmdID_WritePortUlong,
56 CmdID_WritePortUshort,
57 CmdID_WritePortUchar,
58 CmdID_RF_WriteReg,
4db3d5e4 59} SwChnlCmdID;
ecdfa446 60
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RV		 61/* switch channel data structure */
62typedef struct _SwChnlCmd {
63 SwChnlCmdID CmdID;
64 u32 Para1;
65 u32 Para2;
66 u32 msDelay;
67} __attribute__ ((packed)) SwChnlCmd;
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GKH		 68
69extern u32 rtl819XMACPHY_Array_PG[];
70extern u32 rtl819XPHY_REG_1T2RArray[];
71extern u32 rtl819XAGCTAB_Array[];
72extern u32 rtl819XRadioA_Array[];
73extern u32 rtl819XRadioB_Array[];
74extern u32 rtl819XRadioC_Array[];
75extern u32 rtl819XRadioD_Array[];
76
4db3d5e4 77typedef enum _HW90_BLOCK {
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GKH		 78 HW90_BLOCK_MAC = 0,
79 HW90_BLOCK_PHY0 = 1,
80 HW90_BLOCK_PHY1 = 2,
81 HW90_BLOCK_RF = 3,
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RV		 82 /* Don't ever use this. */
83 HW90_BLOCK_MAXIMUM = 4,
84} HW90_BLOCK_E, *PHW90_BLOCK_E;
85
86typedef enum _RF90_RADIO_PATH {
87 /* Radio paths */
88 RF90_PATH_A = 0,
89 RF90_PATH_B = 1,
90 RF90_PATH_C = 2,
91 RF90_PATH_D = 3,
92
93 /* Max RF number 92 support */
94 RF90_PATH_MAX
95} RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
96
97#define bMaskByte0 0xff
98#define bMaskByte1 0xff00
99#define bMaskByte2 0xff0000
100#define bMaskByte3 0xff000000
101#define bMaskHWord 0xffff0000
102#define bMaskLWord 0x0000ffff
103#define bMaskDWord 0xffffffff
104
105/*extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
106
107extern u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
108 RF90_RADIO_PATH_E eRFPath, u32 Offset);
109
110extern void rtl8192_phy_RFSerialWrite(struct net_device *dev,
111 RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
112
113extern void rtl8192_InitBBRFRegDef(struct net_device *dev);
114
115extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device *dev); */
116
117extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath);
118
119extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr,
120 u32 dwBitMask, u32 dwData);
121
122extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr,
123 u32 dwBitMask);
124
125extern void rtl8192_phy_SetRFReg(struct net_device *dev,
126 RF90_RADIO_PATH_E eRFPath, u32 RegAddr,
127 u32 BitMask, u32 Data);
128
129extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
130 RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
131
132extern void rtl8192_phy_configmac(struct net_device *dev);
133
134extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
135
136extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device *dev,
137 HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
138
139extern RT_STATUS rtl8192_BBConfig(struct net_device *dev);
140
141extern void rtl8192_phy_getTxPower(struct net_device *dev);
142
143extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
144
ecdfa446 145extern RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev);
4db3d5e4 146
ecdfa446 147extern void rtl8192_phy_updateInitGain(struct net_device* dev);
ecdfa446 148
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RV		 149extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
150 RF90_RADIO_PATH_E eRFPath);
151
152extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
153
154extern void rtl8192_SetBWMode(struct net_device *dev,
155 HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
156
ecdfa446 157extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
4db3d5e4 158
ecdfa446 159extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
4db3d5e4 160
ecdfa446
GKH		 161extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
162
4db3d5e4 163#endif /* _R819XU_PHY_H */
kernel source for telekom puls (alcatel/mediatek)