include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rtl8187se / r8180_core.c
CommitLineData
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1/*
2 This is part of rtl818x pci OpenSource driver - v 0.1
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public License)
5
6 Parts of this driver are based on the GPL part of the official
7 Realtek driver.
8
9 Parts of this driver are based on the rtl8180 driver skeleton
10 from Patric Schenke & Andres Salomon.
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
13
14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
15
16 RSSI calc function from 'The Deuce'
17
18 Some ideas borrowed from the 8139too.c driver included in linux kernel.
19
20 We (I?) want to thanks the Authors of those projecs and also the
21 Ndiswrapper's project Authors.
22
23 A big big thanks goes also to Realtek corp. for their help in my attempt to
24 add RTL8185 and RTL8225 support, and to David Young also.
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25
26 Power management interface routines.
27 Written by Mariusz Matuszek.
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28*/
29
c8d86be3 30#undef RX_DONT_PASS_UL
c8d86be3 31#undef DUMMY_RX
c8d86be3 32
5a0e3ad6 33#include <linux/slab.h>
c8d86be3 34#include <linux/syscalls.h>
742821ce 35#include <linux/eeprom_93cx6.h>
fd882783 36
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37#include "r8180_hw.h"
38#include "r8180.h"
c8d86be3 39#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
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40#include "r8180_93cx6.h" /* Card EEPROM */
41#include "r8180_wx.h"
42#include "r8180_dm.h"
43
fd9b8d6e 44#include "ieee80211/dot11d.h"
c8d86be3 45
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46static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = {
47 {
48 .vendor = PCI_VENDOR_ID_REALTEK,
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49 .device = 0x8199,
50 .subvendor = PCI_ANY_ID,
51 .subdevice = PCI_ANY_ID,
52 .driver_data = 0,
53 },
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54 {
55 .vendor = 0,
56 .device = 0,
57 .subvendor = 0,
58 .subdevice = 0,
59 .driver_data = 0,
60 }
61};
62
63
64static char* ifname = "wlan%d";
65static int hwseqnum = 0;
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66static int hwwep = 0;
67static int channels = 0x3fff;
68
69#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
70#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
71MODULE_LICENSE("GPL");
72MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
73MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
74MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards");
75
76
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77module_param(ifname, charp, S_IRUGO|S_IWUSR );
78module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
79module_param(hwwep,int, S_IRUGO|S_IWUSR);
80module_param(channels,int, S_IRUGO|S_IWUSR);
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81
82MODULE_PARM_DESC(devname," Net interface name, wlan%d=default");
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83MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
84MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
85MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
86
87
88static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
89 const struct pci_device_id *id);
90
91static void __devexit rtl8180_pci_remove(struct pci_dev *pdev);
92
93static void rtl8180_shutdown (struct pci_dev *pdev)
94{
95 struct net_device *dev = pci_get_drvdata(pdev);
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96 if (dev->netdev_ops->ndo_stop)
97 dev->netdev_ops->ndo_stop(dev);
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98 pci_disable_device(pdev);
99}
100
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101static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
102{
103 struct net_device *dev = pci_get_drvdata(pdev);
104
105 if (!netif_running(dev))
106 goto out_pci_suspend;
107
108 if (dev->netdev_ops->ndo_stop)
109 dev->netdev_ops->ndo_stop(dev);
110
111 netif_device_detach(dev);
112
113out_pci_suspend:
114 pci_save_state(pdev);
115 pci_disable_device(pdev);
116 pci_set_power_state(pdev, pci_choose_state(pdev, state));
117 return 0;
118}
119
120static int rtl8180_resume(struct pci_dev *pdev)
121{
122 struct net_device *dev = pci_get_drvdata(pdev);
123 int err;
124 u32 val;
125
126 pci_set_power_state(pdev, PCI_D0);
127
128 err = pci_enable_device(pdev);
129 if (err) {
130 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
131 dev->name);
132
133 return err;
134 }
135
136 pci_restore_state(pdev);
137
138 /*
139 * Suspend/Resume resets the PCI configuration space, so we have to
140 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
141 * from interfering with C3 CPU state. pci_restore_state won't help
142 * here since it only restores the first 64 bytes pci config header.
143 */
144 pci_read_config_dword(pdev, 0x40, &val);
145 if ((val & 0x0000ff00) != 0)
146 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
147
148 if (!netif_running(dev))
149 goto out;
150
151 if (dev->netdev_ops->ndo_open)
152 dev->netdev_ops->ndo_open(dev);
153
154 netif_device_attach(dev);
155out:
156 return 0;
157}
158
c8d86be3 159static struct pci_driver rtl8180_pci_driver = {
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160 .name = RTL8180_MODULE_NAME,
161 .id_table = rtl8180_pci_id_tbl,
162 .probe = rtl8180_pci_probe,
163 .remove = __devexit_p(rtl8180_pci_remove),
164 .suspend = rtl8180_suspend,
165 .resume = rtl8180_resume,
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166 .shutdown = rtl8180_shutdown,
167};
168
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169u8 read_nic_byte(struct net_device *dev, int x)
170{
171 return 0xff&readb((u8*)dev->mem_start +x);
172}
173
174u32 read_nic_dword(struct net_device *dev, int x)
175{
176 return readl((u8*)dev->mem_start +x);
177}
178
179u16 read_nic_word(struct net_device *dev, int x)
180{
181 return readw((u8*)dev->mem_start +x);
182}
183
184void write_nic_byte(struct net_device *dev, int x,u8 y)
185{
186 writeb(y,(u8*)dev->mem_start +x);
187 udelay(20);
188}
189
190void write_nic_dword(struct net_device *dev, int x,u32 y)
191{
192 writel(y,(u8*)dev->mem_start +x);
193 udelay(20);
194}
195
196void write_nic_word(struct net_device *dev, int x,u16 y)
197{
198 writew(y,(u8*)dev->mem_start +x);
199 udelay(20);
200}
201
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202inline void force_pci_posting(struct net_device *dev)
203{
204 read_nic_byte(dev,EPROM_CMD);
c8d86be3 205 mb();
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206}
207
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208irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs);
209void set_nic_rxring(struct net_device *dev);
210void set_nic_txring(struct net_device *dev);
211static struct net_device_stats *rtl8180_stats(struct net_device *dev);
212void rtl8180_commit(struct net_device *dev);
213void rtl8180_start_tx_beacon(struct net_device *dev);
214
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215static struct proc_dir_entry *rtl8180_proc = NULL;
216
217static int proc_get_registers(char *page, char **start,
218 off_t offset, int count,
219 int *eof, void *data)
220{
221 struct net_device *dev = data;
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222 int len = 0;
223 int i,n;
fd882783 224 int max = 0xff;
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225
226 /* This dump the current register page */
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227 for (n = 0; n <= max;) {
228 len += snprintf(page + len, count - len, "\nD: %2x > ", n);
c8d86be3 229
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230 for (i = 0; i < 16 && n <= max; i++, n++)
231 len += snprintf(page + len, count - len, "%2x ",
232 read_nic_byte(dev, n));
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233 }
234 len += snprintf(page + len, count - len,"\n");
235
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236 *eof = 1;
237 return len;
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238}
239
240int get_curr_tx_free_desc(struct net_device *dev, int priority);
241
242static int proc_get_stats_hw(char *page, char **start,
243 off_t offset, int count,
244 int *eof, void *data)
245{
c8d86be3 246 int len = 0;
c8d86be3 247
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248 *eof = 1;
249 return len;
250}
251
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252static int proc_get_stats_rx(char *page, char **start,
253 off_t offset, int count,
254 int *eof, void *data)
255{
256 struct net_device *dev = data;
257 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
258
259 int len = 0;
260
261 len += snprintf(page + len, count - len,
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262 "RX OK: %lu\n"
263 "RX Retry: %lu\n"
264 "RX CRC Error(0-500): %lu\n"
265 "RX CRC Error(500-1000): %lu\n"
266 "RX CRC Error(>1000): %lu\n"
267 "RX ICV Error: %lu\n",
268 priv->stats.rxint,
269 priv->stats.rxerr,
270 priv->stats.rxcrcerrmin,
271 priv->stats.rxcrcerrmid,
272 priv->stats.rxcrcerrmax,
273 priv->stats.rxicverr
274 );
275
276 *eof = 1;
277 return len;
278}
279
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280static int proc_get_stats_tx(char *page, char **start,
281 off_t offset, int count,
282 int *eof, void *data)
283{
284 struct net_device *dev = data;
285 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
286
287 int len = 0;
288 unsigned long totalOK;
289
290 totalOK=priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
291 len += snprintf(page + len, count - len,
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292 "TX OK: %lu\n"
293 "TX Error: %lu\n"
294 "TX Retry: %lu\n"
295 "TX beacon OK: %lu\n"
296 "TX beacon error: %lu\n",
297 totalOK,
298 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
299 priv->stats.txretry,
300 priv->stats.txbeacon,
301 priv->stats.txbeaconerr
302 );
303
304 *eof = 1;
305 return len;
306}
307
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308void rtl8180_proc_module_init(void)
309{
310 DMESG("Initializing proc filesystem");
c8d86be3 311 rtl8180_proc=create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net);
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312}
313
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314void rtl8180_proc_module_remove(void)
315{
c8d86be3 316 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
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317}
318
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319void rtl8180_proc_remove_one(struct net_device *dev)
320{
321 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
322 if (priv->dir_dev) {
323 remove_proc_entry("stats-hw", priv->dir_dev);
324 remove_proc_entry("stats-tx", priv->dir_dev);
325 remove_proc_entry("stats-rx", priv->dir_dev);
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326 remove_proc_entry("registers", priv->dir_dev);
327 remove_proc_entry(dev->name, rtl8180_proc);
328 priv->dir_dev = NULL;
329 }
330}
331
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332void rtl8180_proc_init_one(struct net_device *dev)
333{
334 struct proc_dir_entry *e;
335 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 336
be286fd2 337 priv->dir_dev = rtl8180_proc;
c8d86be3 338 if (!priv->dir_dev) {
be286fd2 339 DMESGE("Unable to initialize /proc/net/r8180/%s\n",
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340 dev->name);
341 return;
342 }
343
344 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
345 priv->dir_dev, proc_get_stats_hw, dev);
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346 if (!e) {
347 DMESGE("Unable to initialize "
be286fd2 348 "/proc/net/r8180/%s/stats-hw\n",
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349 dev->name);
350 }
351
352 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
353 priv->dir_dev, proc_get_stats_rx, dev);
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354 if (!e) {
355 DMESGE("Unable to initialize "
be286fd2 356 "/proc/net/r8180/%s/stats-rx\n",
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357 dev->name);
358 }
359
360
361 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
362 priv->dir_dev, proc_get_stats_tx, dev);
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363 if (!e) {
364 DMESGE("Unable to initialize "
be286fd2 365 "/proc/net/r8180/%s/stats-tx\n",
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366 dev->name);
367 }
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368
369 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
370 priv->dir_dev, proc_get_registers, dev);
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371 if (!e) {
372 DMESGE("Unable to initialize "
be286fd2 373 "/proc/net/r8180/%s/registers\n",
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374 dev->name);
375 }
376}
fd882783 377
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378/*
379 FIXME: check if we can use some standard already-existent
380 data type+functions in kernel
381*/
382
383short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
384 struct buffer **bufferhead)
385{
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386 struct buffer *tmp;
387
388 if(! *buffer){
389
390 *buffer = kmalloc(sizeof(struct buffer),GFP_KERNEL);
391
392 if (*buffer == NULL) {
393 DMESGE("Failed to kmalloc head of TX/RX struct");
394 return -1;
395 }
396 (*buffer)->next=*buffer;
397 (*buffer)->buf=buf;
398 (*buffer)->dma=dma;
399 if(bufferhead !=NULL)
400 (*bufferhead) = (*buffer);
401 return 0;
402 }
403 tmp=*buffer;
404
405 while(tmp->next!=(*buffer)) tmp=tmp->next;
406 if ((tmp->next= kmalloc(sizeof(struct buffer),GFP_KERNEL)) == NULL){
407 DMESGE("Failed to kmalloc TX/RX struct");
408 return -1;
409 }
410 tmp->next->buf=buf;
411 tmp->next->dma=dma;
412 tmp->next->next=*buffer;
413
414 return 0;
415}
416
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417void buffer_free(struct net_device *dev,struct buffer **buffer,int len,short
418consistent)
419{
420
421 struct buffer *tmp,*next;
422 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
423 struct pci_dev *pdev=priv->pdev;
c8d86be3 424
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425 if (!*buffer)
426 return;
c8d86be3 427
fd882783 428 tmp = *buffer;
c8d86be3 429
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430 do{
431 next=tmp->next;
432 if(consistent){
433 pci_free_consistent(pdev,len,
434 tmp->buf,tmp->dma);
435 }else{
436 pci_unmap_single(pdev, tmp->dma,
437 len,PCI_DMA_FROMDEVICE);
438 kfree(tmp->buf);
439 }
440 kfree(tmp);
441 tmp = next;
442 }
443 while(next != *buffer);
444
445 *buffer=NULL;
446}
447
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448void print_buffer(u32 *buffer, int len)
449{
450 int i;
451 u8 *buf =(u8*)buffer;
452
453 printk("ASCII BUFFER DUMP (len: %x):\n",len);
454
455 for(i=0;i<len;i++)
456 printk("%c",buf[i]);
457
458 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
459
460 for(i=0;i<len;i++)
461 printk("%02x",buf[i]);
462
463 printk("\n");
464}
465
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466int get_curr_tx_free_desc(struct net_device *dev, int priority)
467{
468 struct r8180_priv *priv = ieee80211_priv(dev);
469 u32* tail;
470 u32* head;
471 int ret;
472
473 switch (priority){
474 case MANAGE_PRIORITY:
475 head = priv->txmapringhead;
476 tail = priv->txmapringtail;
477 break;
478 case BK_PRIORITY:
479 head = priv->txbkpringhead;
480 tail = priv->txbkpringtail;
481 break;
482 case BE_PRIORITY:
483 head = priv->txbepringhead;
484 tail = priv->txbepringtail;
485 break;
486 case VI_PRIORITY:
487 head = priv->txvipringhead;
488 tail = priv->txvipringtail;
489 break;
490 case VO_PRIORITY:
491 head = priv->txvopringhead;
492 tail = priv->txvopringtail;
493 break;
494 case HI_PRIORITY:
495 head = priv->txhpringhead;
496 tail = priv->txhpringtail;
497 break;
498 default:
499 return -1;
500 }
501
fd882783 502 if (head <= tail)
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503 ret = priv->txringcount - (tail - head)/8;
504 else
505 ret = (head - tail)/8;
506
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507 if (ret > priv->txringcount)
508 DMESG("BUG");
509
c8d86be3 510 return ret;
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511}
512
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513short check_nic_enought_desc(struct net_device *dev, int priority)
514{
515 struct r8180_priv *priv = ieee80211_priv(dev);
516 struct ieee80211_device *ieee = netdev_priv(dev);
c8d86be3 517 int requiredbyte, required;
fd882783 518
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519 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
520
fd882783 521 if (ieee->current_network.QoS_Enable)
c8d86be3 522 requiredbyte += 2;
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523
524 required = requiredbyte / (priv->txbuffsize-4);
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525
526 if (requiredbyte % priv->txbuffsize)
527 required++;
528
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529 /* for now we keep two free descriptor as a safety boundary
530 * between the tail and the head
531 */
532
533 return (required+2 < get_curr_tx_free_desc(dev,priority));
534}
535
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536void fix_tx_fifo(struct net_device *dev)
537{
538 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
539 u32 *tmp;
540 int i;
ff954853 541
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542 for (tmp=priv->txmapring, i=0;
543 i < priv->txringcount;
544 tmp+=8, i++){
545 *tmp = *tmp &~ (1<<31);
546 }
547
548 for (tmp=priv->txbkpring, i=0;
549 i < priv->txringcount;
550 tmp+=8, i++) {
551 *tmp = *tmp &~ (1<<31);
552 }
553
554 for (tmp=priv->txbepring, i=0;
555 i < priv->txringcount;
556 tmp+=8, i++){
557 *tmp = *tmp &~ (1<<31);
558 }
559 for (tmp=priv->txvipring, i=0;
560 i < priv->txringcount;
561 tmp+=8, i++) {
562 *tmp = *tmp &~ (1<<31);
563 }
564
565 for (tmp=priv->txvopring, i=0;
566 i < priv->txringcount;
567 tmp+=8, i++){
568 *tmp = *tmp &~ (1<<31);
569 }
570
571 for (tmp=priv->txhpring, i=0;
572 i < priv->txringcount;
573 tmp+=8,i++){
574 *tmp = *tmp &~ (1<<31);
575 }
576
577 for (tmp=priv->txbeaconring, i=0;
578 i < priv->txbeaconcount;
579 tmp+=8, i++){
580 *tmp = *tmp &~ (1<<31);
581 }
ff954853 582
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583 priv->txmapringtail = priv->txmapring;
584 priv->txmapringhead = priv->txmapring;
585 priv->txmapbufstail = priv->txmapbufs;
586
587 priv->txbkpringtail = priv->txbkpring;
588 priv->txbkpringhead = priv->txbkpring;
589 priv->txbkpbufstail = priv->txbkpbufs;
590
591 priv->txbepringtail = priv->txbepring;
592 priv->txbepringhead = priv->txbepring;
593 priv->txbepbufstail = priv->txbepbufs;
594
595 priv->txvipringtail = priv->txvipring;
596 priv->txvipringhead = priv->txvipring;
597 priv->txvipbufstail = priv->txvipbufs;
598
599 priv->txvopringtail = priv->txvopring;
600 priv->txvopringhead = priv->txvopring;
601 priv->txvopbufstail = priv->txvopbufs;
602
603 priv->txhpringtail = priv->txhpring;
604 priv->txhpringhead = priv->txhpring;
605 priv->txhpbufstail = priv->txhpbufs;
606
607 priv->txbeaconringtail = priv->txbeaconring;
608 priv->txbeaconbufstail = priv->txbeaconbufs;
609 set_nic_txring(dev);
610
611 ieee80211_reset_queue(priv->ieee80211);
612 priv->ack_tx_to_ieee = 0;
613}
614
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615void fix_rx_fifo(struct net_device *dev)
616{
617 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
618 u32 *tmp;
619 struct buffer *rxbuf;
620 u8 rx_desc_size;
621
c8d86be3 622 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 623
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624 for (tmp=priv->rxring, rxbuf=priv->rxbufferhead;
625 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
626 tmp+=rx_desc_size,rxbuf=rxbuf->next){
627 *(tmp+2) = rxbuf->dma;
628 *tmp=*tmp &~ 0xfff;
629 *tmp=*tmp | priv->rxbuffersize;
630 *tmp |= (1<<31);
631 }
632
c8d86be3
GKH
633 priv->rxringtail=priv->rxring;
634 priv->rxbuffer=priv->rxbufferhead;
635 priv->rx_skb_complete=1;
636 set_nic_rxring(dev);
637}
638
c8d86be3 639unsigned char QUALITY_MAP[] = {
fd882783
BZ
640 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61,
641 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c,
642 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f,
643 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29,
644 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
645 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20,
646 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e,
647 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19,
648 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f,
649 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00
c8d86be3
GKH
650};
651
652unsigned char STRENGTH_MAP[] = {
fd882783
BZ
653 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
654 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
655 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
656 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
657 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
658 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
659 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
660 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
661 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
662 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
c8d86be3
GKH
663};
664
fd882783
BZ
665void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual)
666{
c8d86be3
GKH
667 u32 temp;
668 u32 temp2;
c8d86be3
GKH
669 u32 q;
670 u32 orig_qual;
671 u8 _rssi;
672
673 q = *qual;
674 orig_qual = *qual;
675 _rssi = 0; // avoid gcc complains..
676
677 if (q <= 0x4e) {
678 temp = QUALITY_MAP[q];
679 } else {
680 if( q & 0x80 ) {
681 temp = 0x32;
682 } else {
683 temp = 1;
684 }
685 }
686
687 *qual = temp;
688 temp2 = *rssi;
689
c8d86be3
GKH
690 if ( _rssi < 0x64 ){
691 if ( _rssi == 0 ) {
692 *rssi = 1;
693 }
694 } else {
695 *rssi = 0x64;
696 }
697
698 return;
699}
700
c8d86be3
GKH
701void rtl8180_irq_enable(struct net_device *dev)
702{
703 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 704
c8d86be3 705 priv->irq_enabled = 1;
c8d86be3
GKH
706 write_nic_word(dev,INTA_MASK, priv->irq_mask);
707}
708
c8d86be3
GKH
709void rtl8180_irq_disable(struct net_device *dev)
710{
711 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
712
c8d86be3 713 write_nic_dword(dev,IMR,0);
c8d86be3
GKH
714 force_pci_posting(dev);
715 priv->irq_enabled = 0;
716}
717
c8d86be3
GKH
718void rtl8180_set_mode(struct net_device *dev,int mode)
719{
720 u8 ecmd;
fd882783 721
c8d86be3
GKH
722 ecmd=read_nic_byte(dev, EPROM_CMD);
723 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
724 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
725 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
726 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
727 write_nic_byte(dev, EPROM_CMD, ecmd);
728}
729
730void rtl8180_adapter_start(struct net_device *dev);
731void rtl8180_beacon_tx_enable(struct net_device *dev);
732
733void rtl8180_update_msr(struct net_device *dev)
734{
735 struct r8180_priv *priv = ieee80211_priv(dev);
736 u8 msr;
737 u32 rxconf;
738
739 msr = read_nic_byte(dev, MSR);
740 msr &= ~ MSR_LINK_MASK;
741
742 rxconf=read_nic_dword(dev,RX_CONF);
743
744 if(priv->ieee80211->state == IEEE80211_LINKED)
745 {
746 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
747 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
748 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
749 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
750 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
751 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
752 else
753 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
754 rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
755
756 }else {
757 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
758 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
759 }
760
761 write_nic_byte(dev, MSR, msr);
762 write_nic_dword(dev, RX_CONF, rxconf);
c8d86be3
GKH
763}
764
c8d86be3
GKH
765void rtl8180_set_chan(struct net_device *dev,short ch)
766{
767 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
768
fd882783 769 if ((ch > 14) || (ch < 1)) {
d599edca 770 printk("In %s: Invalid chnanel %d\n", __func__, ch);
c8d86be3
GKH
771 return;
772 }
773
774 priv->chan=ch;
c8d86be3 775 priv->rf_set_chan(dev,priv->chan);
c8d86be3
GKH
776}
777
c8d86be3
GKH
778void rtl8180_rx_enable(struct net_device *dev)
779{
780 u8 cmd;
781 u32 rxconf;
782 /* for now we accept data, management & ctl frame*/
783 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
784
785 rxconf=read_nic_dword(dev,RX_CONF);
786 rxconf = rxconf &~ MAC_FILTER_MASK;
787 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
788 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
789 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
790 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
fd882783
BZ
791 if (dev->flags & IFF_PROMISC)
792 DMESG("NIC in promisc mode");
c8d86be3
GKH
793
794 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
795 dev->flags & IFF_PROMISC){
796 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
797 }else{
798 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
c8d86be3
GKH
799 }
800
c8d86be3
GKH
801 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
802 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
803 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
804 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
805 }
806
807 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
808 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
809
fd882783
BZ
810 rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK;
811 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT);
c8d86be3
GKH
812
813 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
814 rxconf = rxconf &~ MAX_RX_DMA_MASK;
815 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
816
fd882783 817 rxconf = rxconf | RCR_ONLYERLPKT;
c8d86be3
GKH
818
819 rxconf = rxconf &~ RCR_CS_MASK;
fd882783 820
c8d86be3
GKH
821 write_nic_dword(dev, RX_CONF, rxconf);
822
823 fix_rx_fifo(dev);
824
c8d86be3
GKH
825 cmd=read_nic_byte(dev,CMD);
826 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
c8d86be3
GKH
827}
828
c8d86be3
GKH
829void set_nic_txring(struct net_device *dev)
830{
831 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
832
833 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
c8d86be3 834 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
c8d86be3 835 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
c8d86be3 836 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
c8d86be3 837 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
c8d86be3 838 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
c8d86be3
GKH
839 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
840}
841
c8d86be3
GKH
842void rtl8180_conttx_enable(struct net_device *dev)
843{
844 u32 txconf;
fd882783 845
c8d86be3
GKH
846 txconf = read_nic_dword(dev,TX_CONF);
847 txconf = txconf &~ TX_LOOPBACK_MASK;
848 txconf = txconf | (TX_LOOPBACK_CONTINUE <<TX_LOOPBACK_SHIFT);
849 write_nic_dword(dev,TX_CONF,txconf);
850}
851
c8d86be3
GKH
852void rtl8180_conttx_disable(struct net_device *dev)
853{
854 u32 txconf;
fd882783 855
c8d86be3
GKH
856 txconf = read_nic_dword(dev,TX_CONF);
857 txconf = txconf &~ TX_LOOPBACK_MASK;
858 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
859 write_nic_dword(dev,TX_CONF,txconf);
860}
861
c8d86be3
GKH
862void rtl8180_tx_enable(struct net_device *dev)
863{
864 u8 cmd;
865 u8 tx_agc_ctl;
866 u8 byte;
867 u32 txconf;
868 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 869
fd882783 870 txconf = read_nic_dword(dev, TX_CONF);
c8d86be3 871
d44eb889
LF
872 byte = read_nic_byte(dev, CW_CONF);
873 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
874 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
875 write_nic_byte(dev, CW_CONF, byte);
c8d86be3 876
d44eb889
LF
877 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
878 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
879 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
880 tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT);
881 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
882 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
883
884 txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
c8d86be3
GKH
885
886 txconf = txconf &~ TX_LOOPBACK_MASK;
887 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
888 txconf = txconf &~ TCR_DPRETRY_MASK;
889 txconf = txconf &~ TCR_RTSRETRY_MASK;
890 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
891 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
892 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
893
d44eb889
LF
894 if (priv->hw_plcp_len)
895 txconf = txconf & ~TCR_PLCP_LEN;
896 else
897 txconf = txconf | TCR_PLCP_LEN;
fd882783 898
c8d86be3
GKH
899 txconf = txconf &~ TCR_MXDMA_MASK;
900 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
901 txconf = txconf | TCR_CWMIN;
902 txconf = txconf | TCR_DISCW;
903
fd882783 904 txconf = txconf | (1 << TX_NOICV_SHIFT);
c8d86be3
GKH
905
906 write_nic_dword(dev,TX_CONF,txconf);
907
c8d86be3
GKH
908 fix_tx_fifo(dev);
909
c8d86be3
GKH
910 cmd=read_nic_byte(dev,CMD);
911 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
912
c8d86be3 913 write_nic_dword(dev,TX_CONF,txconf);
c8d86be3
GKH
914}
915
c8d86be3
GKH
916void rtl8180_beacon_tx_enable(struct net_device *dev)
917{
918 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
919
920 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
921 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
922 write_nic_byte(dev,TPPollStop, priv->dma_poll_mask);
c8d86be3
GKH
923 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
924}
925
c8d86be3
GKH
926void rtl8180_beacon_tx_disable(struct net_device *dev)
927{
928 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
929
930 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
931 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
932 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH
933 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
934
935}
936
c8d86be3
GKH
937void rtl8180_rtx_disable(struct net_device *dev)
938{
939 u8 cmd;
940 struct r8180_priv *priv = ieee80211_priv(dev);
941
942 cmd=read_nic_byte(dev,CMD);
943 write_nic_byte(dev, CMD, cmd &~ \
944 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
945 force_pci_posting(dev);
946 mdelay(10);
c8d86be3
GKH
947
948 if(!priv->rx_skb_complete)
949 dev_kfree_skb_any(priv->rx_skb);
950}
951
c8d86be3
GKH
952short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
953 int addr)
954{
955 int i;
956 u32 *desc;
957 u32 *tmp;
958 dma_addr_t dma_desc, dma_tmp;
959 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
960 struct pci_dev *pdev = priv->pdev;
961 void *buf;
962
963 if((bufsize & 0xfff) != bufsize) {
964 DMESGE ("TX buffer allocation too large");
965 return 0;
966 }
967 desc = (u32*)pci_alloc_consistent(pdev,
968 sizeof(u32)*8*count+256, &dma_desc);
fd882783
BZ
969 if (desc == NULL)
970 return -1;
c8d86be3 971
fd882783 972 if (dma_desc & 0xff)
c8d86be3
GKH
973 /*
974 * descriptor's buffer must be 256 byte aligned
975 * we shouldn't be here, since we set DMA mask !
976 */
be286fd2 977 WARN(1, "DMA buffer is not aligned\n");
fd882783
BZ
978
979 tmp = desc;
980
981 for (i = 0; i < count; i++) {
982 buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp);
983 if (buf == NULL)
984 return -ENOMEM;
c8d86be3
GKH
985
986 switch(addr) {
c8d86be3
GKH
987 case TX_MANAGEPRIORITY_RING_ADDR:
988 if(-1 == buffer_add(&(priv->txmapbufs),buf,dma_tmp,NULL)){
989 DMESGE("Unable to allocate mem for buffer NP");
990 return -ENOMEM;
991 }
992 break;
c8d86be3
GKH
993 case TX_BKPRIORITY_RING_ADDR:
994 if(-1 == buffer_add(&(priv->txbkpbufs),buf,dma_tmp,NULL)){
995 DMESGE("Unable to allocate mem for buffer LP");
996 return -ENOMEM;
997 }
998 break;
999 case TX_BEPRIORITY_RING_ADDR:
1000 if(-1 == buffer_add(&(priv->txbepbufs),buf,dma_tmp,NULL)){
1001 DMESGE("Unable to allocate mem for buffer NP");
1002 return -ENOMEM;
1003 }
1004 break;
c8d86be3
GKH
1005 case TX_VIPRIORITY_RING_ADDR:
1006 if(-1 == buffer_add(&(priv->txvipbufs),buf,dma_tmp,NULL)){
1007 DMESGE("Unable to allocate mem for buffer LP");
1008 return -ENOMEM;
1009 }
1010 break;
1011 case TX_VOPRIORITY_RING_ADDR:
1012 if(-1 == buffer_add(&(priv->txvopbufs),buf,dma_tmp,NULL)){
1013 DMESGE("Unable to allocate mem for buffer NP");
1014 return -ENOMEM;
1015 }
1016 break;
c8d86be3
GKH
1017 case TX_HIGHPRIORITY_RING_ADDR:
1018 if(-1 == buffer_add(&(priv->txhpbufs),buf,dma_tmp,NULL)){
1019 DMESGE("Unable to allocate mem for buffer HP");
1020 return -ENOMEM;
1021 }
1022 break;
1023 case TX_BEACON_RING_ADDR:
1024 if(-1 == buffer_add(&(priv->txbeaconbufs),buf,dma_tmp,NULL)){
1025 DMESGE("Unable to allocate mem for buffer BP");
1026 return -ENOMEM;
1027 }
1028 break;
1029 }
1030 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1031 *(tmp+2) = (u32)dma_tmp;
1032 *(tmp+3) = bufsize;
1033
1034 if(i+1<count)
1035 *(tmp+4) = (u32)dma_desc+((i+1)*8*4);
1036 else
1037 *(tmp+4) = (u32)dma_desc;
1038
1039 tmp=tmp+8;
1040 }
1041
1042 switch(addr) {
1043 case TX_MANAGEPRIORITY_RING_ADDR:
1044 priv->txmapringdma=dma_desc;
1045 priv->txmapring=desc;
1046 break;
c8d86be3
GKH
1047 case TX_BKPRIORITY_RING_ADDR:
1048 priv->txbkpringdma=dma_desc;
1049 priv->txbkpring=desc;
1050 break;
c8d86be3
GKH
1051 case TX_BEPRIORITY_RING_ADDR:
1052 priv->txbepringdma=dma_desc;
1053 priv->txbepring=desc;
1054 break;
c8d86be3
GKH
1055 case TX_VIPRIORITY_RING_ADDR:
1056 priv->txvipringdma=dma_desc;
1057 priv->txvipring=desc;
1058 break;
c8d86be3
GKH
1059 case TX_VOPRIORITY_RING_ADDR:
1060 priv->txvopringdma=dma_desc;
1061 priv->txvopring=desc;
1062 break;
c8d86be3
GKH
1063 case TX_HIGHPRIORITY_RING_ADDR:
1064 priv->txhpringdma=dma_desc;
1065 priv->txhpring=desc;
1066 break;
c8d86be3
GKH
1067 case TX_BEACON_RING_ADDR:
1068 priv->txbeaconringdma=dma_desc;
1069 priv->txbeaconring=desc;
1070 break;
1071
1072 }
1073
c8d86be3
GKH
1074 return 0;
1075}
1076
c8d86be3
GKH
1077void free_tx_desc_rings(struct net_device *dev)
1078{
c8d86be3
GKH
1079 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1080 struct pci_dev *pdev=priv->pdev;
1081 int count = priv->txringcount;
1082
1083 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1084 priv->txmapring, priv->txmapringdma);
1085 buffer_free(dev,&(priv->txmapbufs),priv->txbuffsize,1);
1086
1087 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1088 priv->txbkpring, priv->txbkpringdma);
1089 buffer_free(dev,&(priv->txbkpbufs),priv->txbuffsize,1);
1090
1091 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1092 priv->txbepring, priv->txbepringdma);
1093 buffer_free(dev,&(priv->txbepbufs),priv->txbuffsize,1);
1094
1095 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1096 priv->txvipring, priv->txvipringdma);
1097 buffer_free(dev,&(priv->txvipbufs),priv->txbuffsize,1);
1098
1099 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1100 priv->txvopring, priv->txvopringdma);
1101 buffer_free(dev,&(priv->txvopbufs),priv->txbuffsize,1);
1102
1103 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1104 priv->txhpring, priv->txhpringdma);
1105 buffer_free(dev,&(priv->txhpbufs),priv->txbuffsize,1);
1106
1107 count = priv->txbeaconcount;
1108 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1109 priv->txbeaconring, priv->txbeaconringdma);
1110 buffer_free(dev,&(priv->txbeaconbufs),priv->txbuffsize,1);
1111}
1112
c8d86be3
GKH
1113void free_rx_desc_ring(struct net_device *dev)
1114{
1115 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1116 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH
1117 int count = priv->rxringcount;
1118
c8d86be3
GKH
1119 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1120 priv->rxring, priv->rxringdma);
c8d86be3
GKH
1121
1122 buffer_free(dev,&(priv->rxbuffer),priv->rxbuffersize,0);
1123}
1124
c8d86be3
GKH
1125short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
1126{
1127 int i;
1128 u32 *desc;
1129 u32 *tmp;
1130 dma_addr_t dma_desc,dma_tmp;
1131 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1132 struct pci_dev *pdev=priv->pdev;
1133 void *buf;
1134 u8 rx_desc_size;
1135
c8d86be3 1136 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3
GKH
1137
1138 if((bufsize & 0xfff) != bufsize){
1139 DMESGE ("RX buffer allocation too large");
1140 return -1;
1141 }
1142
1143 desc = (u32*)pci_alloc_consistent(pdev,sizeof(u32)*rx_desc_size*count+256,
1144 &dma_desc);
1145
fd882783 1146 if (dma_desc & 0xff)
c8d86be3
GKH
1147 /*
1148 * descriptor's buffer must be 256 byte aligned
1149 * should never happen since we specify the DMA mask
1150 */
be286fd2 1151 WARN(1, "DMA buffer is not aligned\n");
c8d86be3
GKH
1152
1153 priv->rxring=desc;
1154 priv->rxringdma=dma_desc;
1155 tmp=desc;
1156
fd882783 1157 for (i = 0; i < count; i++) {
c8d86be3
GKH
1158 if ((buf= kmalloc(bufsize * sizeof(u8),GFP_ATOMIC)) == NULL){
1159 DMESGE("Failed to kmalloc RX buffer");
1160 return -1;
1161 }
1162
1163 dma_tmp = pci_map_single(pdev,buf,bufsize * sizeof(u8),
1164 PCI_DMA_FROMDEVICE);
1165
c8d86be3
GKH
1166 if(-1 == buffer_add(&(priv->rxbuffer), buf,dma_tmp,
1167 &(priv->rxbufferhead))){
1168 DMESGE("Unable to allocate mem RX buf");
1169 return -1;
1170 }
1171 *tmp = 0; //zero pads the header of the descriptor
1172 *tmp = *tmp |( bufsize&0xfff);
1173 *(tmp+2) = (u32)dma_tmp;
1174 *tmp = *tmp |(1<<31); // descriptor void, owned by the NIC
1175
c8d86be3
GKH
1176 tmp=tmp+rx_desc_size;
1177 }
1178
1179 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor
1180
c8d86be3
GKH
1181 return 0;
1182}
1183
1184
1185void set_nic_rxring(struct net_device *dev)
1186{
1187 u8 pgreg;
1188 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1189
c8d86be3
GKH
1190 pgreg=read_nic_byte(dev, PGSELECT);
1191 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
1192
c8d86be3
GKH
1193 write_nic_dword(dev, RXRING_ADDR,priv->rxringdma);
1194}
1195
c8d86be3
GKH
1196void rtl8180_reset(struct net_device *dev)
1197{
c8d86be3
GKH
1198 u8 cr;
1199
c8d86be3
GKH
1200 rtl8180_irq_disable(dev);
1201
1202 cr=read_nic_byte(dev,CMD);
1203 cr = cr & 2;
1204 cr = cr | (1<<CMD_RST_SHIFT);
1205 write_nic_byte(dev,CMD,cr);
1206
1207 force_pci_posting(dev);
1208
1209 mdelay(200);
1210
1211 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1212 DMESGW("Card reset timeout!");
1213 else
1214 DMESG("Card successfully reset");
1215
c8d86be3
GKH
1216 rtl8180_set_mode(dev,EPROM_CMD_LOAD);
1217 force_pci_posting(dev);
1218 mdelay(200);
c8d86be3
GKH
1219}
1220
1221inline u16 ieeerate2rtlrate(int rate)
1222{
1223 switch(rate){
1224 case 10:
fd882783 1225 return 0;
c8d86be3 1226 case 20:
fd882783 1227 return 1;
c8d86be3 1228 case 55:
fd882783 1229 return 2;
c8d86be3 1230 case 110:
fd882783 1231 return 3;
c8d86be3 1232 case 60:
fd882783 1233 return 4;
c8d86be3 1234 case 90:
fd882783 1235 return 5;
c8d86be3 1236 case 120:
fd882783 1237 return 6;
c8d86be3 1238 case 180:
fd882783 1239 return 7;
c8d86be3 1240 case 240:
fd882783 1241 return 8;
c8d86be3 1242 case 360:
fd882783 1243 return 9;
c8d86be3 1244 case 480:
fd882783 1245 return 10;
c8d86be3 1246 case 540:
fd882783 1247 return 11;
c8d86be3 1248 default:
fd882783 1249 return 3;
c8d86be3
GKH
1250 }
1251}
1252
1253static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540,720};
fd882783 1254
c8d86be3
GKH
1255inline u16 rtl8180_rate2rate(short rate)
1256{
fd882783
BZ
1257 if (rate > 12)
1258 return 10;
c8d86be3
GKH
1259 return rtl_rate[rate];
1260}
fd882783 1261
c8d86be3
GKH
1262inline u8 rtl8180_IsWirelessBMode(u16 rate)
1263{
1264 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
1265 return 1;
fd882783
BZ
1266 else
1267 return 0;
c8d86be3 1268}
fd882783 1269
c8d86be3 1270u16 N_DBPSOfRate(u16 DataRate);
fd882783
BZ
1271
1272u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame,
1273 u8 bShortPreamble)
c8d86be3
GKH
1274{
1275 u16 FrameTime;
1276 u16 N_DBPS;
1277 u16 Ceiling;
1278
fd882783
BZ
1279 if (rtl8180_IsWirelessBMode(DataRate)) {
1280 if (bManagementFrame || !bShortPreamble || DataRate == 10)
1281 /* long preamble */
c8d86be3 1282 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
c8d86be3 1283 else
fd882783 1284 /* short preamble */
c8d86be3 1285 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
fd882783
BZ
1286
1287 if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */
1288 FrameTime++;
1289 } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */
c8d86be3
GKH
1290 N_DBPS = N_DBPSOfRate(DataRate);
1291 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
1292 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
1293 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
1294 }
1295 return FrameTime;
1296}
fd882783 1297
c8d86be3
GKH
1298u16 N_DBPSOfRate(u16 DataRate)
1299{
1300 u16 N_DBPS = 24;
1301
fd882783
BZ
1302 switch (DataRate) {
1303 case 60:
1304 N_DBPS = 24;
1305 break;
1306 case 90:
1307 N_DBPS = 36;
1308 break;
1309 case 120:
1310 N_DBPS = 48;
1311 break;
1312 case 180:
1313 N_DBPS = 72;
1314 break;
1315 case 240:
1316 N_DBPS = 96;
1317 break;
1318 case 360:
1319 N_DBPS = 144;
1320 break;
1321 case 480:
1322 N_DBPS = 192;
1323 break;
1324 case 540:
1325 N_DBPS = 216;
1326 break;
1327 default:
1328 break;
1329 }
c8d86be3 1330
fd882783 1331 return N_DBPS;
c8d86be3
GKH
1332}
1333
c8d86be3
GKH
1334//
1335// Description:
1336// For Netgear case, they want good-looking singal strength.
c8d86be3 1337//
fd882783 1338long NetgearSignalStrengthTranslate(long LastSS, long CurrSS)
c8d86be3
GKH
1339{
1340 long RetSS;
1341
1342 // Step 1. Scale mapping.
fd882783 1343 if (CurrSS >= 71 && CurrSS <= 100)
c8d86be3 1344 RetSS = 90 + ((CurrSS - 70) / 3);
fd882783 1345 else if (CurrSS >= 41 && CurrSS <= 70)
c8d86be3 1346 RetSS = 78 + ((CurrSS - 40) / 3);
fd882783 1347 else if (CurrSS >= 31 && CurrSS <= 40)
c8d86be3 1348 RetSS = 66 + (CurrSS - 30);
fd882783 1349 else if (CurrSS >= 21 && CurrSS <= 30)
c8d86be3 1350 RetSS = 54 + (CurrSS - 20);
fd882783 1351 else if (CurrSS >= 5 && CurrSS <= 20)
c8d86be3 1352 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
fd882783 1353 else if (CurrSS == 4)
c8d86be3 1354 RetSS = 36;
fd882783 1355 else if (CurrSS == 3)
c8d86be3 1356 RetSS = 27;
fd882783 1357 else if (CurrSS == 2)
c8d86be3 1358 RetSS = 18;
fd882783 1359 else if (CurrSS == 1)
c8d86be3 1360 RetSS = 9;
c8d86be3 1361 else
c8d86be3 1362 RetSS = CurrSS;
c8d86be3
GKH
1363
1364 // Step 2. Smoothing.
1365 if(LastSS > 0)
c8d86be3 1366 RetSS = ((LastSS * 5) + (RetSS)+ 5) / 6;
c8d86be3
GKH
1367
1368 return RetSS;
1369}
fd882783 1370
c8d86be3
GKH
1371//
1372// Description:
1373// Translate 0-100 signal strength index into dBm.
1374//
fd882783 1375long TranslateToDbm8185(u8 SignalStrengthIndex)
c8d86be3 1376{
fd882783 1377 long SignalPower;
c8d86be3
GKH
1378
1379 // Translate to dBm (x=0.5y-95).
1380 SignalPower = (long)((SignalStrengthIndex + 1) >> 1);
1381 SignalPower -= 95;
1382
1383 return SignalPower;
1384}
fd882783 1385
c8d86be3
GKH
1386//
1387// Description:
1388// Perform signal smoothing for dynamic mechanism.
1389// This is different with PerformSignalSmoothing8185 in smoothing fomula.
1390// No dramatic adjustion is apply because dynamic mechanism need some degree
1391// of correctness. Ported from 8187B.
c8d86be3 1392//
fd882783
BZ
1393void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv,
1394 bool bCckRate)
c8d86be3 1395{
c8d86be3
GKH
1396 // Determin the current packet is CCK rate.
1397 priv->bCurCCKPkt = bCckRate;
1398
fd882783 1399 if (priv->UndecoratedSmoothedSS >= 0)
c8d86be3 1400 priv->UndecoratedSmoothedSS = ( (priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10) ) / 6;
c8d86be3 1401 else
c8d86be3 1402 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10;
c8d86be3
GKH
1403
1404 priv->UndercorateSmoothedRxPower = ( (priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower* 11)) / 60;
1405
fd882783 1406 if (bCckRate)
c8d86be3 1407 priv->CurCCKRSSI = priv->RSSI;
c8d86be3 1408 else
c8d86be3 1409 priv->CurCCKRSSI = 0;
c8d86be3
GKH
1410}
1411
c8d86be3
GKH
1412
1413/* This is rough RX isr handling routine*/
1414void rtl8180_rx(struct net_device *dev)
1415{
1416 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1417 struct sk_buff *tmp_skb;
c8d86be3
GKH
1418 short first,last;
1419 u32 len;
1420 int lastlen;
1421 unsigned char quality, signal;
1422 u8 rate;
c8d86be3
GKH
1423 u32 *tmp,*tmp2;
1424 u8 rx_desc_size;
1425 u8 padding;
c8d86be3
GKH
1426 char rxpower = 0;
1427 u32 RXAGC = 0;
1428 long RxAGC_dBm = 0;
1429 u8 LNA=0, BB=0;
1430 u8 LNA_gain[4]={02, 17, 29, 39};
1431 u8 Antenna = 0;
0604384d 1432 struct ieee80211_hdr_4addr *hdr;
c8d86be3
GKH
1433 u16 fc,type;
1434 u8 bHwError = 0,bCRC = 0,bICV = 0;
c8d86be3
GKH
1435 bool bCckRate = false;
1436 u8 RSSI = 0;
fd882783 1437 long SignalStrengthIndex = 0;
c8d86be3
GKH
1438 struct ieee80211_rx_stats stats = {
1439 .signal = 0,
1440 .noise = -98,
1441 .rate = 0,
c8d86be3
GKH
1442 .freq = IEEE80211_24GHZ_BAND,
1443 };
1444
c8d86be3
GKH
1445 stats.nic_type = NIC_8185B;
1446 rx_desc_size = 8;
1447
c8d86be3 1448 if ((*(priv->rxringtail)) & (1<<31)) {
c8d86be3
GKH
1449 /* we have got an RX int, but the descriptor
1450 * we are pointing is empty*/
1451
1452 priv->stats.rxnodata++;
1453 priv->ieee80211->stats.rx_errors++;
1454
c8d86be3
GKH
1455 tmp2 = NULL;
1456 tmp = priv->rxringtail;
1457 do{
1458 if(tmp == priv->rxring)
c8d86be3
GKH
1459 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size;
1460 else
1461 tmp -= rx_desc_size;
1462
1463 if(! (*tmp & (1<<31)))
1464 tmp2 = tmp;
1465 }while(tmp != priv->rxring);
1466
1467 if(tmp2) priv->rxringtail = tmp2;
c8d86be3
GKH
1468 }
1469
1470 /* while there are filled descriptors */
1471 while(!(*(priv->rxringtail) & (1<<31))){
1472 if(*(priv->rxringtail) & (1<<26))
1473 DMESGW("RX buffer overflow");
1474 if(*(priv->rxringtail) & (1<<12))
1475 priv->stats.rxicverr++;
1476
1477 if(*(priv->rxringtail) & (1<<27)){
1478 priv->stats.rxdmafail++;
1479 //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail);
1480 goto drop;
1481 }
1482
1483 pci_dma_sync_single_for_cpu(priv->pdev,
1484 priv->rxbuffer->dma,
1485 priv->rxbuffersize * \
1486 sizeof(u8),
1487 PCI_DMA_FROMDEVICE);
1488
1489 first = *(priv->rxringtail) & (1<<29) ? 1:0;
1490 if(first) priv->rx_prevlen=0;
1491
1492 last = *(priv->rxringtail) & (1<<28) ? 1:0;
1493 if(last){
1494 lastlen=((*priv->rxringtail) &0xfff);
1495
1496 /* if the last descriptor (that should
1497 * tell us the total packet len) tell
1498 * us something less than the descriptors
1499 * len we had until now, then there is some
1500 * problem..
1501 * workaround to prevent kernel panic
1502 */
1503 if(lastlen < priv->rx_prevlen)
1504 len=0;
1505 else
1506 len=lastlen-priv->rx_prevlen;
1507
1508 if(*(priv->rxringtail) & (1<<13)) {
c8d86be3
GKH
1509 if ((*(priv->rxringtail) & 0xfff) <500)
1510 priv->stats.rxcrcerrmin++;
1511 else if ((*(priv->rxringtail) & 0x0fff) >1000)
1512 priv->stats.rxcrcerrmax++;
1513 else
1514 priv->stats.rxcrcerrmid++;
1515
1516 }
1517
1518 }else{
1519 len = priv->rxbuffersize;
1520 }
1521
c8d86be3
GKH
1522 if(first && last) {
1523 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1524 }else if(first) {
1525 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1526 if(padding) {
1527 len -= 2;
1528 }
1529 }else {
1530 padding = 0;
1531 }
c8d86be3 1532 padding = 0;
c8d86be3
GKH
1533 priv->rx_prevlen+=len;
1534
1535 if(priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100){
1536 /* HW is probably passing several buggy frames
1537 * without FD or LD flag set.
1538 * Throw this garbage away to prevent skb
1539 * memory exausting
1540 */
1541 if(!priv->rx_skb_complete)
1542 dev_kfree_skb_any(priv->rx_skb);
1543 priv->rx_skb_complete = 1;
1544 }
1545
c8d86be3 1546 signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16);
1994130e 1547 signal = (signal & 0xfe) >> 1;
c8d86be3
GKH
1548
1549 quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff));
1550
1551 stats.mac_time[0] = *(priv->rxringtail+1);
1552 stats.mac_time[1] = *(priv->rxringtail+2);
1553 rxpower =((char)(((*(priv->rxringtail+4))& (0x00ff0000))>>16))/2 - 42;
1554 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>> 8)) & (0x7f);
1555
c8d86be3
GKH
1556 rate=((*(priv->rxringtail)) &
1557 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20;
1558
1559 stats.rate = rtl8180_rate2rate(rate);
c8d86be3 1560 Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ;
c8d86be3
GKH
1561 if(!rtl8180_IsWirelessBMode(stats.rate))
1562 { // OFDM rate.
1563
1564 RxAGC_dBm = rxpower+1; //bias
1565 }
1566 else
1567 { // CCK rate.
1568 RxAGC_dBm = signal;//bit 0 discard
1569
1570 LNA = (u8) (RxAGC_dBm & 0x60 ) >> 5 ; //bit 6~ bit 5
1571 BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0
1572
1573 RxAGC_dBm = -( LNA_gain[LNA] + (BB *2) ); //Pin_11b=-(LNA_gain+BB_gain) (dBm)
1574
1575 RxAGC_dBm +=4; //bias
1576 }
1577
1578 if(RxAGC_dBm & 0x80) //absolute value
1579 RXAGC= ~(RxAGC_dBm)+1;
1580 bCckRate = rtl8180_IsWirelessBMode(stats.rate);
1581 // Translate RXAGC into 1-100.
1582 if(!rtl8180_IsWirelessBMode(stats.rate))
1583 { // OFDM rate.
1584 if(RXAGC>90)
1585 RXAGC=90;
1586 else if(RXAGC<25)
1587 RXAGC=25;
1588 RXAGC=(90-RXAGC)*100/65;
1589 }
1590 else
1591 { // CCK rate.
1592 if(RXAGC>95)
1593 RXAGC=95;
1594 else if(RXAGC<30)
1595 RXAGC=30;
1596 RXAGC=(95-RXAGC)*100/65;
1597 }
1598 priv->SignalStrength = (u8)RXAGC;
1994130e 1599 priv->RecvSignalPower = RxAGC_dBm;
c8d86be3
GKH
1600 priv->RxPower = rxpower;
1601 priv->RSSI = RSSI;
1994130e 1602 /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */
c8d86be3
GKH
1603 if(quality >= 127)
1604 quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now;
1605 else if(quality < 27)
1606 quality = 100;
1607 else
1608 quality = 127 - quality;
1609 priv->SignalQuality = quality;
c8d86be3
GKH
1610
1611 stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength;
1612 stats.signalstrength = RXAGC;
1613 if(stats.signalstrength > 100)
1614 stats.signalstrength = 100;
1615 stats.signalstrength = (stats.signalstrength * 70)/100 + 30;
1616 // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength);
1617 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality;
1618 stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual;
c8d86be3
GKH
1619 bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 )
1620 | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 );
1621 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13;
1622 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12;
0604384d 1623 hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf;
c8d86be3
GKH
1624 fc = le16_to_cpu(hdr->frame_ctl);
1625 type = WLAN_FC_GET_TYPE(fc);
1626
1627 if((IEEE80211_FTYPE_CTL != type) &&
1628 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
1629 && (!bHwError) && (!bCRC)&& (!bICV))
1630 {
1994130e
LF
1631 /* Perform signal smoothing for dynamic
1632 * mechanism on demand. This is different
1633 * with PerformSignalSmoothing8185 in smoothing
1634 * fomula. No dramatic adjustion is apply
1635 * because dynamic mechanism need some degree
1636 * of correctness. */
c8d86be3
GKH
1637 PerformUndecoratedSignalSmoothing8185(priv,bCckRate);
1638 //
1639 // For good-looking singal strength.
1640 //
1641 SignalStrengthIndex = NetgearSignalStrengthTranslate(
1642 priv->LastSignalStrengthInPercent,
1643 priv->SignalStrength);
1644
1645 priv->LastSignalStrengthInPercent = SignalStrengthIndex;
1646 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex);
1647 //
1648 // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified,
1649 // so we record the correct power here.
1650 //
1651 priv->Stats_SignalQuality =(long) (priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6;
1652 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower -1) / 6;
1653
1654 // Figure out which antenna that received the lasted packet.
1655 priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main.
c8d86be3
GKH
1656 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength);
1657 }
1658
c8d86be3
GKH
1659 if(first){
1660 if(!priv->rx_skb_complete){
1661 /* seems that HW sometimes fails to reiceve and
1662 doesn't provide the last descriptor */
c8d86be3
GKH
1663 dev_kfree_skb_any(priv->rx_skb);
1664 priv->stats.rxnolast++;
c8d86be3
GKH
1665 }
1666 /* support for prism header has been originally added by Christian */
1667 if(priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1668
c8d86be3
GKH
1669 }else{
1670 priv->rx_skb = dev_alloc_skb(len+2);
1671 if( !priv->rx_skb) goto drop;
c8d86be3
GKH
1672 }
1673
1674 priv->rx_skb_complete=0;
1675 priv->rx_skb->dev=dev;
1676 }else{
1677 /* if we are here we should have already RXed
1678 * the first frame.
1679 * If we get here and the skb is not allocated then
1680 * we have just throw out garbage (skb not allocated)
1681 * and we are still rxing garbage....
1682 */
1683 if(!priv->rx_skb_complete){
1684
1685 tmp_skb= dev_alloc_skb(priv->rx_skb->len +len+2);
1686
1687 if(!tmp_skb) goto drop;
1688
1689 tmp_skb->dev=dev;
c8d86be3 1690
c8d86be3
GKH
1691 memcpy(skb_put(tmp_skb,priv->rx_skb->len),
1692 priv->rx_skb->data,
1693 priv->rx_skb->len);
c8d86be3
GKH
1694
1695 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH
1696
1697 priv->rx_skb=tmp_skb;
1698 }
1699 }
ff954853 1700
c8d86be3 1701 if(!priv->rx_skb_complete) {
c8d86be3
GKH
1702 if(padding) {
1703 memcpy(skb_put(priv->rx_skb,len),
1704 (((unsigned char *)priv->rxbuffer->buf) + 2),len);
1705 } else {
c8d86be3
GKH
1706 memcpy(skb_put(priv->rx_skb,len),
1707 priv->rxbuffer->buf,len);
c8d86be3 1708 }
c8d86be3 1709 }
c8d86be3
GKH
1710
1711 if(last && !priv->rx_skb_complete){
c8d86be3
GKH
1712 if(priv->rx_skb->len > 4)
1713 skb_trim(priv->rx_skb,priv->rx_skb->len-4);
df574b8e 1714 if(!ieee80211_rtl_rx(priv->ieee80211,
1994130e 1715 priv->rx_skb, &stats))
c8d86be3 1716 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH
1717 priv->rx_skb_complete=1;
1718 }
1719
c8d86be3
GKH
1720 pci_dma_sync_single_for_device(priv->pdev,
1721 priv->rxbuffer->dma,
1722 priv->rxbuffersize * \
1723 sizeof(u8),
1724 PCI_DMA_FROMDEVICE);
1725
bbc9a991 1726drop: // this is used when we have not enough mem
c8d86be3
GKH
1727 /* restore the descriptor */
1728 *(priv->rxringtail+2)=priv->rxbuffer->dma;
1729 *(priv->rxringtail)=*(priv->rxringtail) &~ 0xfff;
1730 *(priv->rxringtail)=
1731 *(priv->rxringtail) | priv->rxbuffersize;
1732
1733 *(priv->rxringtail)=
1734 *(priv->rxringtail) | (1<<31);
c8d86be3
GKH
1735
1736 priv->rxringtail+=rx_desc_size;
1737 if(priv->rxringtail >=
1738 (priv->rxring)+(priv->rxringcount )*rx_desc_size)
1739 priv->rxringtail=priv->rxring;
1740
c8d86be3 1741 priv->rxbuffer=(priv->rxbuffer->next);
c8d86be3 1742 }
c8d86be3
GKH
1743}
1744
1745
1746void rtl8180_dma_kick(struct net_device *dev, int priority)
1747{
1748 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1749
1750 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
1751 write_nic_byte(dev, TX_DMA_POLLING,
1752 (1 << (priority + 1)) | priv->dma_poll_mask);
1753 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1754
1755 force_pci_posting(dev);
1756}
1757
c8d86be3
GKH
1758void rtl8180_data_hard_stop(struct net_device *dev)
1759{
1760 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1761
1762 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
1763 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ;
1764 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH
1765 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1766}
1767
c8d86be3
GKH
1768void rtl8180_data_hard_resume(struct net_device *dev)
1769{
1770 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1771
1772 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
1773 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ);
1774 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH
1775 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1776}
1777
c8d86be3
GKH
1778/* this function TX data frames when the ieee80211 stack requires this.
1779 * It checks also if we need to stop the ieee tx queue, eventually do it
1780 */
1781void rtl8180_hard_data_xmit(struct sk_buff *skb,struct net_device *dev, int
1782rate)
1783{
1784 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1785 int mode;
1786 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data;
b6b1ac69 1787 short morefrag = (h->frame_control) & IEEE80211_FCTL_MOREFRAGS;
c8d86be3
GKH
1788 unsigned long flags;
1789 int priority;
c8d86be3
GKH
1790
1791 mode = priv->ieee80211->iw_mode;
1792
1793 rate = ieeerate2rtlrate(rate);
1794 /*
1795 * This function doesn't require lock because we make
1796 * sure it's called with the tx_lock already acquired.
bbc9a991
AGR
1797 * this come from the kernel's hard_xmit callback (through
1798 * the ieee stack, or from the try_wake_queue (again through
c8d86be3
GKH
1799 * the ieee stack.
1800 */
c8d86be3 1801 priority = AC2Q(skb->priority);
c8d86be3
GKH
1802 spin_lock_irqsave(&priv->tx_lock,flags);
1803
1804 if(priv->ieee80211->bHwRadioOff)
1805 {
1806 spin_unlock_irqrestore(&priv->tx_lock,flags);
1807
1808 return;
1809 }
1810
c8d86be3 1811 if (!check_nic_enought_desc(dev, priority)){
c8d86be3
GKH
1812 DMESGW("Error: no descriptor left by previous TX (avail %d) ",
1813 get_curr_tx_free_desc(dev, priority));
df574b8e 1814 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3
GKH
1815 }
1816 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag,0,rate);
1817 if (!check_nic_enought_desc(dev, priority))
df574b8e 1818 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3 1819
c8d86be3 1820 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3
GKH
1821}
1822
1823/* This is a rough attempt to TX a frame
1824 * This is called by the ieee 80211 stack to TX management frames.
1825 * If the ring is full packet are dropped (for data frame the queue
1826 * is stopped before this can happen). For this reason it is better
1827 * if the descriptors are larger than the largest management frame
1828 * we intend to TX: i'm unsure what the HW does if it will not found
1829 * the last fragment of a frame because it has been dropped...
1830 * Since queues for Management and Data frames are different we
1831 * might use a different lock than tx_lock (for example mgmt_tx_lock)
1832 */
1833/* these function may loops if invoked with 0 descriptors or 0 len buffer*/
1834int rtl8180_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
1835{
1836 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 1837 unsigned long flags;
c8d86be3
GKH
1838 int priority;
1839
c8d86be3 1840 priority = MANAGE_PRIORITY;
c8d86be3
GKH
1841
1842 spin_lock_irqsave(&priv->tx_lock,flags);
1843
fd882783 1844 if (priv->ieee80211->bHwRadioOff) {
c8d86be3 1845 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3 1846 dev_kfree_skb_any(skb);
ec634fe3 1847 return NETDEV_TX_OK;
c8d86be3
GKH
1848 }
1849
1850 rtl8180_tx(dev, skb->data, skb->len, priority,
1851 0, 0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
1852
1853 priv->ieee80211->stats.tx_bytes+=skb->len;
1854 priv->ieee80211->stats.tx_packets++;
1855 spin_unlock_irqrestore(&priv->tx_lock,flags);
1856
1857 dev_kfree_skb_any(skb);
ec634fe3 1858 return NETDEV_TX_OK;
c8d86be3
GKH
1859}
1860
1861// longpre 144+48 shortpre 72+24
1862u16 rtl8180_len2duration(u32 len, short rate,short* ext)
1863{
1864 u16 duration;
1865 u16 drift;
1866 *ext=0;
1867
1868 switch(rate){
1869 case 0://1mbps
1870 *ext=0;
1871 duration = ((len+4)<<4) /0x2;
1872 drift = ((len+4)<<4) % 0x2;
1873 if(drift ==0 ) break;
1874 duration++;
1875 break;
c8d86be3
GKH
1876 case 1://2mbps
1877 *ext=0;
1878 duration = ((len+4)<<4) /0x4;
1879 drift = ((len+4)<<4) % 0x4;
1880 if(drift ==0 ) break;
1881 duration++;
1882 break;
c8d86be3
GKH
1883 case 2: //5.5mbps
1884 *ext=0;
1885 duration = ((len+4)<<4) /0xb;
1886 drift = ((len+4)<<4) % 0xb;
1887 if(drift ==0 )
1888 break;
1889 duration++;
1890 break;
c8d86be3
GKH
1891 default:
1892 case 3://11mbps
1893 *ext=0;
1894 duration = ((len+4)<<4) /0x16;
1895 drift = ((len+4)<<4) % 0x16;
1896 if(drift ==0 )
1897 break;
1898 duration++;
1899 if(drift > 6)
1900 break;
1901 *ext=1;
1902 break;
1903 }
1904
1905 return duration;
1906}
1907
c8d86be3
GKH
1908void rtl8180_prepare_beacon(struct net_device *dev)
1909{
c8d86be3 1910 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
1911 struct sk_buff *skb;
1912
1913 u16 word = read_nic_word(dev, BcnItv);
1914 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
1915 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval);//0x64;
1916 write_nic_word(dev, BcnItv, word);
1917
c8d86be3
GKH
1918 skb = ieee80211_get_beacon(priv->ieee80211);
1919 if(skb){
1920 rtl8180_tx(dev,skb->data,skb->len,BEACON_PRIORITY,
1921 0,0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
1922 dev_kfree_skb_any(skb);
1923 }
c8d86be3
GKH
1924}
1925
1926/* This function do the real dirty work: it enqueues a TX command
1927 * descriptor in the ring buffer, copyes the frame in a TX buffer
1928 * and kicks the NIC to ensure it does the DMA transfer.
1929 */
1930short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority,
1931 short morefrag, short descfrag, int rate)
1932{
1933 struct r8180_priv *priv = ieee80211_priv(dev);
1934 u32 *tail,*temp_tail;
1935 u32 *begin;
1936 u32 *buf;
1937 int i;
1938 int remain;
1939 int buflen;
1940 int count;
c8d86be3
GKH
1941 u16 duration;
1942 short ext;
1943 struct buffer* buflist;
c8d86be3
GKH
1944 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf;
1945 u8 dest[ETH_ALEN];
1946 u8 bUseShortPreamble = 0;
1947 u8 bCTSEnable = 0;
1948 u8 bRTSEnable = 0;
c8d86be3
GKH
1949 u16 Duration = 0;
1950 u16 RtsDur = 0;
1951 u16 ThisFrameTime = 0;
1952 u16 TxDescDuration = 0;
1994130e 1953 u8 ownbit_flag = false;
c8d86be3
GKH
1954
1955 switch(priority) {
1956 case MANAGE_PRIORITY:
1957 tail=priv->txmapringtail;
1958 begin=priv->txmapring;
1959 buflist = priv->txmapbufstail;
1960 count = priv->txringcount;
1961 break;
c8d86be3
GKH
1962 case BK_PRIORITY:
1963 tail=priv->txbkpringtail;
1964 begin=priv->txbkpring;
1965 buflist = priv->txbkpbufstail;
1966 count = priv->txringcount;
1967 break;
c8d86be3
GKH
1968 case BE_PRIORITY:
1969 tail=priv->txbepringtail;
1970 begin=priv->txbepring;
1971 buflist = priv->txbepbufstail;
1972 count = priv->txringcount;
1973 break;
c8d86be3
GKH
1974 case VI_PRIORITY:
1975 tail=priv->txvipringtail;
1976 begin=priv->txvipring;
1977 buflist = priv->txvipbufstail;
1978 count = priv->txringcount;
1979 break;
c8d86be3
GKH
1980 case VO_PRIORITY:
1981 tail=priv->txvopringtail;
1982 begin=priv->txvopring;
1983 buflist = priv->txvopbufstail;
1984 count = priv->txringcount;
1985 break;
c8d86be3
GKH
1986 case HI_PRIORITY:
1987 tail=priv->txhpringtail;
1988 begin=priv->txhpring;
1989 buflist = priv->txhpbufstail;
1990 count = priv->txringcount;
1991 break;
c8d86be3
GKH
1992 case BEACON_PRIORITY:
1993 tail=priv->txbeaconringtail;
1994 begin=priv->txbeaconring;
1995 buflist = priv->txbeaconbufstail;
1996 count = priv->txbeaconcount;
1997 break;
c8d86be3
GKH
1998 default:
1999 return -1;
2000 break;
2001 }
2002
c8d86be3
GKH
2003 memcpy(&dest, frag_hdr->addr1, ETH_ALEN);
2004 if (is_multicast_ether_addr(dest) ||
2005 is_broadcast_ether_addr(dest))
2006 {
2007 Duration = 0;
2008 RtsDur = 0;
2009 bRTSEnable = 0;
2010 bCTSEnable = 0;
2011
2012 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2013 TxDescDuration = ThisFrameTime;
2014 } else {// Unicast packet
c8d86be3
GKH
2015 u16 AckTime;
2016
2017 //YJ,add,080828,for Keep alive
2018 priv->NumTxUnicast++;
2019
1994130e
LF
2020 /* Figure out ACK rate according to BSS basic rate
2021 * and Tx rate. */
c8d86be3 2022 AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
c8d86be3
GKH
2023
2024 if ( ((len + sCrcLng) > priv->rts) && priv->rts )
2025 { // RTS/CTS.
2026 u16 RtsTime, CtsTime;
2027 //u16 CtsRate;
2028 bRTSEnable = 1;
2029 bCTSEnable = 0;
2030
2031 // Rate and time required for RTS.
2032 RtsTime = ComputeTxTime( sAckCtsLng/8,priv->ieee80211->basic_rate, 0, 0);
2033 // Rate and time required for CTS.
2034 CtsTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
2035
2036 // Figure out time required to transmit this frame.
2037 ThisFrameTime = ComputeTxTime(len + sCrcLng,
2038 rtl8180_rate2rate(rate),
2039 0,
2040 bUseShortPreamble);
2041
2042 // RTS-CTS-ThisFrame-ACK.
2043 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime;
2044
2045 TxDescDuration = RtsTime + RtsDur;
2046 }
2047 else {// Normal case.
2048 bCTSEnable = 0;
2049 bRTSEnable = 0;
2050 RtsDur = 0;
2051
2052 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2053 TxDescDuration = ThisFrameTime + aSifsTime + AckTime;
2054 }
2055
b6b1ac69 2056 if (!(frag_hdr->frame_control & IEEE80211_FCTL_MOREFRAGS)) {
c8d86be3
GKH
2057 // ThisFrame-ACK.
2058 Duration = aSifsTime + AckTime;
2059 } else { // One or more fragments remained.
2060 u16 NextFragTime;
2061 NextFragTime = ComputeTxTime( len + sCrcLng, //pretend following packet length equal current packet
2062 rtl8180_rate2rate(rate),
2063 0,
2064 bUseShortPreamble );
2065
2066 //ThisFrag-ACk-NextFrag-ACK.
2067 Duration = NextFragTime + 3*aSifsTime + 2*AckTime;
2068 }
2069
2070 } // End of Unicast packet
2071
2072 frag_hdr->duration_id = Duration;
c8d86be3
GKH
2073
2074 buflen=priv->txbuffsize;
2075 remain=len;
2076 temp_tail = tail;
fd882783 2077
c8d86be3 2078 while(remain!=0){
c8d86be3
GKH
2079 mb();
2080 if(!buflist){
2081 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority);
c8d86be3
GKH
2082 return -1;
2083 }
2084 buf=buflist->buf;
2085
fd882783
BZ
2086 if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) {
2087 DMESGW("No more TX desc, returning %x of %x",
2088 remain, len);
2089 priv->stats.txrdu++;
c8d86be3 2090 return remain;
c8d86be3
GKH
2091 }
2092
2093 *tail= 0; // zeroes header
2094 *(tail+1) = 0;
2095 *(tail+3) = 0;
2096 *(tail+5) = 0;
2097 *(tail+6) = 0;
2098 *(tail+7) = 0;
2099
d44eb889
LF
2100 /*FIXME: this should be triggered by HW encryption parameters.*/
2101 *tail |= (1<<15); /* no encrypt */
fd882783 2102
c8d86be3 2103 if(remain==len && !descfrag) {
1994130e 2104 ownbit_flag = false;
c8d86be3
GKH
2105 *tail = *tail| (1<<29) ; //fist segment of the packet
2106 *tail = *tail |(len);
2107 } else {
2108 ownbit_flag = true;
2109 }
2110
2111 for(i=0;i<buflen&& remain >0;i++,remain--){
2112 ((u8*)buf)[i]=txbuf[i]; //copy data into descriptor pointed DMAble buffer
2113 if(remain == 4 && i+4 >= buflen) break;
2114 /* ensure the last desc has at least 4 bytes payload */
2115
2116 }
2117 txbuf = txbuf + i;
2118 *(tail+3)=*(tail+3) &~ 0xfff;
2119 *(tail+3)=*(tail+3) | i; // buffer lenght
2120 // Use short preamble or not
2121 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE)
2122 if (priv->plcp_preamble_mode==1 && rate!=0) // short mode now, not long!
b3184e1e 2123 ;// *tail |= (1<<16); // enable short preamble mode.
c8d86be3 2124
c8d86be3
GKH
2125 if(bCTSEnable) {
2126 *tail |= (1<<18);
2127 }
2128
2129 if(bRTSEnable) //rts enable
2130 {
2131 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE
2132 *tail |= (1<<23);//rts enable
2133 *(tail+1) |=(RtsDur&0xffff);//RTS Duration
2134 }
2135 *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION
2136// *(tail+3) |= (0xe6<<16);
2137 *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ;
c8d86be3
GKH
2138
2139 *tail = *tail | ((rate&0xf) << 24);
c8d86be3
GKH
2140
2141 /* hw_plcp_len is not used for rtl8180 chip */
2142 /* FIXME */
d44eb889 2143 if (!priv->hw_plcp_len) {
fd882783 2144 duration = rtl8180_len2duration(len, rate, &ext);
c8d86be3
GKH
2145 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16);
2146 if(ext) *(tail+1) = *(tail+1) |(1<<31); //plcp length extension
2147 }
2148
2149 if(morefrag) *tail = (*tail) | (1<<17); // more fragment
2150 if(!remain) *tail = (*tail) | (1<<28); // last segment of frame
2151
c8d86be3
GKH
2152 *(tail+5) = *(tail+5)|(2<<27);
2153 *(tail+7) = *(tail+7)|(1<<4);
2154
2155 wmb();
2156 if(ownbit_flag)
2157 {
2158 *tail = *tail | (1<<31); // descriptor ready to be txed
2159 }
2160
c8d86be3
GKH
2161 if((tail - begin)/8 == count-1)
2162 tail=begin;
c8d86be3
GKH
2163 else
2164 tail=tail+8;
2165
2166 buflist=buflist->next;
2167
2168 mb();
2169
2170 switch(priority) {
2171 case MANAGE_PRIORITY:
2172 priv->txmapringtail=tail;
2173 priv->txmapbufstail=buflist;
2174 break;
c8d86be3
GKH
2175 case BK_PRIORITY:
2176 priv->txbkpringtail=tail;
2177 priv->txbkpbufstail=buflist;
2178 break;
c8d86be3
GKH
2179 case BE_PRIORITY:
2180 priv->txbepringtail=tail;
2181 priv->txbepbufstail=buflist;
2182 break;
c8d86be3
GKH
2183 case VI_PRIORITY:
2184 priv->txvipringtail=tail;
2185 priv->txvipbufstail=buflist;
2186 break;
c8d86be3
GKH
2187 case VO_PRIORITY:
2188 priv->txvopringtail=tail;
2189 priv->txvopbufstail=buflist;
2190 break;
c8d86be3
GKH
2191 case HI_PRIORITY:
2192 priv->txhpringtail=tail;
2193 priv->txhpbufstail = buflist;
2194 break;
c8d86be3
GKH
2195 case BEACON_PRIORITY:
2196 /* the HW seems to be happy with the 1st
2197 * descriptor filled and the 2nd empty...
2198 * So always update descriptor 1 and never
2199 * touch 2nd
2200 */
c8d86be3 2201 break;
c8d86be3 2202 }
c8d86be3
GKH
2203 }
2204 *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed
2205 rtl8180_dma_kick(dev,priority);
c8d86be3
GKH
2206
2207 return 0;
c8d86be3
GKH
2208}
2209
c8d86be3
GKH
2210void rtl8180_irq_rx_tasklet(struct r8180_priv * priv);
2211
c8d86be3
GKH
2212void rtl8180_link_change(struct net_device *dev)
2213{
2214 struct r8180_priv *priv = ieee80211_priv(dev);
2215 u16 beacon_interval;
c8d86be3 2216 struct ieee80211_network *net = &priv->ieee80211->current_network;
c8d86be3 2217
fd882783 2218 rtl8180_update_msr(dev);
c8d86be3
GKH
2219
2220 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2221
2222 write_nic_dword(dev,BSSID,((u32*)net->bssid)[0]);
2223 write_nic_word(dev,BSSID+4,((u16*)net->bssid)[2]);
2224
c8d86be3
GKH
2225 beacon_interval = read_nic_dword(dev,BEACON_INTERVAL);
2226 beacon_interval &= ~ BEACON_INTERVAL_MASK;
2227 beacon_interval |= net->beacon_interval;
2228 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval);
2229
2230 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
2231
d44eb889 2232 rtl8180_set_chan(dev, priv->chan);
c8d86be3
GKH
2233}
2234
2235void rtl8180_rq_tx_ack(struct net_device *dev){
2236
2237 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 2238
c8d86be3
GKH
2239 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)|CONFIG4_PWRMGT);
2240 priv->ack_tx_to_ieee = 1;
2241}
2242
2243short rtl8180_is_tx_queue_empty(struct net_device *dev){
2244
2245 struct r8180_priv *priv = ieee80211_priv(dev);
2246 u32* d;
2247
2248 for (d = priv->txmapring;
2249 d < priv->txmapring + priv->txringcount;d+=8)
2250 if(*d & (1<<31)) return 0;
2251
2252 for (d = priv->txbkpring;
2253 d < priv->txbkpring + priv->txringcount;d+=8)
2254 if(*d & (1<<31)) return 0;
2255
2256 for (d = priv->txbepring;
2257 d < priv->txbepring + priv->txringcount;d+=8)
2258 if(*d & (1<<31)) return 0;
2259
2260 for (d = priv->txvipring;
2261 d < priv->txvipring + priv->txringcount;d+=8)
2262 if(*d & (1<<31)) return 0;
2263
2264 for (d = priv->txvopring;
2265 d < priv->txvopring + priv->txringcount;d+=8)
2266 if(*d & (1<<31)) return 0;
2267
2268 for (d = priv->txhpring;
2269 d < priv->txhpring + priv->txringcount;d+=8)
2270 if(*d & (1<<31)) return 0;
2271 return 1;
2272}
2273/* FIXME FIXME 5msecs is random */
2274#define HW_WAKE_DELAY 5
2275
2276void rtl8180_hw_wakeup(struct net_device *dev)
2277{
2278 unsigned long flags;
c8d86be3
GKH
2279 struct r8180_priv *priv = ieee80211_priv(dev);
2280
2281 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3 2282 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)&~CONFIG4_PWRMGT);
fd882783 2283 if (priv->rf_wakeup)
c8d86be3 2284 priv->rf_wakeup(dev);
c8d86be3
GKH
2285 spin_unlock_irqrestore(&priv->ps_lock,flags);
2286}
2287
2288void rtl8180_hw_sleep_down(struct net_device *dev)
2289{
2290 unsigned long flags;
c8d86be3
GKH
2291 struct r8180_priv *priv = ieee80211_priv(dev);
2292
2293 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3
GKH
2294 if(priv->rf_sleep)
2295 priv->rf_sleep(dev);
2296 spin_unlock_irqrestore(&priv->ps_lock,flags);
2297}
2298
c8d86be3
GKH
2299void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl)
2300{
c8d86be3 2301 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
2302 u32 rb = jiffies;
2303 unsigned long flags;
2304
2305 spin_lock_irqsave(&priv->ps_lock,flags);
2306
2307 /* Writing HW register with 0 equals to disable
2308 * the timer, that is not really what we want
2309 */
2310 tl -= MSECS(4+16+7);
2311
c8d86be3
GKH
2312 /* If the interval in witch we are requested to sleep is too
2313 * short then give up and remain awake
2314 */
2315 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
2316 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
2317 spin_unlock_irqrestore(&priv->ps_lock,flags);
2318 printk("too short to sleep\n");
2319 return;
2320 }
2321
c8d86be3
GKH
2322 {
2323 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
c8d86be3 2324
c8d86be3
GKH
2325 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp);
2326
2327 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
2328 }
2329 /* if we suspect the TimerInt is gone beyond tl
2330 * while setting it, then give up
2331 */
fd882783 2332
c8d86be3
GKH
2333 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
2334 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
2335 spin_unlock_irqrestore(&priv->ps_lock,flags);
2336 return;
2337 }
c8d86be3
GKH
2338
2339 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq);
2340 spin_unlock_irqrestore(&priv->ps_lock,flags);
2341}
2342
c8d86be3
GKH
2343void rtl8180_wmm_param_update(struct work_struct * work)
2344{
2345 struct ieee80211_device * ieee = container_of(work, struct ieee80211_device,wmm_param_update_wq);
c8d86be3 2346 struct net_device *dev = ieee->dev;
c8d86be3
GKH
2347 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param);
2348 u8 mode = ieee->current_network.mode;
2349 AC_CODING eACI;
2350 AC_PARAM AcParam;
2351 PAC_PARAM pAcParam;
2352 u8 i;
2353
c8d86be3
GKH
2354 if(!ieee->current_network.QoS_Enable){
2355 //legacy ac_xx_param update
2356 AcParam.longData = 0;
2357 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2358 AcParam.f.AciAifsn.f.ACM = 0;
2359 AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin.
2360 AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax.
2361 AcParam.f.TXOPLimit = 0;
2362 for(eACI = 0; eACI < AC_MAX; eACI++){
2363 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2364 {
2365 u8 u1bAIFS;
2366 u32 u4bAcParam;
2367 pAcParam = (PAC_PARAM)(&AcParam);
2368 // Retrive paramters to udpate.
2369 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN *(((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2370 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)|
2371 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)|
2372 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)|
2373 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2374 switch(eACI){
2375 case AC1_BK:
2376 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2377 break;
c8d86be3
GKH
2378 case AC0_BE:
2379 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2380 break;
c8d86be3
GKH
2381 case AC2_VI:
2382 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2383 break;
c8d86be3
GKH
2384 case AC3_VO:
2385 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2386 break;
c8d86be3
GKH
2387 default:
2388 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI);
2389 break;
2390 }
2391 }
2392 }
2393 return;
2394 }
2395
2396 for(i = 0; i < AC_MAX; i++){
2397 //AcParam.longData = 0;
2398 pAcParam = (AC_PARAM * )ac_param;
2399 {
2400 AC_CODING eACI;
2401 u8 u1bAIFS;
2402 u32 u4bAcParam;
2403
2404 // Retrive paramters to udpate.
2405 eACI = pAcParam->f.AciAifsn.f.ACI;
2406 //Mode G/A: slotTimeTimer = 9; Mode B: 20
2407 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2408 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2409 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2410 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2411 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2412
2413 switch(eACI){
2414 case AC1_BK:
2415 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2416 break;
c8d86be3
GKH
2417 case AC0_BE:
2418 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2419 break;
c8d86be3
GKH
2420 case AC2_VI:
2421 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2422 break;
c8d86be3
GKH
2423 case AC3_VO:
2424 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2425 break;
c8d86be3
GKH
2426 default:
2427 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2428 break;
2429 }
2430 }
2431 ac_param += (sizeof(AC_PARAM));
2432 }
c8d86be3
GKH
2433}
2434
c8d86be3 2435void rtl8180_tx_irq_wq(struct work_struct *work);
c8d86be3
GKH
2436void rtl8180_restart_wq(struct work_struct *work);
2437//void rtl8180_rq_tx_ack(struct work_struct *work);
c8d86be3 2438void rtl8180_watch_dog_wq(struct work_struct *work);
c8d86be3 2439void rtl8180_hw_wakeup_wq(struct work_struct *work);
c8d86be3 2440void rtl8180_hw_sleep_wq(struct work_struct *work);
c8d86be3 2441void rtl8180_sw_antenna_wq(struct work_struct *work);
0370453f
BZ
2442void rtl8180_watch_dog(struct net_device *dev);
2443
c8d86be3
GKH
2444void watch_dog_adaptive(unsigned long data)
2445{
fd882783
BZ
2446 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data);
2447
2448 if (!priv->up) {
c8d86be3
GKH
2449 DMESG("<----watch_dog_adaptive():driver is not up!\n");
2450 return;
2451 }
2452
c8d86be3 2453 // Tx High Power Mechanism.
c8d86be3 2454 if(CheckHighPower((struct net_device *)data))
c8d86be3 2455 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq);
c8d86be3 2456
c8d86be3 2457 // Tx Power Tracking on 87SE.
cffd4e16 2458 if (CheckTxPwrTracking((struct net_device *)data))
c8d86be3 2459 TxPwrTracking87SE((struct net_device *)data);
c8d86be3
GKH
2460
2461 // Perform DIG immediately.
c8d86be3 2462 if(CheckDig((struct net_device *)data) == true)
c8d86be3 2463 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq);
c8d86be3
GKH
2464 rtl8180_watch_dog((struct net_device *)data);
2465
c8d86be3
GKH
2466 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem);
2467
2468 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
2469 add_timer(&priv->watch_dog_timer);
c8d86be3
GKH
2470}
2471
c8d86be3
GKH
2472static CHANNEL_LIST ChannelPlan[] = {
2473 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC
2474 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
2475 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
2476 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI.
2477 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI.
2478 {{14,36,40,44,48,52,56,60,64},9}, //MKK
2479 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1
2480 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel.
2481 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC
2482 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
2483 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826
2484};
2485
2486static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee)
2487{
2488 int i;
2489
2490 //lzm add 080826
2491 ieee->MinPassiveChnlNum=MAX_CHANNEL_NUMBER+1;
2492 ieee->IbssStartChnl=0;
2493
2494 switch (channel_plan)
2495 {
2496 case COUNTRY_CODE_FCC:
2497 case COUNTRY_CODE_IC:
2498 case COUNTRY_CODE_ETSI:
2499 case COUNTRY_CODE_SPAIN:
2500 case COUNTRY_CODE_FRANCE:
2501 case COUNTRY_CODE_MKK:
2502 case COUNTRY_CODE_MKK1:
2503 case COUNTRY_CODE_ISRAEL:
2504 case COUNTRY_CODE_TELEC:
2505 {
2506 Dot11d_Init(ieee);
2507 ieee->bGlobalDomain = false;
2508 if (ChannelPlan[channel_plan].Len != 0){
2509 // Clear old channel map
2510 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2511 // Set new channel map
2512 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
2513 {
2514 if(ChannelPlan[channel_plan].Channel[i] <= 14)
2515 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
2516 }
2517 }
2518 break;
2519 }
2520 case COUNTRY_CODE_GLOBAL_DOMAIN:
2521 {
2522 GET_DOT11D_INFO(ieee)->bEnabled = 0;
2523 Dot11d_Reset(ieee);
2524 ieee->bGlobalDomain = true;
2525 break;
2526 }
2527 case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826
2528 {
2529 ieee->MinPassiveChnlNum=12;
2530 ieee->IbssStartChnl= 10;
2531 break;
2532 }
2533 default:
2534 {
2535 Dot11d_Init(ieee);
2536 ieee->bGlobalDomain = false;
2537 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2538 for (i=1;i<=14;i++)
2539 {
2540 GET_DOT11D_INFO(ieee)->channel_map[i] = 1;
2541 }
2542 break;
2543 }
2544 }
2545}
c8d86be3 2546
c8d86be3 2547void GPIOChangeRFWorkItemCallBack(struct work_struct *work);
c8d86be3
GKH
2548
2549//YJ,add,080828
2550static void rtl8180_statistics_init(struct Stats *pstats)
2551{
2552 memset(pstats, 0, sizeof(struct Stats));
2553}
fd882783 2554
c8d86be3
GKH
2555static void rtl8180_link_detect_init(plink_detect_t plink_detect)
2556{
2557 memset(plink_detect, 0, sizeof(link_detect_t));
2558 plink_detect->SlotNum = DEFAULT_SLOT_NUM;
2559}
2560//YJ,add,080828,end
2561
742821ce
LF
2562static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom)
2563{
2564 struct net_device *dev = eeprom->data;
2565 u8 reg = read_nic_byte(dev, EPROM_CMD);
2566
2567 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
2568 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
2569 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
2570 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
2571}
2572
2573static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom)
2574{
2575 struct net_device *dev = eeprom->data;
2576 u8 reg = 2 << 6;
2577
2578 if (eeprom->reg_data_in)
2579 reg |= RTL818X_EEPROM_CMD_WRITE;
2580 if (eeprom->reg_data_out)
2581 reg |= RTL818X_EEPROM_CMD_READ;
2582 if (eeprom->reg_data_clock)
2583 reg |= RTL818X_EEPROM_CMD_CK;
2584 if (eeprom->reg_chip_select)
2585 reg |= RTL818X_EEPROM_CMD_CS;
2586
2587 write_nic_byte(dev, EPROM_CMD, reg);
2588 read_nic_byte(dev, EPROM_CMD);
2589 udelay(10);
2590}
2591
c8d86be3
GKH
2592short rtl8180_init(struct net_device *dev)
2593{
2594 struct r8180_priv *priv = ieee80211_priv(dev);
2595 u16 word;
2596 u16 version;
c8d86be3
GKH
2597 u32 usValue;
2598 u16 tmpu16;
2599 int i, j;
742821ce
LF
2600 struct eeprom_93cx6 eeprom;
2601 u16 eeprom_val;
2602
2603 eeprom.data = dev;
2604 eeprom.register_read = rtl8187se_eeprom_register_read;
2605 eeprom.register_write = rtl8187se_eeprom_register_write;
2606 eeprom.width = PCI_EEPROM_WIDTH_93C46;
c8d86be3 2607
742821ce
LF
2608 eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val);
2609 priv->channel_plan = eeprom_val & 0xFF;
c8d86be3
GKH
2610 if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){
2611 printk("rtl8180_init:Error channel plan! Set to default.\n");
2612 priv->channel_plan = 0;
2613 }
c8d86be3
GKH
2614
2615 DMESG("Channel plan is %d\n",priv->channel_plan);
2616 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211);
c8d86be3 2617
c8d86be3
GKH
2618 //FIXME: these constants are placed in a bad pleace.
2619 priv->txbuffsize = 2048;//1024;
2620 priv->txringcount = 32;//32;
2621 priv->rxbuffersize = 2048;//1024;
2622 priv->rxringcount = 64;//32;
2623 priv->txbeaconcount = 2;
2624 priv->rx_skb_complete = 1;
c8d86be3 2625
c8d86be3
GKH
2626 priv->RFChangeInProgress = false;
2627 priv->SetRFPowerStateInProgress = false;
2628 priv->RFProgType = 0;
2629 priv->bInHctTest = false;
2630
2631 priv->irq_enabled=0;
2632
c8d86be3
GKH
2633 rtl8180_statistics_init(&priv->stats);
2634 rtl8180_link_detect_init(&priv->link_detect);
c8d86be3
GKH
2635
2636 priv->ack_tx_to_ieee = 0;
2637 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
2638 priv->ieee80211->iw_mode = IW_MODE_INFRA;
2639 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
2640 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2641 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2642 priv->ieee80211->active_scan = 1;
2643 priv->ieee80211->rate = 110; //11 mbps
2644 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION;
2645 priv->ieee80211->host_encrypt = 1;
2646 priv->ieee80211->host_decrypt = 1;
2647 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup;
2648 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack;
2649 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep;
2650 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty;
2651
2652 priv->hw_wep = hwwep;
2653 priv->prism_hdr=0;
2654 priv->dev=dev;
2655 priv->retry_rts = DEFAULT_RETRY_RTS;
2656 priv->retry_data = DEFAULT_RETRY_DATA;
2657 priv->RFChangeInProgress = false;
2658 priv->SetRFPowerStateInProgress = false;
2659 priv->RFProgType = 0;
2660 priv->bInHctTest = false;
2661 priv->bInactivePs = true;//false;
2662 priv->ieee80211->bInactivePs = priv->bInactivePs;
2663 priv->bSwRfProcessing = false;
2664 priv->eRFPowerState = eRfOff;
2665 priv->RfOffReason = 0;
2666 priv->LedStrategy = SW_LED_MODE0;
c8d86be3
GKH
2667 priv->TxPollingTimes = 0;//lzm add 080826
2668 priv->bLeisurePs = true;
2669 priv->dot11PowerSaveMode = eActive;
c8d86be3
GKH
2670 priv->AdMinCheckPeriod = 5;
2671 priv->AdMaxCheckPeriod = 10;
c8d86be3
GKH
2672 priv->AdMaxRxSsThreshold = 30;//60->30
2673 priv->AdRxSsThreshold = 20;//50->20
2674 priv->AdCheckPeriod = priv->AdMinCheckPeriod;
2675 priv->AdTickCount = 0;
2676 priv->AdRxSignalStrength = -1;
2677 priv->RegSwAntennaDiversityMechanism = 0;
2678 priv->RegDefaultAntenna = 0;
2679 priv->SignalStrength = 0;
2680 priv->AdRxOkCnt = 0;
2681 priv->CurrAntennaIndex = 0;
2682 priv->AdRxSsBeforeSwitched = 0;
2683 init_timer(&priv->SwAntennaDiversityTimer);
2684 priv->SwAntennaDiversityTimer.data = (unsigned long)dev;
2685 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback;
c8d86be3
GKH
2686 priv->bDigMechanism = 1;
2687 priv->InitialGain = 6;
2688 priv->bXtalCalibration = false;
2689 priv->XtalCal_Xin = 0;
2690 priv->XtalCal_Xout = 0;
2691 priv->bTxPowerTrack = false;
2692 priv->ThermalMeter = 0;
2693 priv->FalseAlarmRegValue = 0;
2694 priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG.
2695 priv->DIG_NumberFallbackVote = 0;
2696 priv->DIG_NumberUpgradeVote = 0;
2697 priv->LastSignalStrengthInPercent = 0;
2698 priv->Stats_SignalStrength = 0;
2699 priv->LastRxPktAntenna = 0;
2700 priv->SignalQuality = 0; // in 0-100 index.
2701 priv->Stats_SignalQuality = 0;
2702 priv->RecvSignalPower = 0; // in dBm.
2703 priv->Stats_RecvSignalPower = 0;
2704 priv->AdMainAntennaRxOkCnt = 0;
2705 priv->AdAuxAntennaRxOkCnt = 0;
2706 priv->bHWAdSwitched = false;
2707 priv->bRegHighPowerMechanism = true;
2708 priv->RegHiPwrUpperTh = 77;
2709 priv->RegHiPwrLowerTh = 75;
2710 priv->RegRSSIHiPwrUpperTh = 70;
2711 priv->RegRSSIHiPwrLowerTh = 20;
2712 priv->bCurCCKPkt = false;
2713 priv->UndecoratedSmoothedSS = -1;
2714 priv->bToUpdateTxPwr = false;
2715 priv->CurCCKRSSI = 0;
2716 priv->RxPower = 0;
2717 priv->RSSI = 0;
c8d86be3
GKH
2718 priv->NumTxOkTotal = 0;
2719 priv->NumTxUnicast = 0;
2720 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL;
2721 priv->PowerProfile = POWER_PROFILE_AC;
1994130e
LF
2722 priv->CurrRetryCnt = 0;
2723 priv->LastRetryCnt = 0;
2724 priv->LastTxokCnt = 0;
2725 priv->LastRxokCnt = 0;
2726 priv->LastRetryRate = 0;
2727 priv->bTryuping = 0;
2728 priv->CurrTxRate = 0;
2729 priv->CurrRetryRate = 0;
2730 priv->TryupingCount = 0;
2731 priv->TryupingCountNoData = 0;
2732 priv->TryDownCountLowData = 0;
2733 priv->LastTxOKBytes = 0;
2734 priv->LastFailTxRate = 0;
2735 priv->LastFailTxRateSS = 0;
2736 priv->FailTxRateCount = 0;
2737 priv->LastTxThroughput = 0;
2738 priv->NumTxOkBytesTotal = 0;
c8d86be3
GKH
2739 priv->ForcedDataRate = 0;
2740 priv->RegBModeGainStage = 1;
2741
1994130e 2742 priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
c8d86be3
GKH
2743 spin_lock_init(&priv->irq_lock);
2744 spin_lock_init(&priv->irq_th_lock);
2745 spin_lock_init(&priv->tx_lock);
2746 spin_lock_init(&priv->ps_lock);
2747 spin_lock_init(&priv->rf_ps_lock);
1994130e
LF
2748 sema_init(&priv->wx_sem, 1);
2749 sema_init(&priv->rf_state, 1);
2750 INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq);
2751 INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq);
2752 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,
2753 (void *)rtl8180_hw_wakeup_wq);
2754 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,
2755 (void *)rtl8180_hw_sleep_wq);
2756 INIT_WORK(&priv->ieee80211->wmm_param_update_wq,
2757 (void *)rtl8180_wmm_param_update);
2758 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,
2759 (void *)rtl8180_rate_adapter);
2760 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,
2761 (void *)rtl8180_hw_dig_wq);
2762 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,
2763 (void *)rtl8180_tx_pw_wq);
2764 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,
2765 (void *) GPIOChangeRFWorkItemCallBack);
c8d86be3
GKH
2766 tasklet_init(&priv->irq_rx_tasklet,
2767 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet,
2768 (unsigned long)priv);
fd882783 2769
1994130e 2770 init_timer(&priv->watch_dog_timer);
c8d86be3
GKH
2771 priv->watch_dog_timer.data = (unsigned long)dev;
2772 priv->watch_dog_timer.function = watch_dog_adaptive;
c8d86be3 2773
1994130e
LF
2774 init_timer(&priv->rateadapter_timer);
2775 priv->rateadapter_timer.data = (unsigned long)dev;
2776 priv->rateadapter_timer.function = timer_rate_adaptive;
2777 priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD;
2778 priv->bEnhanceTxPwr = false;
c8d86be3
GKH
2779
2780 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit;
2781 priv->ieee80211->set_chan = rtl8180_set_chan;
2782 priv->ieee80211->link_change = rtl8180_link_change;
2783 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit;
2784 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop;
2785 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume;
2786
2787 priv->ieee80211->init_wmmparam_flag = 0;
2788
2789 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon;
2790 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable;
2791 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
2792
c8d86be3
GKH
2793 priv->MWIEnable = 0;
2794
2795 priv->ShortRetryLimit = 7;
2796 priv->LongRetryLimit = 7;
2797 priv->EarlyRxThreshold = 7;
2798
2799 priv->CSMethod = (0x01 << 29);
2800
1994130e
LF
2801 priv->TransmitConfig = TCR_DurProcMode_OFFSET |
2802 (7<<TCR_MXDMA_OFFSET) |
2803 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) |
2804 (priv->LongRetryLimit<<TCR_LRL_OFFSET) |
2805 (0 ? TCR_SAT : 0);
2806
2807 priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF |
2808 RCR_AB | RCR_AM | RCR_APM |
2809 (7<<RCR_MXDMA_OFFSET) |
2810 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) |
2811 (priv->EarlyRxThreshold == 7 ?
2812 RCR_ONLYERLPKT : 0);
c8d86be3
GKH
2813
2814 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER |
1994130e
LF
2815 IMR_THPDER | IMR_THPDOK |
2816 IMR_TVODER | IMR_TVODOK |
2817 IMR_TVIDER | IMR_TVIDOK |
2818 IMR_TBEDER | IMR_TBEDOK |
2819 IMR_TBKDER | IMR_TBKDOK |
2820 IMR_RDU |
2821 IMR_RER | IMR_ROK |
2822 IMR_RQoSOK;
c8d86be3
GKH
2823
2824 priv->InitialGain = 6;
c8d86be3 2825
d44eb889
LF
2826 DMESG("MAC controller is a RTL8187SE b/g");
2827 priv->phy_ver = 2;
c8d86be3 2828
d44eb889
LF
2829 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION;
2830 priv->ieee80211->short_slot = 1;
c8d86be3 2831
c8d86be3 2832 // just for sync 85
c8d86be3
GKH
2833 priv->enable_gpio0 = 0;
2834
742821ce
LF
2835 eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val);
2836 usValue = eeprom_val;
c8d86be3 2837 DMESG("usValue is 0x%x\n",usValue);
c8d86be3 2838 //3Read AntennaDiversity
fd882783 2839
c8d86be3 2840 // SW Antenna Diversity.
fd882783 2841 if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE)
c8d86be3 2842 priv->EEPROMSwAntennaDiversity = false;
c8d86be3 2843 else
c8d86be3 2844 priv->EEPROMSwAntennaDiversity = true;
fd882783 2845
c8d86be3 2846 // Default Antenna to use.
fd882783 2847 if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1)
c8d86be3 2848 priv->EEPROMDefaultAntenna1 = false;
c8d86be3 2849 else
c8d86be3 2850 priv->EEPROMDefaultAntenna1 = true;
c8d86be3 2851
c8d86be3 2852 if( priv->RegSwAntennaDiversityMechanism == 0 ) // Auto
fd882783 2853 /* 0: default from EEPROM. */
c8d86be3 2854 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity;
c8d86be3 2855 else
fd882783 2856 /* 1:disable antenna diversity, 2: enable antenna diversity. */
c8d86be3 2857 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1)? false : true);
c8d86be3 2858
fd882783
BZ
2859 if (priv->RegDefaultAntenna == 0)
2860 /* 0: default from EEPROM. */
c8d86be3 2861 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1;
c8d86be3 2862 else
fd882783 2863 /* 1: main, 2: aux. */
c8d86be3 2864 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna== 2) ? true : false);
fd882783 2865
c8d86be3
GKH
2866 /* rtl8185 can calc plcp len in HW.*/
2867 priv->hw_plcp_len = 1;
2868
2869 priv->plcp_preamble_mode = 2;
2870 /*the eeprom type is stored in RCR register bit #6 */
fd882783 2871 if (RCR_9356SEL & read_nic_dword(dev, RCR))
c8d86be3 2872 priv->epromtype=EPROM_93c56;
fd882783 2873 else
c8d86be3 2874 priv->epromtype=EPROM_93c46;
c8d86be3 2875
742821ce
LF
2876 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)
2877 dev->dev_addr, 3);
c8d86be3
GKH
2878
2879 for(i=1,j=0; i<14; i+=2,j++){
742821ce 2880 eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word);
c8d86be3
GKH
2881 priv->chtxpwr[i]=word & 0xff;
2882 priv->chtxpwr[i+1]=(word & 0xff00)>>8;
c8d86be3 2883 }
d44eb889 2884 for (i = 1, j = 0; i < 14; i += 2, j++) {
742821ce 2885 eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word);
d44eb889 2886 priv->chtxpwr_ofdm[i] = word & 0xff;
1994130e 2887 priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8;
c8d86be3 2888 }
fd882783 2889
1994130e 2890 /* 3Read crystal calibtration and thermal meter indication on 87SE. */
742821ce 2891 eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16);
c8d86be3 2892
1994130e
LF
2893 /* Crystal calibration for Xin and Xout resp. */
2894 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK;
2895 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4;
2896 if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12)
2897 priv->bXtalCalibration = true;
c8d86be3 2898
1994130e
LF
2899 /* Thermal meter reference indication. */
2900 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8);
2901 if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13)
2902 priv->bTxPowerTrack = true;
c8d86be3 2903
742821ce 2904 eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word);
c8d86be3
GKH
2905 priv->cck_txpwr_base = word & 0xf;
2906 priv->ofdm_txpwr_base = (word>>4) & 0xf;
c8d86be3 2907
742821ce 2908 eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version);
c8d86be3 2909 DMESG("EEPROM version %x",version);
d44eb889 2910 priv->rcr_csense = 3;
c8d86be3 2911
742821ce
LF
2912 eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val);
2913 priv->cs_treshold = (eeprom_val & 0xff00) >> 8;
c8d86be3 2914
742821ce 2915 eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val);
c8d86be3
GKH
2916 priv->rf_sleep = rtl8225z4_rf_sleep;
2917 priv->rf_wakeup = rtl8225z4_rf_wakeup;
c8d86be3
GKH
2918 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!");
2919
2920 priv->rf_close = rtl8225z2_rf_close;
2921 priv->rf_init = rtl8225z2_rf_init;
2922 priv->rf_set_chan = rtl8225z2_rf_set_chan;
2923 priv->rf_set_sens = NULL;
c8d86be3 2924
c8d86be3
GKH
2925 if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount))
2926 return -ENOMEM;
2927
2928 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2929 TX_MANAGEPRIORITY_RING_ADDR))
2930 return -ENOMEM;
2931
2932 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2933 TX_BKPRIORITY_RING_ADDR))
2934 return -ENOMEM;
2935
2936 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2937 TX_BEPRIORITY_RING_ADDR))
2938 return -ENOMEM;
2939
2940 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2941 TX_VIPRIORITY_RING_ADDR))
2942 return -ENOMEM;
2943
2944 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2945 TX_VOPRIORITY_RING_ADDR))
2946 return -ENOMEM;
2947
2948 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2949 TX_HIGHPRIORITY_RING_ADDR))
2950 return -ENOMEM;
2951
2952 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount,
2953 TX_BEACON_RING_ADDR))
2954 return -ENOMEM;
2955
c8d86be3 2956 if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){
c8d86be3
GKH
2957 DMESGE("Error allocating IRQ %d",dev->irq);
2958 return -1;
2959 }else{
2960 priv->irq=dev->irq;
2961 DMESG("IRQ %d",dev->irq);
2962 }
2963
c8d86be3 2964 return 0;
c8d86be3
GKH
2965}
2966
c8d86be3
GKH
2967void rtl8180_no_hw_wep(struct net_device *dev)
2968{
c8d86be3
GKH
2969}
2970
c8d86be3
GKH
2971void rtl8180_set_hw_wep(struct net_device *dev)
2972{
2973 struct r8180_priv *priv = ieee80211_priv(dev);
2974 u8 pgreg;
2975 u8 security;
2976 u32 key0_word4;
2977
2978 pgreg=read_nic_byte(dev, PGSELECT);
2979 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
2980
2981 key0_word4 = read_nic_dword(dev, KEY0+4+4+4);
2982 key0_word4 &= ~ 0xff;
2983 key0_word4 |= priv->key0[3]& 0xff;
2984 write_nic_dword(dev,KEY0,(priv->key0[0]));
2985 write_nic_dword(dev,KEY0+4,(priv->key0[1]));
2986 write_nic_dword(dev,KEY0+4+4,(priv->key0[2]));
2987 write_nic_dword(dev,KEY0+4+4+4,(key0_word4));
2988
c8d86be3
GKH
2989 security = read_nic_byte(dev,SECURITY);
2990 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT);
2991 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT);
2992 security &= ~ SECURITY_ENCRYP_MASK;
2993 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT);
2994
2995 write_nic_byte(dev, SECURITY, security);
2996
2997 DMESG("key %x %x %x %x",read_nic_dword(dev,KEY0+4+4+4),
2998 read_nic_dword(dev,KEY0+4+4),read_nic_dword(dev,KEY0+4),
2999 read_nic_dword(dev,KEY0));
c8d86be3
GKH
3000}
3001
3002
3003void rtl8185_rf_pins_enable(struct net_device *dev)
3004{
3005// u16 tmp;
3006// tmp = read_nic_word(dev, RFPinsEnable);
3007 write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp);
c8d86be3
GKH
3008}
3009
c8d86be3
GKH
3010void rtl8185_set_anaparam2(struct net_device *dev, u32 a)
3011{
3012 u8 conf3;
3013
3014 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3015
3016 conf3 = read_nic_byte(dev, CONFIG3);
3017 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3018 write_nic_dword(dev, ANAPARAM2, a);
3019
3020 conf3 = read_nic_byte(dev, CONFIG3);
3021 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3022 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
3023}
3024
c8d86be3
GKH
3025void rtl8180_set_anaparam(struct net_device *dev, u32 a)
3026{
3027 u8 conf3;
3028
3029 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3030
3031 conf3 = read_nic_byte(dev, CONFIG3);
3032 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3033 write_nic_dword(dev, ANAPARAM, a);
3034
3035 conf3 = read_nic_byte(dev, CONFIG3);
3036 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3037 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3038}
3039
c8d86be3
GKH
3040void rtl8185_tx_antenna(struct net_device *dev, u8 ant)
3041{
3042 write_nic_byte(dev, TX_ANTENNA, ant);
3043 force_pci_posting(dev);
3044 mdelay(1);
3045}
3046
c8d86be3
GKH
3047void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data)
3048{
c8d86be3 3049 u32 phyw;
c8d86be3
GKH
3050
3051 adr |= 0x80;
3052
3053 phyw= ((data<<8) | adr);
c8d86be3 3054
c8d86be3
GKH
3055 // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register.
3056 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24));
3057 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16));
3058 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8));
3059 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff) ));
5521a513 3060
c8d86be3
GKH
3061 /* this is ok to fail when we write AGC table. check for AGC table might be
3062 * done by masking with 0x7f instead of 0xff
3063 */
3064 //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr);
3065}
3066
c8d86be3
GKH
3067inline void write_phy_ofdm (struct net_device *dev, u8 adr, u32 data)
3068{
3069 data = data & 0xff;
3070 rtl8185_write_phy(dev, adr, data);
3071}
3072
c8d86be3
GKH
3073void write_phy_cck (struct net_device *dev, u8 adr, u32 data)
3074{
3075 data = data & 0xff;
3076 rtl8185_write_phy(dev, adr, data | 0x10000);
3077}
3078
c8d86be3
GKH
3079void rtl8185_set_rate(struct net_device *dev)
3080{
3081 int i;
3082 u16 word;
3083 int basic_rate,min_rr_rate,max_rr_rate;
3084
c8d86be3
GKH
3085 basic_rate = ieeerate2rtlrate(240);
3086 min_rr_rate = ieeerate2rtlrate(60);
3087 max_rr_rate = ieeerate2rtlrate(240);
3088
c8d86be3
GKH
3089 write_nic_byte(dev, RESP_RATE,
3090 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3091
3092 word = read_nic_word(dev, BRSR);
3093 word &= ~BRSR_MBR_8185;
3094
c8d86be3
GKH
3095 for(i=0;i<=basic_rate;i++)
3096 word |= (1<<i);
3097
3098 write_nic_word(dev, BRSR, word);
c8d86be3
GKH
3099}
3100
c8d86be3
GKH
3101void rtl8180_adapter_start(struct net_device *dev)
3102{
3103 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
3104
3105 rtl8180_rtx_disable(dev);
3106 rtl8180_reset(dev);
3107
c8d86be3
GKH
3108 /* enable beacon timeout, beacon TX ok and err
3109 * LP tx ok and err, HP TX ok and err, NP TX ok and err,
3110 * RX ok and ERR, and GP timer */
3111 priv->irq_mask = 0x6fcf;
3112
3113 priv->dma_poll_mask = 0;
3114
3115 rtl8180_beacon_tx_disable(dev);
3116
c8d86be3
GKH
3117 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3118 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
3119 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
3120 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3121
3122 rtl8180_update_msr(dev);
3123
c8d86be3
GKH
3124 /* These might be unnecessary since we do in rx_enable / tx_enable */
3125 fix_rx_fifo(dev);
3126 fix_tx_fifo(dev);
c8d86be3
GKH
3127
3128 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3129
3130 /*
3131 The following is very strange. seems to be that 1 means test mode,
3132 but we need to acknolwledges the nic when a packet is ready
bbc9a991 3133 although we set it to 0
c8d86be3
GKH
3134 */
3135
3136 write_nic_byte(dev,
3137 CONFIG2, read_nic_byte(dev,CONFIG2) &~\
3138 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT));
3139 //^the nic isn't in test mode
d44eb889 3140 write_nic_byte(dev,
c8d86be3
GKH
3141 CONFIG2, read_nic_byte(dev,CONFIG2)|(1<<4));
3142
3143 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3144
3145 write_nic_dword(dev,INT_TIMEOUT,0);
c8d86be3 3146
d44eb889 3147 write_nic_byte(dev, WPA_CONFIG, 0);
c8d86be3
GKH
3148
3149 rtl8180_no_hw_wep(dev);
3150
d44eb889
LF
3151 rtl8185_set_rate(dev);
3152 write_nic_byte(dev, RATE_FALLBACK, 0x81);
c8d86be3 3153
d44eb889 3154 write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6));
c8d86be3 3155
d44eb889
LF
3156 /*FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */
3157 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3158 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3)
3159 | (1 << CONFIG3_CLKRUN_SHIFT));
3160 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
3161
3162 priv->rf_init(dev);
3163
3164 if(priv->rf_set_sens != NULL)
3165 priv->rf_set_sens(dev,priv->sens);
3166 rtl8180_irq_enable(dev);
3167
3168 netif_start_queue(dev);
c8d86be3
GKH
3169}
3170
c8d86be3
GKH
3171/* this configures registers for beacon tx and enables it via
3172 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might
3173 * be used to stop beacon transmission
3174 */
3175void rtl8180_start_tx_beacon(struct net_device *dev)
3176{
c8d86be3 3177 u16 word;
c8d86be3
GKH
3178
3179 DMESG("Enabling beacon TX");
c8d86be3
GKH
3180 rtl8180_prepare_beacon(dev);
3181 rtl8180_irq_disable(dev);
3182 rtl8180_beacon_tx_enable(dev);
c8d86be3 3183
c8d86be3
GKH
3184 word = read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd;
3185 write_nic_word(dev, AtimWnd,word);// word |=
c8d86be3
GKH
3186
3187 word = read_nic_word(dev, BintrItv);
3188 word &= ~BintrItv_BintrItv;
3189 word |= 1000;/*priv->ieee80211->current_network.beacon_interval *
3190 ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
3191 // FIXME: check if correct ^^ worked with 0x3e8;
3192 */
3193 write_nic_word(dev, BintrItv, word);
3194
c8d86be3
GKH
3195 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3196
c8d86be3 3197 rtl8185b_irq_enable(dev);
c8d86be3
GKH
3198}
3199
c8d86be3
GKH
3200static struct net_device_stats *rtl8180_stats(struct net_device *dev)
3201{
3202 struct r8180_priv *priv = ieee80211_priv(dev);
3203
3204 return &priv->ieee80211->stats;
3205}
3206//
3207// Change current and default preamble mode.
c8d86be3
GKH
3208//
3209bool
3210MgntActSet_802_11_PowerSaveMode(
3211 struct r8180_priv *priv,
3212 RT_PS_MODE rtPsMode
3213)
3214{
c8d86be3
GKH
3215 // Currently, we do not change power save mode on IBSS mode.
3216 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3 3217 return false;
c8d86be3 3218
c8d86be3 3219 priv->ieee80211->ps = rtPsMode;
5521a513 3220
c8d86be3
GKH
3221 return true;
3222}
3223
fd882783 3224void LeisurePSEnter(struct r8180_priv *priv)
c8d86be3 3225{
fd882783 3226 if (priv->bLeisurePs) {
c8d86be3 3227 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED)
c8d86be3 3228 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE
c8d86be3
GKH
3229 }
3230}
3231
fd882783 3232void LeisurePSLeave(struct r8180_priv *priv)
c8d86be3 3233{
fd882783 3234 if (priv->bLeisurePs) {
c8d86be3 3235 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED)
c8d86be3 3236 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
c8d86be3
GKH
3237 }
3238}
0370453f 3239
c8d86be3
GKH
3240void rtl8180_hw_wakeup_wq (struct work_struct *work)
3241{
bf6aede7 3242 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH
3243 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
3244 struct net_device *dev = ieee->dev;
c8d86be3 3245
c8d86be3 3246 rtl8180_hw_wakeup(dev);
c8d86be3
GKH
3247}
3248
c8d86be3
GKH
3249void rtl8180_hw_sleep_wq (struct work_struct *work)
3250{
bf6aede7 3251 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH
3252 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
3253 struct net_device *dev = ieee->dev;
c8d86be3
GKH
3254
3255 rtl8180_hw_sleep_down(dev);
3256}
3257
c8d86be3
GKH
3258static void MgntLinkKeepAlive(struct r8180_priv *priv )
3259{
3260 if (priv->keepAliveLevel == 0)
3261 return;
3262
3263 if(priv->ieee80211->state == IEEE80211_LINKED)
3264 {
3265 //
3266 // Keep-Alive.
3267 //
c8d86be3
GKH
3268
3269 if ( (priv->keepAliveLevel== 2) ||
3270 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast &&
3271 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast )
3272 )
3273 {
3274 priv->link_detect.IdleCount++;
3275
3276 //
3277 // Send a Keep-Alive packet packet to AP if we had been idle for a while.
3278 //
3279 if(priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1) )
3280 {
3281 priv->link_detect.IdleCount = 0;
3282 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false);
3283 }
3284 }
3285 else
3286 {
3287 priv->link_detect.IdleCount = 0;
3288 }
3289 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast;
3290 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast;
3291 }
3292}
c8d86be3
GKH
3293
3294static u8 read_acadapter_file(char *filename);
fd882783 3295
c8d86be3
GKH
3296void rtl8180_watch_dog(struct net_device *dev)
3297{
3298 struct r8180_priv *priv = ieee80211_priv(dev);
3299 bool bEnterPS = false;
3300 bool bBusyTraffic = false;
3301 u32 TotalRxNum = 0;
3302 u16 SlotIndex = 0;
3303 u16 i = 0;
c8d86be3
GKH
3304 if(priv->ieee80211->actscanning == false){
3305 if((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)){
3306 IPSEnter(dev);
3307 }
3308 }
c8d86be3
GKH
3309 //YJ,add,080828,for link state check
3310 if((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)){
3311 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum;
3312 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod;
3313 for( i=0; i<priv->link_detect.SlotNum; i++ )
3314 TotalRxNum+= priv->link_detect.RxFrameNum[i];
fd882783 3315
c8d86be3
GKH
3316 if(TotalRxNum == 0){
3317 priv->ieee80211->state = IEEE80211_ASSOCIATING;
3318 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
3319 }
3320 }
3321
3322 //YJ,add,080828,for KeepAlive
3323 MgntLinkKeepAlive(priv);
3324
3325 //YJ,add,080828,for LPS
fd882783 3326 if (priv->PowerProfile == POWER_PROFILE_BATTERY)
c8d86be3 3327 priv->bLeisurePs = true;
fd882783 3328 else if (priv->PowerProfile == POWER_PROFILE_AC) {
c8d86be3
GKH
3329 LeisurePSLeave(priv);
3330 priv->bLeisurePs= false;
3331 }
c8d86be3 3332
c8d86be3
GKH
3333 if(priv->ieee80211->state == IEEE80211_LINKED){
3334 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod;
c8d86be3
GKH
3335 if( priv->link_detect.NumRxOkInPeriod> 666 ||
3336 priv->link_detect.NumTxOkInPeriod> 666 ) {
3337 bBusyTraffic = true;
3338 }
3339 if(((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8)
3340 || (priv->link_detect.NumRxOkInPeriod > 2)) {
3341 bEnterPS= false;
fd882783 3342 } else
c8d86be3 3343 bEnterPS= true;
c8d86be3 3344
fd882783 3345 if (bEnterPS)
c8d86be3 3346 LeisurePSEnter(priv);
fd882783 3347 else
c8d86be3 3348 LeisurePSLeave(priv);
fd882783 3349 } else
c8d86be3 3350 LeisurePSLeave(priv);
c8d86be3
GKH
3351 priv->link_detect.bBusyTraffic = bBusyTraffic;
3352 priv->link_detect.NumRxOkInPeriod = 0;
3353 priv->link_detect.NumTxOkInPeriod = 0;
3354 priv->ieee80211->NumRxDataInPeriod = 0;
3355 priv->ieee80211->NumRxBcnInPeriod = 0;
c8d86be3 3356}
fd882783 3357
c8d86be3
GKH
3358int _rtl8180_up(struct net_device *dev)
3359{
3360 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
3361
3362 priv->up=1;
3363
3364 DMESG("Bringing up iface");
c8d86be3
GKH
3365 rtl8185b_adapter_start(dev);
3366 rtl8185b_rx_enable(dev);
3367 rtl8185b_tx_enable(dev);
c8d86be3
GKH
3368 if(priv->bInactivePs){
3369 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
3370 IPSLeave(dev);
3371 }
c8d86be3 3372 timer_rate_adaptive((unsigned long)dev);
c8d86be3 3373 watch_dog_adaptive((unsigned long)dev);
c8d86be3
GKH
3374 if(priv->bSwAntennaDiverity)
3375 SwAntennaDiversityTimerCallback(dev);
c8d86be3 3376 ieee80211_softmac_start_protocol(priv->ieee80211);
c8d86be3
GKH
3377 return 0;
3378}
3379
c8d86be3
GKH
3380int rtl8180_open(struct net_device *dev)
3381{
3382 struct r8180_priv *priv = ieee80211_priv(dev);
3383 int ret;
3384
3385 down(&priv->wx_sem);
3386 ret = rtl8180_up(dev);
3387 up(&priv->wx_sem);
3388 return ret;
c8d86be3
GKH
3389}
3390
c8d86be3
GKH
3391int rtl8180_up(struct net_device *dev)
3392{
3393 struct r8180_priv *priv = ieee80211_priv(dev);
3394
3395 if (priv->up == 1) return -1;
3396
3397 return _rtl8180_up(dev);
3398}
3399
c8d86be3
GKH
3400int rtl8180_close(struct net_device *dev)
3401{
3402 struct r8180_priv *priv = ieee80211_priv(dev);
3403 int ret;
3404
3405 down(&priv->wx_sem);
3406 ret = rtl8180_down(dev);
3407 up(&priv->wx_sem);
3408
3409 return ret;
c8d86be3
GKH
3410}
3411
3412int rtl8180_down(struct net_device *dev)
3413{
3414 struct r8180_priv *priv = ieee80211_priv(dev);
3415
fd882783
BZ
3416 if (priv->up == 0)
3417 return -1;
c8d86be3
GKH
3418
3419 priv->up=0;
3420
3421 ieee80211_softmac_stop_protocol(priv->ieee80211);
3422 /* FIXME */
3423 if (!netif_queue_stopped(dev))
3424 netif_stop_queue(dev);
3425 rtl8180_rtx_disable(dev);
3426 rtl8180_irq_disable(dev);
3427 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ
3428 del_timer_sync(&priv->rateadapter_timer);
3429 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH
3430 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3431 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3432 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3433 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3434 del_timer_sync(&priv->SwAntennaDiversityTimer);
3435 SetZebraRFPowerState8185(dev,eRfOff);
c8d86be3
GKH
3436 memset(&(priv->ieee80211->current_network),0,sizeof(struct ieee80211_network));
3437 priv->ieee80211->state = IEEE80211_NOLINK;
3438 return 0;
3439}
3440
c8d86be3
GKH
3441void rtl8180_restart_wq(struct work_struct *work)
3442{
3443 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
3444 struct net_device *dev = priv->dev;
0370453f 3445
c8d86be3
GKH
3446 down(&priv->wx_sem);
3447
3448 rtl8180_commit(dev);
3449
3450 up(&priv->wx_sem);
3451}
3452
3453void rtl8180_restart(struct net_device *dev)
3454{
3455 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 3456
c8d86be3 3457 schedule_work(&priv->reset_wq);
c8d86be3
GKH
3458}
3459
c8d86be3
GKH
3460void rtl8180_commit(struct net_device *dev)
3461{
3462 struct r8180_priv *priv = ieee80211_priv(dev);
3463
fd882783
BZ
3464 if (priv->up == 0)
3465 return ;
3466
c8d86be3 3467 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ
3468 del_timer_sync(&priv->rateadapter_timer);
3469 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH
3470 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3471 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3472 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3473 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3474 del_timer_sync(&priv->SwAntennaDiversityTimer);
3475 ieee80211_softmac_stop_protocol(priv->ieee80211);
3476 rtl8180_irq_disable(dev);
3477 rtl8180_rtx_disable(dev);
3478 _rtl8180_up(dev);
3479}
3480
c8d86be3
GKH
3481static void r8180_set_multicast(struct net_device *dev)
3482{
3483 struct r8180_priv *priv = ieee80211_priv(dev);
3484 short promisc;
3485
c8d86be3
GKH
3486 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
3487
3488 if (promisc != priv->promisc)
3489 rtl8180_restart(dev);
3490
3491 priv->promisc = promisc;
c8d86be3
GKH
3492}
3493
c8d86be3
GKH
3494int r8180_set_mac_adr(struct net_device *dev, void *mac)
3495{
3496 struct r8180_priv *priv = ieee80211_priv(dev);
3497 struct sockaddr *addr = mac;
3498
3499 down(&priv->wx_sem);
3500
3501 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3502
3503 if(priv->ieee80211->iw_mode == IW_MODE_MASTER)
3504 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN);
3505
3506 if (priv->up) {
3507 rtl8180_down(dev);
3508 rtl8180_up(dev);
3509 }
3510
3511 up(&priv->wx_sem);
3512
3513 return 0;
3514}
3515
3516/* based on ipw2200 driver */
3517int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3518{
3519 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
3520 struct iwreq *wrq = (struct iwreq *) rq;
3521 int ret=-1;
fd882783 3522
c8d86be3 3523 switch (cmd) {
fd882783 3524 case RTL_IOCTL_WPA_SUPPLICANT:
c8d86be3
GKH
3525 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
3526 return ret;
fd882783 3527 default:
c8d86be3
GKH
3528 return -EOPNOTSUPP;
3529 }
3530
3531 return -EOPNOTSUPP;
3532}
3533
727ae303
AB
3534static const struct net_device_ops rtl8180_netdev_ops = {
3535 .ndo_open = rtl8180_open,
3536 .ndo_stop = rtl8180_close,
3537 .ndo_get_stats = rtl8180_stats,
3538 .ndo_tx_timeout = rtl8180_restart,
3539 .ndo_do_ioctl = rtl8180_ioctl,
3540 .ndo_set_multicast_list = r8180_set_multicast,
3541 .ndo_set_mac_address = r8180_set_mac_adr,
3542 .ndo_validate_addr = eth_validate_addr,
3543 .ndo_change_mtu = eth_change_mtu,
df574b8e 3544 .ndo_start_xmit = ieee80211_rtl_xmit,
727ae303 3545};
c8d86be3
GKH
3546
3547static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
3548 const struct pci_device_id *id)
3549{
3550 unsigned long ioaddr = 0;
3551 struct net_device *dev = NULL;
3552 struct r8180_priv *priv= NULL;
c8d86be3
GKH
3553 u8 unit = 0;
3554
c8d86be3 3555 unsigned long pmem_start, pmem_len, pmem_flags;
c8d86be3
GKH
3556
3557 DMESG("Configuring chip resources");
3558
3559 if( pci_enable_device (pdev) ){
3560 DMESG("Failed to enable PCI device");
3561 return -EIO;
3562 }
3563
3564 pci_set_master(pdev);
c8d86be3
GKH
3565 pci_set_dma_mask(pdev, 0xffffff00ULL);
3566 pci_set_consistent_dma_mask(pdev,0xffffff00ULL);
3567 dev = alloc_ieee80211(sizeof(struct r8180_priv));
3568 if (!dev)
3569 return -ENOMEM;
3570 priv = ieee80211_priv(dev);
3571 priv->ieee80211 = netdev_priv(dev);
3572
c8d86be3
GKH
3573 pci_set_drvdata(pdev, dev);
3574 SET_NETDEV_DEV(dev, &pdev->dev);
3575
3576 priv = ieee80211_priv(dev);
fd882783 3577 priv->pdev = pdev;
c8d86be3
GKH
3578
3579 pmem_start = pci_resource_start(pdev, 1);
3580 pmem_len = pci_resource_len(pdev, 1);
3581 pmem_flags = pci_resource_flags (pdev, 1);
3582
3583 if (!(pmem_flags & IORESOURCE_MEM)) {
3584 DMESG("region #1 not a MMIO resource, aborting");
3585 goto fail;
3586 }
3587
c8d86be3
GKH
3588 if( ! request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) {
3589 DMESG("request_mem_region failed!");
3590 goto fail;
3591 }
3592
c8d86be3
GKH
3593 ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len);
3594 if( ioaddr == (unsigned long)NULL ){
3595 DMESG("ioremap failed!");
c8d86be3
GKH
3596 goto fail1;
3597 }
3598
3599 dev->mem_start = ioaddr; // shared mem start
3600 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
3601
c8d86be3
GKH
3602 pci_read_config_byte(pdev, 0x05, &unit);
3603 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
c8d86be3
GKH
3604
3605 dev->irq = pdev->irq;
3606 priv->irq = 0;
3607
727ae303 3608 dev->netdev_ops = &rtl8180_netdev_ops;
c8d86be3 3609 dev->wireless_handlers = &r8180_wx_handlers_def;
c8d86be3 3610
c8d86be3 3611 dev->type=ARPHRD_ETHER;
1994130e 3612 dev->watchdog_timeo = HZ*3;
c8d86be3
GKH
3613
3614 if (dev_alloc_name(dev, ifname) < 0){
3615 DMESG("Oops: devname already taken! Trying wlan%%d...\n");
3616 ifname = "wlan%d";
c8d86be3
GKH
3617 dev_alloc_name(dev, ifname);
3618 }
3619
c8d86be3
GKH
3620 if(rtl8180_init(dev)!=0){
3621 DMESG("Initialization failed");
3622 goto fail1;
3623 }
3624
3625 netif_carrier_off(dev);
3626
3627 register_netdev(dev);
3628
3629 rtl8180_proc_init_one(dev);
3630
3631 DMESG("Driver probe completed\n");
3632 return 0;
c8d86be3 3633fail1:
c8d86be3
GKH
3634 if( dev->mem_start != (unsigned long)NULL ){
3635 iounmap( (void *)dev->mem_start );
3636 release_mem_region( pci_resource_start(pdev, 1),
3637 pci_resource_len(pdev, 1) );
3638 }
c8d86be3
GKH
3639fail:
3640 if(dev){
c8d86be3
GKH
3641 if (priv->irq) {
3642 free_irq(dev->irq, dev);
3643 dev->irq=0;
3644 }
3645 free_ieee80211(dev);
3646 }
3647
3648 pci_disable_device(pdev);
3649
3650 DMESG("wlan driver load failed\n");
3651 pci_set_drvdata(pdev, NULL);
3652 return -ENODEV;
c8d86be3
GKH
3653}
3654
c8d86be3
GKH
3655static void __devexit rtl8180_pci_remove(struct pci_dev *pdev)
3656{
3657 struct r8180_priv *priv;
3658 struct net_device *dev = pci_get_drvdata(pdev);
c8d86be3 3659
fd882783 3660 if (dev) {
c8d86be3
GKH
3661 unregister_netdev(dev);
3662
fd882783 3663 priv = ieee80211_priv(dev);
c8d86be3
GKH
3664
3665 rtl8180_proc_remove_one(dev);
3666 rtl8180_down(dev);
3667 priv->rf_close(dev);
3668 rtl8180_reset(dev);
c8d86be3 3669 mdelay(10);
c8d86be3
GKH
3670
3671 if(priv->irq){
c8d86be3
GKH
3672 DMESG("Freeing irq %d",dev->irq);
3673 free_irq(dev->irq, dev);
3674 priv->irq=0;
c8d86be3
GKH
3675 }
3676
3677 free_rx_desc_ring(dev);
3678 free_tx_desc_rings(dev);
c8d86be3 3679
c8d86be3
GKH
3680 if( dev->mem_start != (unsigned long)NULL ){
3681 iounmap( (void *)dev->mem_start );
3682 release_mem_region( pci_resource_start(pdev, 1),
3683 pci_resource_len(pdev, 1) );
3684 }
c8d86be3
GKH
3685
3686 free_ieee80211(dev);
3687 }
3688 pci_disable_device(pdev);
3689
3690 DMESG("wlan driver removed\n");
3691}
3692
c8d86be3
GKH
3693/* fun with the built-in ieee80211 stack... */
3694extern int ieee80211_crypto_init(void);
3695extern void ieee80211_crypto_deinit(void);
3696extern int ieee80211_crypto_tkip_init(void);
3697extern void ieee80211_crypto_tkip_exit(void);
3698extern int ieee80211_crypto_ccmp_init(void);
3699extern void ieee80211_crypto_ccmp_exit(void);
3700extern int ieee80211_crypto_wep_init(void);
3701extern void ieee80211_crypto_wep_exit(void);
3702
3703static int __init rtl8180_pci_module_init(void)
3704{
3705 int ret;
3706
3707 ret = ieee80211_crypto_init();
3708 if (ret) {
3709 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret);
3710 return ret;
3711 }
3712 ret = ieee80211_crypto_tkip_init();
3713 if (ret) {
3714 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret);
3715 return ret;
3716 }
3717 ret = ieee80211_crypto_ccmp_init();
3718 if (ret) {
3719 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret);
3720 return ret;
3721 }
3722 ret = ieee80211_crypto_wep_init();
3723 if (ret) {
3724 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret);
3725 return ret;
3726 }
3727
bc568942 3728 printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n");
c8d86be3
GKH
3729 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n");
3730 DMESG("Initializing module");
3731 DMESG("Wireless extensions version %d", WIRELESS_EXT);
3732 rtl8180_proc_module_init();
3733
fd882783 3734 if (pci_register_driver(&rtl8180_pci_driver)) {
c8d86be3 3735 DMESG("No device found");
c8d86be3
GKH
3736 return -ENODEV;
3737 }
3738 return 0;
3739}
3740
c8d86be3
GKH
3741static void __exit rtl8180_pci_module_exit(void)
3742{
3743 pci_unregister_driver (&rtl8180_pci_driver);
3744 rtl8180_proc_module_remove();
c8d86be3
GKH
3745 ieee80211_crypto_tkip_exit();
3746 ieee80211_crypto_ccmp_exit();
3747 ieee80211_crypto_wep_exit();
096c55d1 3748 ieee80211_crypto_deinit();
c8d86be3
GKH
3749 DMESG("Exiting");
3750}
3751
c8d86be3
GKH
3752void rtl8180_try_wake_queue(struct net_device *dev, int pri)
3753{
3754 unsigned long flags;
3755 short enough_desc;
3756 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3757
3758 spin_lock_irqsave(&priv->tx_lock,flags);
3759 enough_desc = check_nic_enought_desc(dev,pri);
3760 spin_unlock_irqrestore(&priv->tx_lock,flags);
3761
3762 if(enough_desc)
df574b8e 3763 ieee80211_rtl_wake_queue(priv->ieee80211);
c8d86be3
GKH
3764}
3765
c8d86be3
GKH
3766void rtl8180_tx_isr(struct net_device *dev, int pri,short error)
3767{
3768 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
3769 u32 *tail; //tail virtual addr
3770 u32 *head; //head virtual addr
3771 u32 *begin;//start of ring virtual addr
3772 u32 *nicv; //nic pointer virtual addr
c8d86be3
GKH
3773 u32 nic; //nic pointer physical addr
3774 u32 nicbegin;// start of ring physical addr
c8d86be3
GKH
3775 unsigned long flag;
3776 /* physical addr are ok on 32 bits since we set DMA mask*/
c8d86be3
GKH
3777 int offs;
3778 int j,i;
3779 int hd;
3780 if (error) priv->stats.txretry++; //tony 20060601
3781 spin_lock_irqsave(&priv->tx_lock,flag);
3782 switch(pri) {
3783 case MANAGE_PRIORITY:
3784 tail = priv->txmapringtail;
3785 begin = priv->txmapring;
3786 head = priv->txmapringhead;
3787 nic = read_nic_dword(dev,TX_MANAGEPRIORITY_RING_ADDR);
3788 nicbegin = priv->txmapringdma;
3789 break;
c8d86be3
GKH
3790 case BK_PRIORITY:
3791 tail = priv->txbkpringtail;
3792 begin = priv->txbkpring;
3793 head = priv->txbkpringhead;
3794 nic = read_nic_dword(dev,TX_BKPRIORITY_RING_ADDR);
3795 nicbegin = priv->txbkpringdma;
3796 break;
c8d86be3
GKH
3797 case BE_PRIORITY:
3798 tail = priv->txbepringtail;
3799 begin = priv->txbepring;
3800 head = priv->txbepringhead;
3801 nic = read_nic_dword(dev,TX_BEPRIORITY_RING_ADDR);
3802 nicbegin = priv->txbepringdma;
3803 break;
c8d86be3
GKH
3804 case VI_PRIORITY:
3805 tail = priv->txvipringtail;
3806 begin = priv->txvipring;
3807 head = priv->txvipringhead;
3808 nic = read_nic_dword(dev,TX_VIPRIORITY_RING_ADDR);
3809 nicbegin = priv->txvipringdma;
3810 break;
c8d86be3
GKH
3811 case VO_PRIORITY:
3812 tail = priv->txvopringtail;
3813 begin = priv->txvopring;
3814 head = priv->txvopringhead;
3815 nic = read_nic_dword(dev,TX_VOPRIORITY_RING_ADDR);
3816 nicbegin = priv->txvopringdma;
3817 break;
c8d86be3
GKH
3818 case HI_PRIORITY:
3819 tail = priv->txhpringtail;
3820 begin = priv->txhpring;
3821 head = priv->txhpringhead;
3822 nic = read_nic_dword(dev,TX_HIGHPRIORITY_RING_ADDR);
3823 nicbegin = priv->txhpringdma;
3824 break;
3825
3826 default:
3827 spin_unlock_irqrestore(&priv->tx_lock,flag);
3828 return ;
3829 }
fd882783 3830
c8d86be3
GKH
3831 nicv = (u32*) ((nic - nicbegin) + (u8*)begin);
3832 if((head <= tail && (nicv > tail || nicv < head)) ||
3833 (head > tail && (nicv > tail && nicv < head))){
c8d86be3 3834 DMESGW("nic has lost pointer");
c8d86be3
GKH
3835 spin_unlock_irqrestore(&priv->tx_lock,flag);
3836 rtl8180_restart(dev);
3837 return;
3838 }
3839
3840 /* we check all the descriptors between the head and the nic,
bbc9a991 3841 * but not the currently pointed by the nic (the next to be txed)
c8d86be3
GKH
3842 * and the previous of the pointed (might be in process ??)
3843 */
c8d86be3 3844 offs = (nic - nicbegin);
c8d86be3 3845 offs = offs / 8 /4;
c8d86be3
GKH
3846 hd = (head - begin) /8;
3847
3848 if(offs >= hd)
3849 j = offs - hd;
3850 else
3851 j = offs + (priv->txringcount -1 -hd);
c8d86be3
GKH
3852
3853 j-=2;
3854 if(j<0) j=0;
3855
c8d86be3
GKH
3856 for(i=0;i<j;i++)
3857 {
c8d86be3
GKH
3858 if((*head) & (1<<31))
3859 break;
3860 if(((*head)&(0x10000000)) != 0){
c8d86be3 3861 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff));
fd882783 3862 if (!error)
c8d86be3 3863 priv->NumTxOkTotal++;
c8d86be3 3864 }
fd882783
BZ
3865
3866 if (!error)
c8d86be3 3867 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff);
fd882783 3868
c8d86be3
GKH
3869 *head = *head &~ (1<<31);
3870
3871 if((head - begin)/8 == priv->txringcount-1)
3872 head=begin;
c8d86be3
GKH
3873 else
3874 head+=8;
3875 }
c8d86be3 3876
c8d86be3
GKH
3877 /* the head has been moved to the last certainly TXed
3878 * (or at least processed by the nic) packet.
3879 * The driver take forcefully owning of all these packets
3880 * If the packet previous of the nic pointer has been
3881 * processed this doesn't matter: it will be checked
3882 * here at the next round. Anyway if no more packet are
3883 * TXed no memory leak occour at all.
3884 */
3885
3886 switch(pri) {
3887 case MANAGE_PRIORITY:
3888 priv->txmapringhead = head;
fd882783 3889
c8d86be3 3890 if(priv->ack_tx_to_ieee){
c8d86be3 3891 if(rtl8180_is_tx_queue_empty(dev)){
c8d86be3
GKH
3892 priv->ack_tx_to_ieee = 0;
3893 ieee80211_ps_tx_ack(priv->ieee80211,!error);
3894 }
c8d86be3
GKH
3895 }
3896 break;
c8d86be3
GKH
3897 case BK_PRIORITY:
3898 priv->txbkpringhead = head;
3899 break;
c8d86be3
GKH
3900 case BE_PRIORITY:
3901 priv->txbepringhead = head;
3902 break;
c8d86be3
GKH
3903 case VI_PRIORITY:
3904 priv->txvipringhead = head;
3905 break;
c8d86be3
GKH
3906 case VO_PRIORITY:
3907 priv->txvopringhead = head;
3908 break;
c8d86be3
GKH
3909 case HI_PRIORITY:
3910 priv->txhpringhead = head;
3911 break;
3912 }
3913
c8d86be3 3914 spin_unlock_irqrestore(&priv->tx_lock,flag);
c8d86be3
GKH
3915}
3916
c8d86be3
GKH
3917void rtl8180_tx_irq_wq(struct work_struct *work)
3918{
bf6aede7 3919 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH
3920 struct ieee80211_device * ieee = (struct ieee80211_device*)
3921 container_of(dwork, struct ieee80211_device, watch_dog_wq);
3922 struct net_device *dev = ieee->dev;
0370453f 3923
c8d86be3
GKH
3924 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
3925}
3926irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs)
3927{
3928 struct net_device *dev = (struct net_device *) netdev;
3929 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3930 unsigned long flags;
3931 u32 inta;
3932
3933 /* We should return IRQ_NONE, but for now let me keep this */
3934 if(priv->irq_enabled == 0) return IRQ_HANDLED;
3935
3936 spin_lock_irqsave(&priv->irq_th_lock,flags);
3937
c8d86be3
GKH
3938 //ISR: 4bytes
3939 inta = read_nic_dword(dev, ISR);// & priv->IntrMask;
3940 write_nic_dword(dev,ISR,inta); // reset int situation
c8d86be3
GKH
3941
3942 priv->stats.shints++;
3943
c8d86be3
GKH
3944 if(!inta){
3945 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
3946 return IRQ_HANDLED;
3947 /*
3948 most probably we can safely return IRQ_NONE,
3949 but for now is better to avoid problems
3950 */
3951 }
3952
fd882783
BZ
3953 if (inta == 0xffff) {
3954 /* HW disappared */
3955 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
3956 return IRQ_HANDLED;
c8d86be3
GKH
3957 }
3958
3959 priv->stats.ints++;
c8d86be3
GKH
3960
3961 if(!netif_running(dev)) {
3962 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
3963 return IRQ_HANDLED;
3964 }
3965
fd882783 3966 if (inta & ISR_TimeOut)
c8d86be3 3967 write_nic_dword(dev, TimerInt, 0);
c8d86be3 3968
fd882783 3969 if (inta & ISR_TBDOK)
c8d86be3 3970 priv->stats.txbeacon++;
c8d86be3 3971
fd882783 3972 if (inta & ISR_TBDER)
c8d86be3 3973 priv->stats.txbeaconerr++;
c8d86be3 3974
fd882783 3975 if (inta & IMR_TMGDOK)
c8d86be3 3976 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
c8d86be3
GKH
3977
3978 if(inta & ISR_THPDER){
c8d86be3
GKH
3979 priv->stats.txhperr++;
3980 rtl8180_tx_isr(dev,HI_PRIORITY,1);
3981 priv->ieee80211->stats.tx_errors++;
3982 }
3983
3984 if(inta & ISR_THPDOK){ //High priority tx ok
c8d86be3
GKH
3985 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
3986 priv->stats.txhpokint++;
3987 rtl8180_tx_isr(dev,HI_PRIORITY,0);
3988 }
3989
3990 if(inta & ISR_RER) {
3991 priv->stats.rxerr++;
c8d86be3 3992 }
c8d86be3
GKH
3993 if(inta & ISR_TBKDER){ //corresponding to BK_PRIORITY
3994 priv->stats.txbkperr++;
3995 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH
3996 rtl8180_tx_isr(dev,BK_PRIORITY,1);
3997 rtl8180_try_wake_queue(dev, BE_PRIORITY);
3998 }
3999
4000 if(inta & ISR_TBEDER){ //corresponding to BE_PRIORITY
4001 priv->stats.txbeperr++;
4002 priv->ieee80211->stats.tx_errors++;
c8d86be3 4003 rtl8180_tx_isr(dev,BE_PRIORITY,1);
c8d86be3
GKH
4004 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4005 }
c8d86be3
GKH
4006 if(inta & ISR_TNPDER){ //corresponding to VO_PRIORITY
4007 priv->stats.txnperr++;
4008 priv->ieee80211->stats.tx_errors++;
c8d86be3 4009 rtl8180_tx_isr(dev,NORM_PRIORITY,1);
c8d86be3 4010 rtl8180_try_wake_queue(dev, NORM_PRIORITY);
c8d86be3
GKH
4011 }
4012
4013 if(inta & ISR_TLPDER){ //corresponding to VI_PRIORITY
4014 priv->stats.txlperr++;
4015 priv->ieee80211->stats.tx_errors++;
c8d86be3 4016 rtl8180_tx_isr(dev,LOW_PRIORITY,1);
c8d86be3
GKH
4017 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4018 }
4019
4020 if(inta & ISR_ROK){
c8d86be3
GKH
4021 priv->stats.rxint++;
4022 tasklet_schedule(&priv->irq_rx_tasklet);
4023 }
4024
4025 if(inta & ISR_RQoSOK ){
c8d86be3
GKH
4026 priv->stats.rxint++;
4027 tasklet_schedule(&priv->irq_rx_tasklet);
4028 }
4029 if(inta & ISR_BcnInt) {
c8d86be3
GKH
4030 rtl8180_prepare_beacon(dev);
4031 }
4032
4033 if(inta & ISR_RDU){
c8d86be3
GKH
4034 DMESGW("No RX descriptor available");
4035 priv->stats.rxrdu++;
c8d86be3 4036 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3 4037 }
fd882783 4038
c8d86be3 4039 if(inta & ISR_RXFOVW){
c8d86be3
GKH
4040 priv->stats.rxoverflow++;
4041 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3
GKH
4042 }
4043
fd882783
BZ
4044 if (inta & ISR_TXFOVW)
4045 priv->stats.txoverflow++;
c8d86be3
GKH
4046
4047 if(inta & ISR_TNPDOK){ //Normal priority tx ok
c8d86be3 4048 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH
4049 priv->stats.txnpokint++;
4050 rtl8180_tx_isr(dev,NORM_PRIORITY,0);
4051 }
4052
4053 if(inta & ISR_TLPDOK){ //Low priority tx ok
c8d86be3 4054 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH
4055 priv->stats.txlpokint++;
4056 rtl8180_tx_isr(dev,LOW_PRIORITY,0);
4057 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4058 }
4059
c8d86be3
GKH
4060 if(inta & ISR_TBKDOK){ //corresponding to BK_PRIORITY
4061 priv->stats.txbkpokint++;
c8d86be3
GKH
4062 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4063 rtl8180_tx_isr(dev,BK_PRIORITY,0);
4064 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4065 }
4066
4067 if(inta & ISR_TBEDOK){ //corresponding to BE_PRIORITY
4068 priv->stats.txbeperr++;
c8d86be3
GKH
4069 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4070 rtl8180_tx_isr(dev,BE_PRIORITY,0);
4071 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4072 }
c8d86be3
GKH
4073 force_pci_posting(dev);
4074 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4075
4076 return IRQ_HANDLED;
4077}
4078
c8d86be3
GKH
4079void rtl8180_irq_rx_tasklet(struct r8180_priv* priv)
4080{
c8d86be3 4081 rtl8180_rx(priv->dev);
c8d86be3
GKH
4082}
4083
c8d86be3
GKH
4084void GPIOChangeRFWorkItemCallBack(struct work_struct *work)
4085{
c8d86be3
GKH
4086 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work);
4087 struct net_device *dev = ieee->dev;
4088 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
4089 u8 btPSR;
4090 u8 btConfig0;
4091 RT_RF_POWER_STATE eRfPowerStateToSet;
4092 bool bActuallySet=false;
4093
4094 char *argv[3];
4095 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh";
4096 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL};
4097 static int readf_count = 0;
c8d86be3 4098
c8d86be3
GKH
4099 if(readf_count % 10 == 0)
4100 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state");
4101
4102 readf_count = (readf_count+1)%0xffff;
1994130e 4103 /* We should turn off LED before polling FF51[4]. */
c8d86be3 4104
1994130e
LF
4105 /* Turn off LED. */
4106 btPSR = read_nic_byte(dev, PSR);
4107 write_nic_byte(dev, PSR, (btPSR & ~BIT3));
c8d86be3 4108
1994130e
LF
4109 /* It need to delay 4us suggested by Jong, 2008-01-16 */
4110 udelay(4);
c8d86be3 4111
1994130e
LF
4112 /* HW radio On/Off according to the value of FF51[4](config0) */
4113 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0);
c8d86be3 4114
1994130e 4115 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;
c8d86be3 4116
6de92dd6
LF
4117 /* Turn LED back on when radio enabled */
4118 if (eRfPowerStateToSet == eRfOn)
4119 write_nic_byte(dev, PSR, btPSR | BIT3);
c8d86be3 4120
1994130e
LF
4121 if ((priv->ieee80211->bHwRadioOff == true) &&
4122 (eRfPowerStateToSet == eRfOn)) {
4123 priv->ieee80211->bHwRadioOff = false;
4124 bActuallySet = true;
4125 } else if ((priv->ieee80211->bHwRadioOff == false) &&
4126 (eRfPowerStateToSet == eRfOff)) {
4127 priv->ieee80211->bHwRadioOff = true;
4128 bActuallySet = true;
4129 }
c8d86be3 4130
1994130e
LF
4131 if (bActuallySet) {
4132 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
4133
4134 /* To update the UI status for Power status changed */
4135 if (priv->ieee80211->bHwRadioOff == true)
4136 argv[1] = "RFOFF";
4137 else
4138 argv[1] = "RFON";
4139 argv[0] = RadioPowerPath;
4140 argv[2] = NULL;
4141
4142 call_usermodehelper(RadioPowerPath, argv, envp, 1);
4143 }
c8d86be3
GKH
4144}
4145
4146static u8 read_acadapter_file(char *filename)
4147{
c8d86be3
GKH
4148 return 0;
4149}
4150
c8d86be3
GKH
4151module_init(rtl8180_pci_module_init);
4152module_exit(rtl8180_pci_module_exit);