Commit | Line | Data |
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ad41a8a5 KH |
1 | #include <linux/kernel.h> |
2 | #include <linux/init.h> | |
3 | #include <linux/module.h> | |
4 | ||
5 | #include <linux/pci.h> | |
6 | #include <linux/device.h> | |
7 | ||
8 | #include <scsi/scsi_host.h> | |
9 | #include <linux/libata.h> | |
10 | ||
11 | #include "pata_rdc.h" | |
12 | ||
482612af | 13 | /* #define DBGPRINTF */ |
ad41a8a5 KH |
14 | |
15 | #ifdef DBGPRINTF | |
16 | ||
17 | #define dbgprintf(format, arg...) printk(KERN_INFO format, ## arg) | |
18 | ||
19 | #else | |
20 | ||
21 | #define dbgprintf(...) | |
22 | ||
23 | #endif | |
24 | ||
482612af GKH |
25 | /* Driver Info. */ |
26 | #define DRIVER_NAME "pata_rdc" /* sata_rdc for SATA */ | |
27 | #define DRIVER_VERSION "2.6.28" /* based on kernel version. */ | |
28 | /* because each kernel main version has | |
29 | * its libata, we follow kernel to | |
30 | * determine the last libata version. | |
31 | */ | |
ad41a8a5 KH |
32 | |
33 | ||
34 | static const struct pci_device_id rdc_pata_id_table[] = { | |
1a24bda2 GKH |
35 | { PCI_DEVICE(0x17F3, 0x1011), RDC_17F31011}, |
36 | { PCI_DEVICE(0x17F3, 0x1012), RDC_17F31012}, | |
482612af | 37 | { } /* terminate list */ |
ad41a8a5 | 38 | }; |
ad41a8a5 | 39 | MODULE_DEVICE_TABLE(pci, rdc_pata_id_table); |
ad41a8a5 | 40 | |
482612af GKH |
41 | /* see ATA Host Adapters Standards. */ |
42 | static struct pci_bits ATA_Decode_Enable_Bits[] = { | |
43 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */ | |
44 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */ | |
ad41a8a5 KH |
45 | }; |
46 | ||
c0a5962f | 47 | static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) |
ad41a8a5 | 48 | { |
c0a5962f GKH |
49 | uint funcresult; |
50 | unchar *pchar; | |
51 | uint i; | |
482612af | 52 | |
c0a5962f | 53 | funcresult = TRUE; |
482612af | 54 | |
c0a5962f | 55 | pchar = pBuffer; |
482612af | 56 | |
c0a5962f GKH |
57 | for (i = 0; i < Length; i++) { |
58 | pci_read_config_byte(pdev, Offset, pchar); | |
59 | Offset++; | |
60 | pchar++; | |
482612af | 61 | } |
482612af | 62 | |
c0a5962f | 63 | funcresult = TRUE; |
482612af | 64 | |
c0a5962f GKH |
65 | goto funcexit; |
66 | funcexit: | |
482612af | 67 | |
c0a5962f | 68 | return funcresult; |
ad41a8a5 KH |
69 | } |
70 | ||
c0a5962f GKH |
71 | static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) |
72 | { | |
73 | uint funcresult; | |
74 | unchar *pchar; | |
75 | uint i; | |
ad41a8a5 | 76 | |
c0a5962f | 77 | funcresult = TRUE; |
ad41a8a5 | 78 | |
c0a5962f | 79 | pchar = pBuffer; |
482612af | 80 | |
c0a5962f GKH |
81 | for (i = 0; i < Length; i++) { |
82 | pci_write_config_byte(pdev, Offset, *pchar); | |
83 | Offset++; | |
84 | pchar++; | |
482612af | 85 | } |
ad41a8a5 | 86 | |
c0a5962f | 87 | funcresult = TRUE; |
ad41a8a5 | 88 | |
c0a5962f GKH |
89 | goto funcexit; |
90 | funcexit: | |
ad41a8a5 | 91 | |
c0a5962f | 92 | return funcresult; |
ad41a8a5 KH |
93 | } |
94 | ||
c0a5962f GKH |
95 | static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, |
96 | uint PIOTimingMode, uint DMAEnable, | |
97 | uint PrefetchPostingEnable) | |
ad41a8a5 | 98 | { |
c0a5962f GKH |
99 | uint funcresult; |
100 | uint result; | |
101 | uint ATATimingRegister; | |
102 | uint Device1TimingRegister; | |
ad41a8a5 | 103 | |
c0a5962f | 104 | funcresult = TRUE; |
ad41a8a5 | 105 | |
c0a5962f GKH |
106 | ATATimingRegister = 0; |
107 | Device1TimingRegister = 0; | |
ad41a8a5 | 108 | |
c0a5962f GKH |
109 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
110 | ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, | |
111 | ATAConfiguration_ID_PrimaryTiming_Size, | |
112 | &ATATimingRegister); | |
113 | if (result == FALSE) { | |
114 | funcresult = FALSE; | |
115 | goto funcexit; | |
116 | } | |
ad41a8a5 | 117 | |
c0a5962f GKH |
118 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
119 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
120 | ATAConfiguration_ID_Device1Timing_Size, | |
121 | &Device1TimingRegister); | |
122 | if (result == FALSE) { | |
123 | funcresult = FALSE; | |
124 | goto funcexit; | |
482612af | 125 | } |
ad41a8a5 | 126 | |
c0a5962f | 127 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; |
ad41a8a5 | 128 | |
c0a5962f GKH |
129 | switch (DeviceID) { |
130 | case 0: | |
131 | /* mask clear */ | |
132 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable | | |
133 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable | | |
134 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable | | |
135 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable | | |
136 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode | | |
137 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode); | |
ad41a8a5 | 138 | |
c0a5962f GKH |
139 | if (PIOTimingMode > PIO0) |
140 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; | |
ad41a8a5 | 141 | |
c0a5962f GKH |
142 | if (PIOTimingMode >= PIO3) |
143 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; | |
ad41a8a5 | 144 | |
c0a5962f GKH |
145 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) |
146 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; | |
ad41a8a5 | 147 | |
c0a5962f GKH |
148 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) |
149 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; | |
ad41a8a5 | 150 | |
c0a5962f GKH |
151 | if (PIOTimingMode <= PIO2) |
152 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; | |
153 | else if (PIOTimingMode == PIO3) | |
154 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; | |
155 | else if (PIOTimingMode == PIO4) | |
156 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; | |
ad41a8a5 | 157 | |
c0a5962f GKH |
158 | if (PIOTimingMode <= PIO1) |
159 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; | |
160 | else if (PIOTimingMode == PIO2) | |
161 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; | |
162 | else if (PIOTimingMode <= PIO4) | |
163 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; | |
164 | break; | |
165 | case 1: | |
166 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable | | |
167 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable | | |
168 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable | | |
169 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable); | |
482612af | 170 | |
c0a5962f GKH |
171 | if (PIOTimingMode > PIO0) |
172 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; | |
482612af | 173 | |
c0a5962f GKH |
174 | if (PIOTimingMode >= PIO3) |
175 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; | |
482612af | 176 | |
c0a5962f GKH |
177 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) |
178 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; | |
482612af | 179 | |
c0a5962f GKH |
180 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) |
181 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; | |
482612af | 182 | |
c0a5962f GKH |
183 | Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode | |
184 | ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode); | |
482612af | 185 | |
c0a5962f GKH |
186 | if (PIOTimingMode <= PIO2) |
187 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0; | |
188 | else if (PIOTimingMode == PIO3) | |
189 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1; | |
190 | else if (PIOTimingMode == PIO4) | |
191 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3; | |
482612af | 192 | |
c0a5962f GKH |
193 | if (PIOTimingMode <= PIO1) |
194 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0; | |
195 | else if (PIOTimingMode == PIO2) | |
196 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1; | |
197 | else if (PIOTimingMode <= PIO4) | |
198 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2; | |
199 | break; | |
200 | default: | |
201 | funcresult = FALSE; | |
202 | goto funcexit; | |
203 | break; | |
204 | } | |
482612af | 205 | |
c0a5962f GKH |
206 | result = PCIDeviceIO_WritePCIConfiguration(pdev, |
207 | ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, | |
208 | ATAConfiguration_ID_PrimaryTiming_Size, | |
209 | &ATATimingRegister); | |
210 | if (result == FALSE) { | |
211 | funcresult = FALSE; | |
212 | goto funcexit; | |
213 | } | |
482612af | 214 | |
c0a5962f GKH |
215 | result = PCIDeviceIO_WritePCIConfiguration(pdev, |
216 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
217 | ATAConfiguration_ID_Device1Timing_Size, | |
218 | &Device1TimingRegister); | |
219 | if (result == FALSE) { | |
220 | funcresult = FALSE; | |
221 | goto funcexit; | |
482612af | 222 | } |
c0a5962f GKH |
223 | |
224 | goto funcexit; | |
225 | funcexit: | |
226 | ||
227 | return funcresult; | |
ad41a8a5 KH |
228 | } |
229 | ||
c0a5962f GKH |
230 | static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, |
231 | uint PIOTimingMode, uint DMAEnable, | |
232 | uint PrefetchPostingEnable) | |
ad41a8a5 | 233 | { |
c0a5962f GKH |
234 | uint funcresult; |
235 | uint result; | |
236 | uint ATATimingRegister; | |
237 | uint Device1TimingRegister; | |
482612af | 238 | |
c0a5962f | 239 | funcresult = TRUE; |
482612af | 240 | |
c0a5962f GKH |
241 | ATATimingRegister = 0; |
242 | Device1TimingRegister = 0; | |
482612af | 243 | |
c0a5962f GKH |
244 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
245 | ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, | |
246 | ATAConfiguration_ID_SecondaryTiming_Size, | |
247 | &ATATimingRegister); | |
248 | if (result == FALSE) { | |
249 | funcresult = FALSE; | |
250 | goto funcexit; | |
482612af GKH |
251 | } |
252 | ||
c0a5962f GKH |
253 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
254 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
255 | ATAConfiguration_ID_Device1Timing_Size, | |
256 | &Device1TimingRegister); | |
257 | if (result == FALSE) { | |
258 | funcresult = FALSE; | |
259 | goto funcexit; | |
482612af GKH |
260 | } |
261 | ||
c0a5962f | 262 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; |
482612af | 263 | |
c0a5962f GKH |
264 | switch (DeviceID) { |
265 | case 0: | |
266 | /* mask clear */ | |
267 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable | | |
268 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable | | |
269 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable | | |
270 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable | | |
271 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode | | |
272 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode); | |
482612af | 273 | |
c0a5962f GKH |
274 | if (PIOTimingMode > PIO0) |
275 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; | |
482612af | 276 | |
c0a5962f GKH |
277 | if (PIOTimingMode >= PIO3) |
278 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; | |
482612af GKH |
279 | |
280 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) | |
281 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; | |
282 | ||
283 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) | |
284 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; | |
285 | ||
286 | if (PIOTimingMode <= PIO2) | |
287 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; | |
288 | else if (PIOTimingMode == PIO3) | |
289 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; | |
290 | else if (PIOTimingMode == PIO4) | |
291 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; | |
292 | ||
293 | if (PIOTimingMode <= PIO1) | |
294 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; | |
295 | else if (PIOTimingMode == PIO2) | |
296 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; | |
297 | else if (PIOTimingMode <= PIO4) | |
298 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; | |
299 | break; | |
300 | case 1: | |
301 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable | | |
302 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable | | |
303 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable | | |
304 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable); | |
305 | ||
306 | if (PIOTimingMode > PIO0) | |
307 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; | |
308 | ||
309 | if (PIOTimingMode >= PIO3) | |
310 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; | |
311 | ||
312 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) | |
313 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; | |
314 | ||
315 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) | |
316 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; | |
317 | ||
318 | Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode | | |
319 | ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode); | |
320 | ||
321 | if (PIOTimingMode <= PIO2) | |
322 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0; | |
323 | else if (PIOTimingMode == PIO3) | |
324 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1; | |
325 | else if (PIOTimingMode == PIO4) | |
326 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3; | |
327 | ||
328 | if (PIOTimingMode <= PIO1) | |
329 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0; | |
330 | else if (PIOTimingMode == PIO2) | |
331 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1; | |
332 | else if (PIOTimingMode <= PIO4) | |
333 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2; | |
334 | break; | |
335 | default: | |
336 | funcresult = FALSE; | |
337 | goto funcexit; | |
338 | break; | |
339 | } | |
340 | ||
341 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
342 | ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, | |
343 | ATAConfiguration_ID_SecondaryTiming_Size, | |
344 | &ATATimingRegister); | |
345 | if (result == FALSE) { | |
346 | funcresult = FALSE; | |
347 | goto funcexit; | |
348 | } | |
349 | ||
350 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
351 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
352 | ATAConfiguration_ID_Device1Timing_Size, | |
353 | &Device1TimingRegister); | |
354 | if (result == FALSE) { | |
355 | funcresult = FALSE; | |
356 | goto funcexit; | |
357 | } | |
358 | ||
359 | goto funcexit; | |
ad41a8a5 | 360 | funcexit: |
482612af | 361 | return funcresult; |
ad41a8a5 KH |
362 | } |
363 | ||
482612af GKH |
364 | static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, |
365 | uint UDMAEnable, uint UDMATimingMode) | |
ad41a8a5 | 366 | { |
482612af GKH |
367 | uint funcresult; |
368 | uint result; | |
369 | uint UDMAControlRegister; | |
370 | uint UDMATimingRegister; | |
371 | ulong IDEIOConfigurationRegister; | |
372 | ||
373 | funcresult = TRUE; | |
374 | UDMAControlRegister = 0; | |
375 | UDMATimingRegister = 0; | |
376 | IDEIOConfigurationRegister = 0; | |
377 | ||
378 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
379 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
380 | ATAConfiguration_ID_UDMAControl_Size, | |
381 | &UDMAControlRegister); | |
382 | if (result == FALSE) { | |
383 | funcresult = FALSE; | |
384 | goto funcexit; | |
385 | } | |
386 | ||
387 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
388 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
389 | ATAConfiguration_ID_UDMATiming_Size, | |
390 | &UDMATimingRegister); | |
391 | if (result == FALSE) { | |
392 | funcresult = FALSE; | |
393 | goto funcexit; | |
394 | } | |
395 | ||
396 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
397 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
398 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
399 | &IDEIOConfigurationRegister); | |
400 | if (result == FALSE) { | |
401 | funcresult = FALSE; | |
402 | goto funcexit; | |
403 | } | |
404 | ||
405 | /*Rom Code will determine the device cable type and ATA 100.*/ | |
406 | /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/ | |
407 | /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/ | |
408 | ||
409 | switch (DeviceID) { | |
410 | case 0: | |
411 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable); | |
412 | if (UDMAEnable == TRUE) | |
413 | UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable; | |
414 | ||
415 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable | | |
416 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable); | |
417 | ||
418 | if (UDMATimingMode >= UDMA5) | |
419 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable; | |
420 | else if (UDMATimingMode >= UDMA3) | |
421 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable; | |
422 | ||
423 | /* if 80 cable report */ | |
424 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime); | |
425 | ||
426 | if (UDMATimingMode == UDMA0) { | |
427 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0; | |
428 | } else if (UDMATimingMode == UDMA1 || | |
429 | UDMATimingMode == UDMA3 || | |
430 | UDMATimingMode == UDMA5) { | |
431 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1; | |
432 | } else if (UDMATimingMode == UDMA2 || | |
433 | UDMATimingMode == UDMA4) { | |
434 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2; | |
435 | } | |
436 | break; | |
437 | case 1: | |
438 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable); | |
439 | if (UDMAEnable == TRUE) | |
440 | UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable; | |
441 | ||
442 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable | | |
443 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable); | |
444 | ||
445 | if (UDMATimingMode >= UDMA5) | |
446 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable; | |
447 | else if (UDMATimingMode >= UDMA3) | |
448 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable; | |
449 | ||
450 | /* if 80 cable report */ | |
451 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime); | |
452 | ||
453 | if (UDMATimingMode == UDMA0) { | |
454 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0; | |
455 | } else if (UDMATimingMode == UDMA1 || | |
456 | UDMATimingMode == UDMA3 || | |
457 | UDMATimingMode == UDMA5) { | |
458 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1; | |
459 | } else if (UDMATimingMode == UDMA2 || | |
460 | UDMATimingMode == UDMA4) { | |
461 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2; | |
462 | } | |
463 | break; | |
464 | default: | |
465 | funcresult = FALSE; | |
466 | goto funcexit; | |
467 | break; | |
468 | } | |
469 | ||
470 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
471 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
472 | ATAConfiguration_ID_UDMAControl_Size, | |
473 | &UDMAControlRegister); | |
474 | if (result == FALSE) { | |
475 | funcresult = FALSE; | |
476 | goto funcexit; | |
477 | } | |
478 | ||
479 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
480 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
481 | ATAConfiguration_ID_UDMATiming_Size, | |
482 | &UDMATimingRegister); | |
483 | if (result == FALSE) { | |
484 | funcresult = FALSE; | |
485 | goto funcexit; | |
486 | } | |
487 | ||
488 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
489 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
490 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
491 | &IDEIOConfigurationRegister); | |
492 | if (result == FALSE) { | |
493 | funcresult = FALSE; | |
494 | goto funcexit; | |
495 | } | |
496 | ||
497 | goto funcexit; | |
ad41a8a5 | 498 | funcexit: |
482612af | 499 | return funcresult; |
ad41a8a5 KH |
500 | } |
501 | ||
482612af GKH |
502 | static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, |
503 | uint UDMAEnable, uint UDMATimingMode) | |
ad41a8a5 | 504 | { |
482612af GKH |
505 | uint funcresult; |
506 | uint result; | |
507 | uint UDMAControlRegister; | |
508 | uint UDMATimingRegister; | |
509 | ulong IDEIOConfigurationRegister; | |
510 | ||
511 | funcresult = TRUE; | |
512 | ||
513 | UDMAControlRegister = 0; | |
514 | UDMATimingRegister = 0; | |
515 | IDEIOConfigurationRegister = 0; | |
516 | ||
517 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
518 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
519 | ATAConfiguration_ID_UDMAControl_Size, | |
520 | &UDMAControlRegister); | |
521 | if (result == FALSE) { | |
522 | funcresult = FALSE; | |
523 | goto funcexit; | |
524 | } | |
525 | ||
526 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
527 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
528 | ATAConfiguration_ID_UDMATiming_Size, | |
529 | &UDMATimingRegister); | |
530 | if (result == FALSE) { | |
531 | funcresult = FALSE; | |
532 | goto funcexit; | |
533 | } | |
534 | ||
535 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
536 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
537 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
538 | &IDEIOConfigurationRegister); | |
539 | if (result == FALSE) { | |
540 | funcresult = FALSE; | |
541 | goto funcexit; | |
542 | } | |
543 | ||
544 | /* Rom Code will determine the device cable type and ATA 100. */ | |
545 | /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */ | |
546 | /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */ | |
547 | ||
548 | switch (DeviceID) { | |
549 | case 0: | |
550 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable); | |
551 | if (UDMAEnable == TRUE) | |
552 | UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable; | |
553 | ||
554 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable | | |
555 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable); | |
556 | ||
557 | if (UDMATimingMode >= UDMA5) | |
558 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable; | |
559 | else if (UDMATimingMode >= UDMA3) | |
560 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable; | |
561 | ||
562 | /* if 80 cable report */ | |
563 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime); | |
564 | ||
565 | if (UDMATimingMode == UDMA0) { | |
566 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0; | |
567 | } else if (UDMATimingMode == UDMA1 || | |
568 | UDMATimingMode == UDMA3 || | |
569 | UDMATimingMode == UDMA5) { | |
570 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1; | |
571 | } else if (UDMATimingMode == UDMA2 || | |
572 | UDMATimingMode == UDMA4) { | |
573 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2; | |
574 | } | |
575 | break; | |
576 | case 1: | |
577 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable); | |
578 | if (UDMAEnable == TRUE) | |
579 | UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable; | |
580 | ||
581 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable | | |
582 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable); | |
583 | ||
584 | if (UDMATimingMode >= UDMA5) | |
585 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable; | |
586 | else if (UDMATimingMode >= UDMA3) | |
587 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable; | |
588 | ||
589 | /* if 80 cable report */ | |
590 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime); | |
591 | ||
592 | if (UDMATimingMode == UDMA0) { | |
593 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0; | |
594 | } else if (UDMATimingMode == UDMA1 || | |
595 | UDMATimingMode == UDMA3 || | |
596 | UDMATimingMode == UDMA5) { | |
597 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1; | |
598 | } else if (UDMATimingMode == UDMA2 || | |
599 | UDMATimingMode == UDMA4) { | |
600 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2; | |
601 | } | |
602 | break; | |
603 | default: | |
604 | funcresult = FALSE; | |
605 | goto funcexit; | |
606 | break; | |
607 | } | |
608 | ||
609 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
610 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
611 | ATAConfiguration_ID_UDMAControl_Size, | |
612 | &UDMAControlRegister); | |
613 | if (result == FALSE) { | |
614 | funcresult = FALSE; | |
615 | goto funcexit; | |
616 | } | |
617 | ||
618 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
619 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
620 | ATAConfiguration_ID_UDMATiming_Size, | |
621 | &UDMATimingRegister); | |
622 | if (result == FALSE) { | |
623 | funcresult = FALSE; | |
624 | goto funcexit; | |
625 | } | |
626 | ||
627 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
628 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
629 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
630 | &IDEIOConfigurationRegister); | |
631 | if (result == FALSE) { | |
632 | funcresult = FALSE; | |
633 | goto funcexit; | |
634 | } | |
635 | ||
636 | goto funcexit; | |
ad41a8a5 | 637 | funcexit: |
482612af | 638 | return funcresult; |
ad41a8a5 | 639 | } |
c0a5962f GKH |
640 | |
641 | /** | |
642 | * Set port up for dma. | |
643 | * @ap: Port to initialize | |
644 | * | |
645 | * Called just after data structures for each port are | |
646 | * initialized. Allocates space for PRD table if the device | |
647 | * is DMA capable SFF. | |
648 | ||
649 | Some drivers also use this entry point as a chance to allocate driverprivate | |
650 | memory for ap->private_data. | |
651 | ||
652 | * | |
653 | * May be used as the port_start() entry in ata_port_operations. | |
654 | * | |
655 | * LOCKING: | |
656 | * Inherited from caller. | |
657 | */ | |
658 | static int rdc_pata_port_start(struct ata_port *ap) | |
659 | { | |
660 | uint Channel; | |
661 | ||
662 | Channel = ap->port_no; | |
663 | dbgprintf("rdc_pata_port_start Channel: %u \n", Channel); | |
664 | if (ap->ioaddr.bmdma_addr) { | |
665 | return ata_port_start(ap); | |
666 | } else { | |
667 | dbgprintf("rdc_pata_port_start return 0 !!!\n"); | |
668 | return 0; | |
669 | } | |
670 | } | |
671 | ||
672 | static void rdc_pata_port_stop(struct ata_port *ap) | |
673 | { | |
674 | uint Channel; | |
675 | ||
676 | Channel = ap->port_no; | |
677 | ||
678 | dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel); | |
679 | } | |
680 | ||
681 | /** | |
682 | * prereset for PATA host controller | |
683 | * @link: Target link | |
684 | * @deadline: deadline jiffies for the operation | |
685 | * | |
686 | * LOCKING: | |
687 | * None (inherited from caller). | |
688 | */ | |
689 | static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline) | |
690 | { | |
691 | struct pci_dev *pdev; | |
692 | struct ata_port *ap; | |
693 | uint Channel; | |
694 | ||
695 | dbgprintf("rdc_pata_prereset\n"); | |
696 | ||
697 | ap = link->ap; | |
698 | pdev = to_pci_dev(ap->host->dev); | |
699 | ||
700 | Channel = ap->port_no; | |
701 | ||
702 | /* test ATA Decode Enable Bits, should be enable. */ | |
703 | if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) { | |
704 | dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel); | |
705 | return -ENOENT; | |
706 | } else { | |
707 | dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel); | |
708 | return ata_std_prereset(link, deadline); | |
709 | } | |
710 | } | |
711 | ||
712 | /** | |
713 | * Probe host controller cable detect info | |
714 | * @ap: Port for which cable detect info is desired | |
715 | * | |
716 | * Read cable indicator from ATA PCI device's PCI config | |
717 | * register. This register is normally set by firmware (BIOS). | |
718 | * | |
719 | * LOCKING: | |
720 | * None (inherited from caller). | |
721 | */ | |
722 | static int rdc_pata_cable_detect(struct ata_port *ap) | |
723 | { | |
724 | struct pci_dev *pdev; | |
725 | uint Channel; | |
726 | uint Mask; | |
727 | u32 u32Value; | |
728 | ||
729 | dbgprintf("rdc_pata_cable_detect\n"); | |
730 | ||
731 | pdev = to_pci_dev(ap->host->dev); | |
732 | ||
733 | Channel = ap->port_no; | |
734 | ||
735 | if (Channel == 0) | |
736 | Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report; | |
737 | else | |
738 | Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report; | |
739 | ||
740 | /* check BIOS cable detect results */ | |
741 | pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value); | |
742 | ||
743 | if ((u32Value & Mask) == 0) { | |
744 | dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel); | |
745 | return ATA_CBL_PATA40; | |
746 | } else { | |
747 | dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel); | |
748 | return ATA_CBL_PATA80; | |
749 | } | |
750 | } | |
751 | ||
752 | /** | |
753 | * Initialize host controller PATA PIO timings | |
754 | * @ap: Port whose timings we are configuring | |
755 | * @adev: um | |
756 | * | |
757 | * Set PIO mode for device, in host controller PCI config space. | |
758 | * | |
759 | * LOCKING: | |
760 | * None (inherited from caller). | |
761 | */ | |
762 | static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
763 | { | |
764 | struct pci_dev *pdev; | |
765 | uint Channel; | |
766 | uint DeviceID; | |
767 | uint PIOTimingMode; | |
768 | uint PrefetchPostingEnable; | |
769 | ||
770 | dbgprintf("rdc_pata_set_piomode\n"); | |
771 | ||
772 | pdev = to_pci_dev(ap->host->dev); | |
773 | ||
774 | Channel = ap->port_no; | |
775 | DeviceID = adev->devno; | |
776 | /* | |
777 | * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, | |
778 | * XFER_PIO_2, XFER_PIO_3... | |
779 | */ | |
780 | PIOTimingMode = adev->pio_mode - XFER_PIO_0; | |
781 | ||
782 | if (adev->class == ATA_DEV_ATA) { | |
783 | PrefetchPostingEnable = TRUE; | |
784 | } else { | |
785 | /* ATAPI, CD DVD Rom */ | |
786 | PrefetchPostingEnable = FALSE; | |
787 | } | |
788 | ||
789 | /* PIO configuration clears DTE unconditionally. It will be | |
790 | * programmed in set_dmamode which is guaranteed to be called | |
791 | * after set_piomode if any DMA mode is available. | |
792 | */ | |
793 | ||
794 | /* Ensure the UDMA bit is off - it will be turned back on if UDMA is | |
795 | * selected */ | |
796 | ||
797 | if (Channel == 0) { | |
798 | ATAHostAdapter_SetPrimaryPIO( | |
799 | pdev, | |
800 | DeviceID, | |
801 | PIOTimingMode, | |
802 | TRUE,/* DMAEnable, */ | |
803 | PrefetchPostingEnable | |
804 | ); | |
805 | ||
806 | ATAHostAdapter_SetPrimaryUDMA( | |
807 | pdev, | |
808 | DeviceID, | |
809 | FALSE,/* UDMAEnable, */ | |
810 | UDMA0 | |
811 | ); | |
812 | } else { | |
813 | ATAHostAdapter_SetSecondaryPIO( | |
814 | pdev, | |
815 | DeviceID, | |
816 | PIOTimingMode, | |
817 | TRUE,/* DMAEnable, */ | |
818 | PrefetchPostingEnable | |
819 | ); | |
820 | ||
821 | ATAHostAdapter_SetSecondaryUDMA( | |
822 | pdev, | |
823 | DeviceID, | |
824 | FALSE,/* UDMAEnable, */ | |
825 | UDMA0 | |
826 | ); | |
827 | } | |
828 | dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode); | |
829 | } | |
830 | ||
831 | /** | |
832 | * Initialize host controller PATA DMA timings | |
833 | * @ap: Port whose timings we are configuring | |
834 | * @adev: um | |
835 | * | |
836 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
837 | * | |
838 | * LOCKING: | |
839 | * None (inherited from caller). | |
840 | */ | |
841 | static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
842 | { | |
843 | struct pci_dev *pdev; | |
844 | uint Channel; | |
845 | uint DeviceID; | |
846 | uint PIOTimingMode; | |
847 | uint PrefetchPostingEnable; | |
848 | uint DMATimingMode; | |
849 | uint UDMAEnable; | |
850 | ||
851 | dbgprintf("rdc_pata_set_dmamode\n"); | |
852 | ||
853 | pdev = to_pci_dev(ap->host->dev); | |
854 | ||
855 | Channel = ap->port_no; | |
856 | DeviceID = adev->devno; | |
857 | PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */ | |
858 | DMATimingMode = adev->dma_mode; /* UDMA or MDMA */ | |
859 | ||
860 | if (adev->class == ATA_DEV_ATA) { | |
861 | PrefetchPostingEnable = TRUE; | |
862 | } else { | |
863 | /* ATAPI, CD DVD Rom */ | |
864 | PrefetchPostingEnable = FALSE; | |
865 | } | |
866 | ||
867 | if (ap->udma_mask == 0) { | |
868 | /* ata_port dont support udma. depend on hardware spec. */ | |
869 | UDMAEnable = FALSE; | |
870 | } else { | |
871 | UDMAEnable = TRUE; | |
872 | } | |
873 | ||
874 | /*if (ap->mdma_mask == 0) { | |
875 | }*/ | |
876 | ||
877 | if (Channel == 0) { | |
878 | if (DMATimingMode >= XFER_UDMA_0) { | |
879 | /* UDMA */ | |
880 | ATAHostAdapter_SetPrimaryPIO(pdev, | |
881 | DeviceID, | |
882 | PIOTimingMode, | |
883 | TRUE,/*DMAEnable,*/ | |
884 | PrefetchPostingEnable); | |
885 | ||
886 | ATAHostAdapter_SetPrimaryUDMA(pdev, | |
887 | DeviceID, | |
888 | UDMAEnable, | |
889 | DMATimingMode - XFER_UDMA_0); | |
890 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0)); | |
891 | } else { | |
892 | /* MDMA */ | |
893 | ATAHostAdapter_SetPrimaryPIO(pdev, | |
894 | DeviceID, | |
895 | (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */ | |
896 | TRUE,/*DMAEnable,*/ | |
897 | PrefetchPostingEnable); | |
898 | ||
899 | ATAHostAdapter_SetPrimaryUDMA(pdev, | |
900 | DeviceID, | |
901 | FALSE,/*UDMAEnable,*/ | |
902 | UDMA0); | |
903 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0)); | |
904 | } | |
905 | } else { | |
906 | if (DMATimingMode >= XFER_UDMA_0) { | |
907 | /* UDMA */ | |
908 | ATAHostAdapter_SetSecondaryPIO(pdev, | |
909 | DeviceID, | |
910 | PIOTimingMode, | |
911 | TRUE,/*DMAEnable,*/ | |
912 | PrefetchPostingEnable); | |
913 | ||
914 | ATAHostAdapter_SetSecondaryUDMA(pdev, | |
915 | DeviceID, | |
916 | UDMAEnable, | |
917 | DMATimingMode - XFER_UDMA_0); | |
918 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0)); | |
919 | } else { | |
920 | /* MDMA */ | |
921 | ATAHostAdapter_SetSecondaryPIO(pdev, | |
922 | DeviceID, | |
923 | (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */ | |
924 | TRUE,/*DMAEnable,*/ | |
925 | PrefetchPostingEnable); | |
926 | ||
927 | ATAHostAdapter_SetSecondaryUDMA(pdev, | |
928 | DeviceID, | |
929 | FALSE,/*UDMAEnable,*/ | |
930 | UDMA0); | |
931 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0)); | |
932 | } | |
933 | } | |
934 | } | |
935 | ||
936 | /* pata host template */ | |
937 | static struct scsi_host_template rdc_pata_sht = { | |
938 | ATA_BMDMA_SHT(DRIVER_NAME), | |
939 | }; | |
940 | ||
6b23e310 | 941 | static struct ata_port_operations rdc_pata_ops = { |
c0a5962f GKH |
942 | .inherits = &ata_bmdma_port_ops, |
943 | ||
944 | .port_start = rdc_pata_port_start, | |
945 | .port_stop = rdc_pata_port_stop, | |
946 | .prereset = rdc_pata_prereset, | |
947 | .cable_detect = rdc_pata_cable_detect, | |
948 | .set_piomode = rdc_pata_set_piomode, | |
949 | .set_dmamode = rdc_pata_set_dmamode, | |
950 | }; | |
951 | ||
952 | static struct ata_port_info rdc_pata_port_info[] = { | |
953 | [RDC_17F31011] = { | |
954 | .flags = ATA_FLAG_SLAVE_POSS, | |
955 | .pio_mask = 0x1f, /* pio0-4 */ | |
956 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
957 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
958 | .port_ops = &rdc_pata_ops, | |
959 | }, | |
960 | ||
961 | [RDC_17F31012] = { | |
962 | .flags = ATA_FLAG_SLAVE_POSS, | |
963 | .pio_mask = 0x1f, /* pio0-4 */ | |
964 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
965 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
966 | .port_ops = &rdc_pata_ops, | |
967 | }, | |
968 | }; | |
969 | ||
970 | static int __devinit rdc_init_one(struct pci_dev *pdev, | |
971 | const struct pci_device_id *ent) | |
972 | { | |
973 | /*struct device *dev = &pdev->dev; */ | |
974 | struct ata_port_info port_info[2]; | |
975 | const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] }; | |
976 | ||
977 | int rc; | |
978 | ||
979 | dbgprintf("rdc_init_one\n"); | |
980 | ||
c0a5962f GKH |
981 | port_info[0] = rdc_pata_port_info[ent->driver_data]; |
982 | port_info[1] = rdc_pata_port_info[ent->driver_data]; | |
983 | ||
984 | /* enable device and prepare host */ | |
985 | rc = pci_enable_device(pdev); | |
986 | if (rc) { | |
987 | dbgprintf("rdc_init_one pci_enable_device failed \n"); | |
988 | return rc; | |
989 | } | |
990 | /* initialize controller */ | |
991 | ||
992 | pci_intx(pdev, 1); /* enable interrupt */ | |
993 | ||
994 | return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL); | |
995 | } | |
996 | ||
997 | /* a pci driver */ | |
998 | static struct pci_driver rdc_pata_driver = { | |
999 | .name = DRIVER_NAME, | |
1000 | .id_table = rdc_pata_id_table, | |
1001 | .probe = rdc_init_one, | |
1002 | .remove = ata_pci_remove_one, | |
1003 | #ifdef CONFIG_PM | |
1004 | .suspend = ata_pci_device_suspend, | |
1005 | .resume = ata_pci_device_resume, | |
1006 | #endif | |
1007 | }; | |
1008 | ||
1009 | static int __init pata_rdc_init(void) | |
1010 | { | |
1011 | int rc; | |
1012 | ||
1013 | dbgprintf("pata_rdc_init\n"); | |
1014 | rc = pci_register_driver(&rdc_pata_driver); | |
1015 | if (rc) { | |
1016 | dbgprintf("pata_rdc_init faile\n"); | |
1017 | return rc; | |
1018 | } | |
1019 | ||
c0a5962f GKH |
1020 | return 0; |
1021 | } | |
1022 | ||
1023 | static void __exit pata_rdc_exit(void) | |
1024 | { | |
1025 | dbgprintf("pata_rdc_exit\n"); | |
1026 | pci_unregister_driver(&rdc_pata_driver); | |
1027 | } | |
1028 | ||
1029 | module_init(pata_rdc_init); | |
1030 | module_exit(pata_rdc_exit); | |
1031 | ||
1032 | MODULE_LICENSE("GPL"); | |
1033 | MODULE_DESCRIPTION("RDC PCI IDE Driver"); | |
1034 | MODULE_VERSION(DRIVER_VERSION); |