Commit | Line | Data |
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ad41a8a5 KH |
1 | #include <linux/kernel.h> |
2 | #include <linux/init.h> | |
3 | #include <linux/module.h> | |
4 | ||
5 | #include <linux/pci.h> | |
6 | #include <linux/device.h> | |
7 | ||
8 | #include <scsi/scsi_host.h> | |
9 | #include <linux/libata.h> | |
10 | ||
11 | #include "pata_rdc.h" | |
12 | ||
482612af | 13 | /* #define DBGPRINTF */ |
ad41a8a5 KH |
14 | |
15 | #ifdef DBGPRINTF | |
16 | ||
17 | #define dbgprintf(format, arg...) printk(KERN_INFO format, ## arg) | |
18 | ||
19 | #else | |
20 | ||
21 | #define dbgprintf(...) | |
22 | ||
23 | #endif | |
24 | ||
482612af GKH |
25 | /* Driver Info. */ |
26 | #define DRIVER_NAME "pata_rdc" /* sata_rdc for SATA */ | |
27 | #define DRIVER_VERSION "2.6.28" /* based on kernel version. */ | |
28 | /* because each kernel main version has | |
29 | * its libata, we follow kernel to | |
30 | * determine the last libata version. | |
31 | */ | |
ad41a8a5 KH |
32 | |
33 | ||
34 | static const struct pci_device_id rdc_pata_id_table[] = { | |
482612af GKH |
35 | { 0x17F3, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31011}, |
36 | { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012}, | |
37 | { } /* terminate list */ | |
ad41a8a5 | 38 | }; |
ad41a8a5 | 39 | MODULE_DEVICE_TABLE(pci, rdc_pata_id_table); |
ad41a8a5 | 40 | |
482612af | 41 | static unsigned int in_module_init = 1; /* hotplugging check??? */ |
ad41a8a5 | 42 | |
482612af | 43 | /* ata device data */ |
ad41a8a5 | 44 | |
482612af GKH |
45 | /* see ATA Host Adapters Standards. */ |
46 | static struct pci_bits ATA_Decode_Enable_Bits[] = { | |
47 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */ | |
48 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */ | |
ad41a8a5 KH |
49 | }; |
50 | ||
c0a5962f | 51 | static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) |
ad41a8a5 | 52 | { |
c0a5962f GKH |
53 | uint funcresult; |
54 | unchar *pchar; | |
55 | uint i; | |
482612af | 56 | |
c0a5962f | 57 | funcresult = TRUE; |
482612af | 58 | |
c0a5962f | 59 | pchar = pBuffer; |
482612af | 60 | |
c0a5962f GKH |
61 | for (i = 0; i < Length; i++) { |
62 | pci_read_config_byte(pdev, Offset, pchar); | |
63 | Offset++; | |
64 | pchar++; | |
482612af | 65 | } |
482612af | 66 | |
c0a5962f | 67 | funcresult = TRUE; |
482612af | 68 | |
c0a5962f GKH |
69 | goto funcexit; |
70 | funcexit: | |
482612af | 71 | |
c0a5962f | 72 | return funcresult; |
ad41a8a5 KH |
73 | } |
74 | ||
c0a5962f GKH |
75 | static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) |
76 | { | |
77 | uint funcresult; | |
78 | unchar *pchar; | |
79 | uint i; | |
ad41a8a5 | 80 | |
c0a5962f | 81 | funcresult = TRUE; |
ad41a8a5 | 82 | |
c0a5962f | 83 | pchar = pBuffer; |
482612af | 84 | |
c0a5962f GKH |
85 | for (i = 0; i < Length; i++) { |
86 | pci_write_config_byte(pdev, Offset, *pchar); | |
87 | Offset++; | |
88 | pchar++; | |
482612af | 89 | } |
ad41a8a5 | 90 | |
c0a5962f | 91 | funcresult = TRUE; |
ad41a8a5 | 92 | |
c0a5962f GKH |
93 | goto funcexit; |
94 | funcexit: | |
ad41a8a5 | 95 | |
c0a5962f | 96 | return funcresult; |
ad41a8a5 KH |
97 | } |
98 | ||
c0a5962f GKH |
99 | static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, |
100 | uint PIOTimingMode, uint DMAEnable, | |
101 | uint PrefetchPostingEnable) | |
ad41a8a5 | 102 | { |
c0a5962f GKH |
103 | uint funcresult; |
104 | uint result; | |
105 | uint ATATimingRegister; | |
106 | uint Device1TimingRegister; | |
ad41a8a5 | 107 | |
c0a5962f | 108 | funcresult = TRUE; |
ad41a8a5 | 109 | |
c0a5962f GKH |
110 | ATATimingRegister = 0; |
111 | Device1TimingRegister = 0; | |
ad41a8a5 | 112 | |
c0a5962f GKH |
113 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
114 | ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, | |
115 | ATAConfiguration_ID_PrimaryTiming_Size, | |
116 | &ATATimingRegister); | |
117 | if (result == FALSE) { | |
118 | funcresult = FALSE; | |
119 | goto funcexit; | |
120 | } | |
ad41a8a5 | 121 | |
c0a5962f GKH |
122 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
123 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
124 | ATAConfiguration_ID_Device1Timing_Size, | |
125 | &Device1TimingRegister); | |
126 | if (result == FALSE) { | |
127 | funcresult = FALSE; | |
128 | goto funcexit; | |
482612af | 129 | } |
ad41a8a5 | 130 | |
c0a5962f | 131 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; |
ad41a8a5 | 132 | |
c0a5962f GKH |
133 | switch (DeviceID) { |
134 | case 0: | |
135 | /* mask clear */ | |
136 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable | | |
137 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable | | |
138 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable | | |
139 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable | | |
140 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode | | |
141 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode); | |
ad41a8a5 | 142 | |
c0a5962f GKH |
143 | if (PIOTimingMode > PIO0) |
144 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; | |
ad41a8a5 | 145 | |
c0a5962f GKH |
146 | if (PIOTimingMode >= PIO3) |
147 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; | |
ad41a8a5 | 148 | |
c0a5962f GKH |
149 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) |
150 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; | |
ad41a8a5 | 151 | |
c0a5962f GKH |
152 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) |
153 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; | |
ad41a8a5 | 154 | |
c0a5962f GKH |
155 | if (PIOTimingMode <= PIO2) |
156 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; | |
157 | else if (PIOTimingMode == PIO3) | |
158 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; | |
159 | else if (PIOTimingMode == PIO4) | |
160 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; | |
ad41a8a5 | 161 | |
c0a5962f GKH |
162 | if (PIOTimingMode <= PIO1) |
163 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; | |
164 | else if (PIOTimingMode == PIO2) | |
165 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; | |
166 | else if (PIOTimingMode <= PIO4) | |
167 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; | |
168 | break; | |
169 | case 1: | |
170 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable | | |
171 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable | | |
172 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable | | |
173 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable); | |
482612af | 174 | |
c0a5962f GKH |
175 | if (PIOTimingMode > PIO0) |
176 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; | |
482612af | 177 | |
c0a5962f GKH |
178 | if (PIOTimingMode >= PIO3) |
179 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; | |
482612af | 180 | |
c0a5962f GKH |
181 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) |
182 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; | |
482612af | 183 | |
c0a5962f GKH |
184 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) |
185 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; | |
482612af | 186 | |
c0a5962f GKH |
187 | Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode | |
188 | ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode); | |
482612af | 189 | |
c0a5962f GKH |
190 | if (PIOTimingMode <= PIO2) |
191 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0; | |
192 | else if (PIOTimingMode == PIO3) | |
193 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1; | |
194 | else if (PIOTimingMode == PIO4) | |
195 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3; | |
482612af | 196 | |
c0a5962f GKH |
197 | if (PIOTimingMode <= PIO1) |
198 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0; | |
199 | else if (PIOTimingMode == PIO2) | |
200 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1; | |
201 | else if (PIOTimingMode <= PIO4) | |
202 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2; | |
203 | break; | |
204 | default: | |
205 | funcresult = FALSE; | |
206 | goto funcexit; | |
207 | break; | |
208 | } | |
482612af | 209 | |
c0a5962f GKH |
210 | result = PCIDeviceIO_WritePCIConfiguration(pdev, |
211 | ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, | |
212 | ATAConfiguration_ID_PrimaryTiming_Size, | |
213 | &ATATimingRegister); | |
214 | if (result == FALSE) { | |
215 | funcresult = FALSE; | |
216 | goto funcexit; | |
217 | } | |
482612af | 218 | |
c0a5962f GKH |
219 | result = PCIDeviceIO_WritePCIConfiguration(pdev, |
220 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
221 | ATAConfiguration_ID_Device1Timing_Size, | |
222 | &Device1TimingRegister); | |
223 | if (result == FALSE) { | |
224 | funcresult = FALSE; | |
225 | goto funcexit; | |
482612af | 226 | } |
c0a5962f GKH |
227 | |
228 | goto funcexit; | |
229 | funcexit: | |
230 | ||
231 | return funcresult; | |
ad41a8a5 KH |
232 | } |
233 | ||
c0a5962f GKH |
234 | static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, |
235 | uint PIOTimingMode, uint DMAEnable, | |
236 | uint PrefetchPostingEnable) | |
ad41a8a5 | 237 | { |
c0a5962f GKH |
238 | uint funcresult; |
239 | uint result; | |
240 | uint ATATimingRegister; | |
241 | uint Device1TimingRegister; | |
482612af | 242 | |
c0a5962f | 243 | funcresult = TRUE; |
482612af | 244 | |
c0a5962f GKH |
245 | ATATimingRegister = 0; |
246 | Device1TimingRegister = 0; | |
482612af | 247 | |
c0a5962f GKH |
248 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
249 | ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, | |
250 | ATAConfiguration_ID_SecondaryTiming_Size, | |
251 | &ATATimingRegister); | |
252 | if (result == FALSE) { | |
253 | funcresult = FALSE; | |
254 | goto funcexit; | |
482612af GKH |
255 | } |
256 | ||
c0a5962f GKH |
257 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
258 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
259 | ATAConfiguration_ID_Device1Timing_Size, | |
260 | &Device1TimingRegister); | |
261 | if (result == FALSE) { | |
262 | funcresult = FALSE; | |
263 | goto funcexit; | |
482612af GKH |
264 | } |
265 | ||
c0a5962f | 266 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; |
482612af | 267 | |
c0a5962f GKH |
268 | switch (DeviceID) { |
269 | case 0: | |
270 | /* mask clear */ | |
271 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable | | |
272 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable | | |
273 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable | | |
274 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable | | |
275 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode | | |
276 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode); | |
482612af | 277 | |
c0a5962f GKH |
278 | if (PIOTimingMode > PIO0) |
279 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; | |
482612af | 280 | |
c0a5962f GKH |
281 | if (PIOTimingMode >= PIO3) |
282 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; | |
482612af GKH |
283 | |
284 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) | |
285 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; | |
286 | ||
287 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) | |
288 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; | |
289 | ||
290 | if (PIOTimingMode <= PIO2) | |
291 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; | |
292 | else if (PIOTimingMode == PIO3) | |
293 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; | |
294 | else if (PIOTimingMode == PIO4) | |
295 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; | |
296 | ||
297 | if (PIOTimingMode <= PIO1) | |
298 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; | |
299 | else if (PIOTimingMode == PIO2) | |
300 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; | |
301 | else if (PIOTimingMode <= PIO4) | |
302 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; | |
303 | break; | |
304 | case 1: | |
305 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable | | |
306 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable | | |
307 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable | | |
308 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable); | |
309 | ||
310 | if (PIOTimingMode > PIO0) | |
311 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; | |
312 | ||
313 | if (PIOTimingMode >= PIO3) | |
314 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; | |
315 | ||
316 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) | |
317 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; | |
318 | ||
319 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) | |
320 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; | |
321 | ||
322 | Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode | | |
323 | ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode); | |
324 | ||
325 | if (PIOTimingMode <= PIO2) | |
326 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0; | |
327 | else if (PIOTimingMode == PIO3) | |
328 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1; | |
329 | else if (PIOTimingMode == PIO4) | |
330 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3; | |
331 | ||
332 | if (PIOTimingMode <= PIO1) | |
333 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0; | |
334 | else if (PIOTimingMode == PIO2) | |
335 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1; | |
336 | else if (PIOTimingMode <= PIO4) | |
337 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2; | |
338 | break; | |
339 | default: | |
340 | funcresult = FALSE; | |
341 | goto funcexit; | |
342 | break; | |
343 | } | |
344 | ||
345 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
346 | ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, | |
347 | ATAConfiguration_ID_SecondaryTiming_Size, | |
348 | &ATATimingRegister); | |
349 | if (result == FALSE) { | |
350 | funcresult = FALSE; | |
351 | goto funcexit; | |
352 | } | |
353 | ||
354 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
355 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
356 | ATAConfiguration_ID_Device1Timing_Size, | |
357 | &Device1TimingRegister); | |
358 | if (result == FALSE) { | |
359 | funcresult = FALSE; | |
360 | goto funcexit; | |
361 | } | |
362 | ||
363 | goto funcexit; | |
ad41a8a5 | 364 | funcexit: |
482612af | 365 | return funcresult; |
ad41a8a5 KH |
366 | } |
367 | ||
482612af GKH |
368 | static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, |
369 | uint UDMAEnable, uint UDMATimingMode) | |
ad41a8a5 | 370 | { |
482612af GKH |
371 | uint funcresult; |
372 | uint result; | |
373 | uint UDMAControlRegister; | |
374 | uint UDMATimingRegister; | |
375 | ulong IDEIOConfigurationRegister; | |
376 | ||
377 | funcresult = TRUE; | |
378 | UDMAControlRegister = 0; | |
379 | UDMATimingRegister = 0; | |
380 | IDEIOConfigurationRegister = 0; | |
381 | ||
382 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
383 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
384 | ATAConfiguration_ID_UDMAControl_Size, | |
385 | &UDMAControlRegister); | |
386 | if (result == FALSE) { | |
387 | funcresult = FALSE; | |
388 | goto funcexit; | |
389 | } | |
390 | ||
391 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
392 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
393 | ATAConfiguration_ID_UDMATiming_Size, | |
394 | &UDMATimingRegister); | |
395 | if (result == FALSE) { | |
396 | funcresult = FALSE; | |
397 | goto funcexit; | |
398 | } | |
399 | ||
400 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
401 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
402 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
403 | &IDEIOConfigurationRegister); | |
404 | if (result == FALSE) { | |
405 | funcresult = FALSE; | |
406 | goto funcexit; | |
407 | } | |
408 | ||
409 | /*Rom Code will determine the device cable type and ATA 100.*/ | |
410 | /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/ | |
411 | /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/ | |
412 | ||
413 | switch (DeviceID) { | |
414 | case 0: | |
415 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable); | |
416 | if (UDMAEnable == TRUE) | |
417 | UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable; | |
418 | ||
419 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable | | |
420 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable); | |
421 | ||
422 | if (UDMATimingMode >= UDMA5) | |
423 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable; | |
424 | else if (UDMATimingMode >= UDMA3) | |
425 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable; | |
426 | ||
427 | /* if 80 cable report */ | |
428 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime); | |
429 | ||
430 | if (UDMATimingMode == UDMA0) { | |
431 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0; | |
432 | } else if (UDMATimingMode == UDMA1 || | |
433 | UDMATimingMode == UDMA3 || | |
434 | UDMATimingMode == UDMA5) { | |
435 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1; | |
436 | } else if (UDMATimingMode == UDMA2 || | |
437 | UDMATimingMode == UDMA4) { | |
438 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2; | |
439 | } | |
440 | break; | |
441 | case 1: | |
442 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable); | |
443 | if (UDMAEnable == TRUE) | |
444 | UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable; | |
445 | ||
446 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable | | |
447 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable); | |
448 | ||
449 | if (UDMATimingMode >= UDMA5) | |
450 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable; | |
451 | else if (UDMATimingMode >= UDMA3) | |
452 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable; | |
453 | ||
454 | /* if 80 cable report */ | |
455 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime); | |
456 | ||
457 | if (UDMATimingMode == UDMA0) { | |
458 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0; | |
459 | } else if (UDMATimingMode == UDMA1 || | |
460 | UDMATimingMode == UDMA3 || | |
461 | UDMATimingMode == UDMA5) { | |
462 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1; | |
463 | } else if (UDMATimingMode == UDMA2 || | |
464 | UDMATimingMode == UDMA4) { | |
465 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2; | |
466 | } | |
467 | break; | |
468 | default: | |
469 | funcresult = FALSE; | |
470 | goto funcexit; | |
471 | break; | |
472 | } | |
473 | ||
474 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
475 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
476 | ATAConfiguration_ID_UDMAControl_Size, | |
477 | &UDMAControlRegister); | |
478 | if (result == FALSE) { | |
479 | funcresult = FALSE; | |
480 | goto funcexit; | |
481 | } | |
482 | ||
483 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
484 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
485 | ATAConfiguration_ID_UDMATiming_Size, | |
486 | &UDMATimingRegister); | |
487 | if (result == FALSE) { | |
488 | funcresult = FALSE; | |
489 | goto funcexit; | |
490 | } | |
491 | ||
492 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
493 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
494 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
495 | &IDEIOConfigurationRegister); | |
496 | if (result == FALSE) { | |
497 | funcresult = FALSE; | |
498 | goto funcexit; | |
499 | } | |
500 | ||
501 | goto funcexit; | |
ad41a8a5 | 502 | funcexit: |
482612af | 503 | return funcresult; |
ad41a8a5 KH |
504 | } |
505 | ||
482612af GKH |
506 | static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, |
507 | uint UDMAEnable, uint UDMATimingMode) | |
ad41a8a5 | 508 | { |
482612af GKH |
509 | uint funcresult; |
510 | uint result; | |
511 | uint UDMAControlRegister; | |
512 | uint UDMATimingRegister; | |
513 | ulong IDEIOConfigurationRegister; | |
514 | ||
515 | funcresult = TRUE; | |
516 | ||
517 | UDMAControlRegister = 0; | |
518 | UDMATimingRegister = 0; | |
519 | IDEIOConfigurationRegister = 0; | |
520 | ||
521 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
522 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
523 | ATAConfiguration_ID_UDMAControl_Size, | |
524 | &UDMAControlRegister); | |
525 | if (result == FALSE) { | |
526 | funcresult = FALSE; | |
527 | goto funcexit; | |
528 | } | |
529 | ||
530 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
531 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
532 | ATAConfiguration_ID_UDMATiming_Size, | |
533 | &UDMATimingRegister); | |
534 | if (result == FALSE) { | |
535 | funcresult = FALSE; | |
536 | goto funcexit; | |
537 | } | |
538 | ||
539 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
540 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
541 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
542 | &IDEIOConfigurationRegister); | |
543 | if (result == FALSE) { | |
544 | funcresult = FALSE; | |
545 | goto funcexit; | |
546 | } | |
547 | ||
548 | /* Rom Code will determine the device cable type and ATA 100. */ | |
549 | /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */ | |
550 | /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */ | |
551 | ||
552 | switch (DeviceID) { | |
553 | case 0: | |
554 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable); | |
555 | if (UDMAEnable == TRUE) | |
556 | UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable; | |
557 | ||
558 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable | | |
559 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable); | |
560 | ||
561 | if (UDMATimingMode >= UDMA5) | |
562 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable; | |
563 | else if (UDMATimingMode >= UDMA3) | |
564 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable; | |
565 | ||
566 | /* if 80 cable report */ | |
567 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime); | |
568 | ||
569 | if (UDMATimingMode == UDMA0) { | |
570 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0; | |
571 | } else if (UDMATimingMode == UDMA1 || | |
572 | UDMATimingMode == UDMA3 || | |
573 | UDMATimingMode == UDMA5) { | |
574 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1; | |
575 | } else if (UDMATimingMode == UDMA2 || | |
576 | UDMATimingMode == UDMA4) { | |
577 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2; | |
578 | } | |
579 | break; | |
580 | case 1: | |
581 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable); | |
582 | if (UDMAEnable == TRUE) | |
583 | UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable; | |
584 | ||
585 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable | | |
586 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable); | |
587 | ||
588 | if (UDMATimingMode >= UDMA5) | |
589 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable; | |
590 | else if (UDMATimingMode >= UDMA3) | |
591 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable; | |
592 | ||
593 | /* if 80 cable report */ | |
594 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime); | |
595 | ||
596 | if (UDMATimingMode == UDMA0) { | |
597 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0; | |
598 | } else if (UDMATimingMode == UDMA1 || | |
599 | UDMATimingMode == UDMA3 || | |
600 | UDMATimingMode == UDMA5) { | |
601 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1; | |
602 | } else if (UDMATimingMode == UDMA2 || | |
603 | UDMATimingMode == UDMA4) { | |
604 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2; | |
605 | } | |
606 | break; | |
607 | default: | |
608 | funcresult = FALSE; | |
609 | goto funcexit; | |
610 | break; | |
611 | } | |
612 | ||
613 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
614 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
615 | ATAConfiguration_ID_UDMAControl_Size, | |
616 | &UDMAControlRegister); | |
617 | if (result == FALSE) { | |
618 | funcresult = FALSE; | |
619 | goto funcexit; | |
620 | } | |
621 | ||
622 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
623 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
624 | ATAConfiguration_ID_UDMATiming_Size, | |
625 | &UDMATimingRegister); | |
626 | if (result == FALSE) { | |
627 | funcresult = FALSE; | |
628 | goto funcexit; | |
629 | } | |
630 | ||
631 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
632 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
633 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
634 | &IDEIOConfigurationRegister); | |
635 | if (result == FALSE) { | |
636 | funcresult = FALSE; | |
637 | goto funcexit; | |
638 | } | |
639 | ||
640 | goto funcexit; | |
ad41a8a5 | 641 | funcexit: |
482612af | 642 | return funcresult; |
ad41a8a5 | 643 | } |
c0a5962f GKH |
644 | |
645 | /** | |
646 | * Set port up for dma. | |
647 | * @ap: Port to initialize | |
648 | * | |
649 | * Called just after data structures for each port are | |
650 | * initialized. Allocates space for PRD table if the device | |
651 | * is DMA capable SFF. | |
652 | ||
653 | Some drivers also use this entry point as a chance to allocate driverprivate | |
654 | memory for ap->private_data. | |
655 | ||
656 | * | |
657 | * May be used as the port_start() entry in ata_port_operations. | |
658 | * | |
659 | * LOCKING: | |
660 | * Inherited from caller. | |
661 | */ | |
662 | static int rdc_pata_port_start(struct ata_port *ap) | |
663 | { | |
664 | uint Channel; | |
665 | ||
666 | Channel = ap->port_no; | |
667 | dbgprintf("rdc_pata_port_start Channel: %u \n", Channel); | |
668 | if (ap->ioaddr.bmdma_addr) { | |
669 | return ata_port_start(ap); | |
670 | } else { | |
671 | dbgprintf("rdc_pata_port_start return 0 !!!\n"); | |
672 | return 0; | |
673 | } | |
674 | } | |
675 | ||
676 | static void rdc_pata_port_stop(struct ata_port *ap) | |
677 | { | |
678 | uint Channel; | |
679 | ||
680 | Channel = ap->port_no; | |
681 | ||
682 | dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel); | |
683 | } | |
684 | ||
685 | /** | |
686 | * prereset for PATA host controller | |
687 | * @link: Target link | |
688 | * @deadline: deadline jiffies for the operation | |
689 | * | |
690 | * LOCKING: | |
691 | * None (inherited from caller). | |
692 | */ | |
693 | static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline) | |
694 | { | |
695 | struct pci_dev *pdev; | |
696 | struct ata_port *ap; | |
697 | uint Channel; | |
698 | ||
699 | dbgprintf("rdc_pata_prereset\n"); | |
700 | ||
701 | ap = link->ap; | |
702 | pdev = to_pci_dev(ap->host->dev); | |
703 | ||
704 | Channel = ap->port_no; | |
705 | ||
706 | /* test ATA Decode Enable Bits, should be enable. */ | |
707 | if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) { | |
708 | dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel); | |
709 | return -ENOENT; | |
710 | } else { | |
711 | dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel); | |
712 | return ata_std_prereset(link, deadline); | |
713 | } | |
714 | } | |
715 | ||
716 | /** | |
717 | * Probe host controller cable detect info | |
718 | * @ap: Port for which cable detect info is desired | |
719 | * | |
720 | * Read cable indicator from ATA PCI device's PCI config | |
721 | * register. This register is normally set by firmware (BIOS). | |
722 | * | |
723 | * LOCKING: | |
724 | * None (inherited from caller). | |
725 | */ | |
726 | static int rdc_pata_cable_detect(struct ata_port *ap) | |
727 | { | |
728 | struct pci_dev *pdev; | |
729 | uint Channel; | |
730 | uint Mask; | |
731 | u32 u32Value; | |
732 | ||
733 | dbgprintf("rdc_pata_cable_detect\n"); | |
734 | ||
735 | pdev = to_pci_dev(ap->host->dev); | |
736 | ||
737 | Channel = ap->port_no; | |
738 | ||
739 | if (Channel == 0) | |
740 | Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report; | |
741 | else | |
742 | Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report; | |
743 | ||
744 | /* check BIOS cable detect results */ | |
745 | pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value); | |
746 | ||
747 | if ((u32Value & Mask) == 0) { | |
748 | dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel); | |
749 | return ATA_CBL_PATA40; | |
750 | } else { | |
751 | dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel); | |
752 | return ATA_CBL_PATA80; | |
753 | } | |
754 | } | |
755 | ||
756 | /** | |
757 | * Initialize host controller PATA PIO timings | |
758 | * @ap: Port whose timings we are configuring | |
759 | * @adev: um | |
760 | * | |
761 | * Set PIO mode for device, in host controller PCI config space. | |
762 | * | |
763 | * LOCKING: | |
764 | * None (inherited from caller). | |
765 | */ | |
766 | static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
767 | { | |
768 | struct pci_dev *pdev; | |
769 | uint Channel; | |
770 | uint DeviceID; | |
771 | uint PIOTimingMode; | |
772 | uint PrefetchPostingEnable; | |
773 | ||
774 | dbgprintf("rdc_pata_set_piomode\n"); | |
775 | ||
776 | pdev = to_pci_dev(ap->host->dev); | |
777 | ||
778 | Channel = ap->port_no; | |
779 | DeviceID = adev->devno; | |
780 | /* | |
781 | * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, | |
782 | * XFER_PIO_2, XFER_PIO_3... | |
783 | */ | |
784 | PIOTimingMode = adev->pio_mode - XFER_PIO_0; | |
785 | ||
786 | if (adev->class == ATA_DEV_ATA) { | |
787 | PrefetchPostingEnable = TRUE; | |
788 | } else { | |
789 | /* ATAPI, CD DVD Rom */ | |
790 | PrefetchPostingEnable = FALSE; | |
791 | } | |
792 | ||
793 | /* PIO configuration clears DTE unconditionally. It will be | |
794 | * programmed in set_dmamode which is guaranteed to be called | |
795 | * after set_piomode if any DMA mode is available. | |
796 | */ | |
797 | ||
798 | /* Ensure the UDMA bit is off - it will be turned back on if UDMA is | |
799 | * selected */ | |
800 | ||
801 | if (Channel == 0) { | |
802 | ATAHostAdapter_SetPrimaryPIO( | |
803 | pdev, | |
804 | DeviceID, | |
805 | PIOTimingMode, | |
806 | TRUE,/* DMAEnable, */ | |
807 | PrefetchPostingEnable | |
808 | ); | |
809 | ||
810 | ATAHostAdapter_SetPrimaryUDMA( | |
811 | pdev, | |
812 | DeviceID, | |
813 | FALSE,/* UDMAEnable, */ | |
814 | UDMA0 | |
815 | ); | |
816 | } else { | |
817 | ATAHostAdapter_SetSecondaryPIO( | |
818 | pdev, | |
819 | DeviceID, | |
820 | PIOTimingMode, | |
821 | TRUE,/* DMAEnable, */ | |
822 | PrefetchPostingEnable | |
823 | ); | |
824 | ||
825 | ATAHostAdapter_SetSecondaryUDMA( | |
826 | pdev, | |
827 | DeviceID, | |
828 | FALSE,/* UDMAEnable, */ | |
829 | UDMA0 | |
830 | ); | |
831 | } | |
832 | dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode); | |
833 | } | |
834 | ||
835 | /** | |
836 | * Initialize host controller PATA DMA timings | |
837 | * @ap: Port whose timings we are configuring | |
838 | * @adev: um | |
839 | * | |
840 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
841 | * | |
842 | * LOCKING: | |
843 | * None (inherited from caller). | |
844 | */ | |
845 | static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
846 | { | |
847 | struct pci_dev *pdev; | |
848 | uint Channel; | |
849 | uint DeviceID; | |
850 | uint PIOTimingMode; | |
851 | uint PrefetchPostingEnable; | |
852 | uint DMATimingMode; | |
853 | uint UDMAEnable; | |
854 | ||
855 | dbgprintf("rdc_pata_set_dmamode\n"); | |
856 | ||
857 | pdev = to_pci_dev(ap->host->dev); | |
858 | ||
859 | Channel = ap->port_no; | |
860 | DeviceID = adev->devno; | |
861 | PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */ | |
862 | DMATimingMode = adev->dma_mode; /* UDMA or MDMA */ | |
863 | ||
864 | if (adev->class == ATA_DEV_ATA) { | |
865 | PrefetchPostingEnable = TRUE; | |
866 | } else { | |
867 | /* ATAPI, CD DVD Rom */ | |
868 | PrefetchPostingEnable = FALSE; | |
869 | } | |
870 | ||
871 | if (ap->udma_mask == 0) { | |
872 | /* ata_port dont support udma. depend on hardware spec. */ | |
873 | UDMAEnable = FALSE; | |
874 | } else { | |
875 | UDMAEnable = TRUE; | |
876 | } | |
877 | ||
878 | /*if (ap->mdma_mask == 0) { | |
879 | }*/ | |
880 | ||
881 | if (Channel == 0) { | |
882 | if (DMATimingMode >= XFER_UDMA_0) { | |
883 | /* UDMA */ | |
884 | ATAHostAdapter_SetPrimaryPIO(pdev, | |
885 | DeviceID, | |
886 | PIOTimingMode, | |
887 | TRUE,/*DMAEnable,*/ | |
888 | PrefetchPostingEnable); | |
889 | ||
890 | ATAHostAdapter_SetPrimaryUDMA(pdev, | |
891 | DeviceID, | |
892 | UDMAEnable, | |
893 | DMATimingMode - XFER_UDMA_0); | |
894 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0)); | |
895 | } else { | |
896 | /* MDMA */ | |
897 | ATAHostAdapter_SetPrimaryPIO(pdev, | |
898 | DeviceID, | |
899 | (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */ | |
900 | TRUE,/*DMAEnable,*/ | |
901 | PrefetchPostingEnable); | |
902 | ||
903 | ATAHostAdapter_SetPrimaryUDMA(pdev, | |
904 | DeviceID, | |
905 | FALSE,/*UDMAEnable,*/ | |
906 | UDMA0); | |
907 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0)); | |
908 | } | |
909 | } else { | |
910 | if (DMATimingMode >= XFER_UDMA_0) { | |
911 | /* UDMA */ | |
912 | ATAHostAdapter_SetSecondaryPIO(pdev, | |
913 | DeviceID, | |
914 | PIOTimingMode, | |
915 | TRUE,/*DMAEnable,*/ | |
916 | PrefetchPostingEnable); | |
917 | ||
918 | ATAHostAdapter_SetSecondaryUDMA(pdev, | |
919 | DeviceID, | |
920 | UDMAEnable, | |
921 | DMATimingMode - XFER_UDMA_0); | |
922 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0)); | |
923 | } else { | |
924 | /* MDMA */ | |
925 | ATAHostAdapter_SetSecondaryPIO(pdev, | |
926 | DeviceID, | |
927 | (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */ | |
928 | TRUE,/*DMAEnable,*/ | |
929 | PrefetchPostingEnable); | |
930 | ||
931 | ATAHostAdapter_SetSecondaryUDMA(pdev, | |
932 | DeviceID, | |
933 | FALSE,/*UDMAEnable,*/ | |
934 | UDMA0); | |
935 | dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0)); | |
936 | } | |
937 | } | |
938 | } | |
939 | ||
940 | /* pata host template */ | |
941 | static struct scsi_host_template rdc_pata_sht = { | |
942 | ATA_BMDMA_SHT(DRIVER_NAME), | |
943 | }; | |
944 | ||
945 | static const struct ata_port_operations rdc_pata_ops = { | |
946 | .inherits = &ata_bmdma_port_ops, | |
947 | ||
948 | .port_start = rdc_pata_port_start, | |
949 | .port_stop = rdc_pata_port_stop, | |
950 | .prereset = rdc_pata_prereset, | |
951 | .cable_detect = rdc_pata_cable_detect, | |
952 | .set_piomode = rdc_pata_set_piomode, | |
953 | .set_dmamode = rdc_pata_set_dmamode, | |
954 | }; | |
955 | ||
956 | static struct ata_port_info rdc_pata_port_info[] = { | |
957 | [RDC_17F31011] = { | |
958 | .flags = ATA_FLAG_SLAVE_POSS, | |
959 | .pio_mask = 0x1f, /* pio0-4 */ | |
960 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
961 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
962 | .port_ops = &rdc_pata_ops, | |
963 | }, | |
964 | ||
965 | [RDC_17F31012] = { | |
966 | .flags = ATA_FLAG_SLAVE_POSS, | |
967 | .pio_mask = 0x1f, /* pio0-4 */ | |
968 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
969 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
970 | .port_ops = &rdc_pata_ops, | |
971 | }, | |
972 | }; | |
973 | ||
974 | static int __devinit rdc_init_one(struct pci_dev *pdev, | |
975 | const struct pci_device_id *ent) | |
976 | { | |
977 | /*struct device *dev = &pdev->dev; */ | |
978 | struct ata_port_info port_info[2]; | |
979 | const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] }; | |
980 | ||
981 | int rc; | |
982 | ||
983 | dbgprintf("rdc_init_one\n"); | |
984 | ||
985 | /* no hotplugging support (FIXME) */ /* why??? */ | |
986 | if (!in_module_init) { | |
987 | dbgprintf("rdc_init_one in_module_init == 0 failed \n"); | |
988 | return -ENODEV; | |
989 | } | |
990 | port_info[0] = rdc_pata_port_info[ent->driver_data]; | |
991 | port_info[1] = rdc_pata_port_info[ent->driver_data]; | |
992 | ||
993 | /* enable device and prepare host */ | |
994 | rc = pci_enable_device(pdev); | |
995 | if (rc) { | |
996 | dbgprintf("rdc_init_one pci_enable_device failed \n"); | |
997 | return rc; | |
998 | } | |
999 | /* initialize controller */ | |
1000 | ||
1001 | pci_intx(pdev, 1); /* enable interrupt */ | |
1002 | ||
1003 | return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL); | |
1004 | } | |
1005 | ||
1006 | /* a pci driver */ | |
1007 | static struct pci_driver rdc_pata_driver = { | |
1008 | .name = DRIVER_NAME, | |
1009 | .id_table = rdc_pata_id_table, | |
1010 | .probe = rdc_init_one, | |
1011 | .remove = ata_pci_remove_one, | |
1012 | #ifdef CONFIG_PM | |
1013 | .suspend = ata_pci_device_suspend, | |
1014 | .resume = ata_pci_device_resume, | |
1015 | #endif | |
1016 | }; | |
1017 | ||
1018 | static int __init pata_rdc_init(void) | |
1019 | { | |
1020 | int rc; | |
1021 | ||
1022 | dbgprintf("pata_rdc_init\n"); | |
1023 | rc = pci_register_driver(&rdc_pata_driver); | |
1024 | if (rc) { | |
1025 | dbgprintf("pata_rdc_init faile\n"); | |
1026 | return rc; | |
1027 | } | |
1028 | ||
1029 | in_module_init = 0; | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static void __exit pata_rdc_exit(void) | |
1035 | { | |
1036 | dbgprintf("pata_rdc_exit\n"); | |
1037 | pci_unregister_driver(&rdc_pata_driver); | |
1038 | } | |
1039 | ||
1040 | module_init(pata_rdc_init); | |
1041 | module_exit(pata_rdc_exit); | |
1042 | ||
1043 | MODULE_LICENSE("GPL"); | |
1044 | MODULE_DESCRIPTION("RDC PCI IDE Driver"); | |
1045 | MODULE_VERSION(DRIVER_VERSION); |