Commit | Line | Data |
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ad41a8a5 KH |
1 | #include <linux/kernel.h> |
2 | #include <linux/init.h> | |
3 | #include <linux/module.h> | |
4 | ||
5 | #include <linux/pci.h> | |
6 | #include <linux/device.h> | |
7 | ||
8 | #include <scsi/scsi_host.h> | |
9 | #include <linux/libata.h> | |
10 | ||
11 | #include "pata_rdc.h" | |
12 | ||
ad41a8a5 | 13 | static const struct pci_device_id rdc_pata_id_table[] = { |
1a24bda2 GKH |
14 | { PCI_DEVICE(0x17F3, 0x1011), RDC_17F31011}, |
15 | { PCI_DEVICE(0x17F3, 0x1012), RDC_17F31012}, | |
482612af | 16 | { } /* terminate list */ |
ad41a8a5 | 17 | }; |
ad41a8a5 | 18 | MODULE_DEVICE_TABLE(pci, rdc_pata_id_table); |
ad41a8a5 | 19 | |
482612af GKH |
20 | /* see ATA Host Adapters Standards. */ |
21 | static struct pci_bits ATA_Decode_Enable_Bits[] = { | |
22 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */ | |
23 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */ | |
ad41a8a5 KH |
24 | }; |
25 | ||
c0a5962f | 26 | static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) |
ad41a8a5 | 27 | { |
c0a5962f GKH |
28 | uint funcresult; |
29 | unchar *pchar; | |
30 | uint i; | |
482612af | 31 | |
c0a5962f | 32 | funcresult = TRUE; |
482612af | 33 | |
c0a5962f | 34 | pchar = pBuffer; |
482612af | 35 | |
c0a5962f GKH |
36 | for (i = 0; i < Length; i++) { |
37 | pci_read_config_byte(pdev, Offset, pchar); | |
38 | Offset++; | |
39 | pchar++; | |
482612af | 40 | } |
482612af | 41 | |
c0a5962f | 42 | funcresult = TRUE; |
482612af | 43 | |
c0a5962f GKH |
44 | goto funcexit; |
45 | funcexit: | |
482612af | 46 | |
c0a5962f | 47 | return funcresult; |
ad41a8a5 KH |
48 | } |
49 | ||
c0a5962f GKH |
50 | static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) |
51 | { | |
52 | uint funcresult; | |
53 | unchar *pchar; | |
54 | uint i; | |
ad41a8a5 | 55 | |
c0a5962f | 56 | funcresult = TRUE; |
ad41a8a5 | 57 | |
c0a5962f | 58 | pchar = pBuffer; |
482612af | 59 | |
c0a5962f GKH |
60 | for (i = 0; i < Length; i++) { |
61 | pci_write_config_byte(pdev, Offset, *pchar); | |
62 | Offset++; | |
63 | pchar++; | |
482612af | 64 | } |
ad41a8a5 | 65 | |
c0a5962f | 66 | funcresult = TRUE; |
ad41a8a5 | 67 | |
c0a5962f GKH |
68 | goto funcexit; |
69 | funcexit: | |
ad41a8a5 | 70 | |
c0a5962f | 71 | return funcresult; |
ad41a8a5 KH |
72 | } |
73 | ||
c0a5962f GKH |
74 | static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, |
75 | uint PIOTimingMode, uint DMAEnable, | |
76 | uint PrefetchPostingEnable) | |
ad41a8a5 | 77 | { |
c0a5962f GKH |
78 | uint funcresult; |
79 | uint result; | |
80 | uint ATATimingRegister; | |
81 | uint Device1TimingRegister; | |
ad41a8a5 | 82 | |
c0a5962f | 83 | funcresult = TRUE; |
ad41a8a5 | 84 | |
c0a5962f GKH |
85 | ATATimingRegister = 0; |
86 | Device1TimingRegister = 0; | |
ad41a8a5 | 87 | |
c0a5962f GKH |
88 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
89 | ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, | |
90 | ATAConfiguration_ID_PrimaryTiming_Size, | |
91 | &ATATimingRegister); | |
92 | if (result == FALSE) { | |
93 | funcresult = FALSE; | |
94 | goto funcexit; | |
95 | } | |
ad41a8a5 | 96 | |
c0a5962f GKH |
97 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
98 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
99 | ATAConfiguration_ID_Device1Timing_Size, | |
100 | &Device1TimingRegister); | |
101 | if (result == FALSE) { | |
102 | funcresult = FALSE; | |
103 | goto funcexit; | |
482612af | 104 | } |
ad41a8a5 | 105 | |
c0a5962f | 106 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; |
ad41a8a5 | 107 | |
c0a5962f GKH |
108 | switch (DeviceID) { |
109 | case 0: | |
110 | /* mask clear */ | |
111 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable | | |
112 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable | | |
113 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable | | |
114 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable | | |
115 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode | | |
116 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode); | |
ad41a8a5 | 117 | |
c0a5962f GKH |
118 | if (PIOTimingMode > PIO0) |
119 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; | |
ad41a8a5 | 120 | |
c0a5962f GKH |
121 | if (PIOTimingMode >= PIO3) |
122 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; | |
ad41a8a5 | 123 | |
c0a5962f GKH |
124 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) |
125 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; | |
ad41a8a5 | 126 | |
c0a5962f GKH |
127 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) |
128 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; | |
ad41a8a5 | 129 | |
c0a5962f GKH |
130 | if (PIOTimingMode <= PIO2) |
131 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; | |
132 | else if (PIOTimingMode == PIO3) | |
133 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; | |
134 | else if (PIOTimingMode == PIO4) | |
135 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; | |
ad41a8a5 | 136 | |
c0a5962f GKH |
137 | if (PIOTimingMode <= PIO1) |
138 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; | |
139 | else if (PIOTimingMode == PIO2) | |
140 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; | |
141 | else if (PIOTimingMode <= PIO4) | |
142 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; | |
143 | break; | |
144 | case 1: | |
145 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable | | |
146 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable | | |
147 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable | | |
148 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable); | |
482612af | 149 | |
c0a5962f GKH |
150 | if (PIOTimingMode > PIO0) |
151 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; | |
482612af | 152 | |
c0a5962f GKH |
153 | if (PIOTimingMode >= PIO3) |
154 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; | |
482612af | 155 | |
c0a5962f GKH |
156 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) |
157 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; | |
482612af | 158 | |
c0a5962f GKH |
159 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) |
160 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; | |
482612af | 161 | |
c0a5962f GKH |
162 | Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode | |
163 | ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode); | |
482612af | 164 | |
c0a5962f GKH |
165 | if (PIOTimingMode <= PIO2) |
166 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0; | |
167 | else if (PIOTimingMode == PIO3) | |
168 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1; | |
169 | else if (PIOTimingMode == PIO4) | |
170 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3; | |
482612af | 171 | |
c0a5962f GKH |
172 | if (PIOTimingMode <= PIO1) |
173 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0; | |
174 | else if (PIOTimingMode == PIO2) | |
175 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1; | |
176 | else if (PIOTimingMode <= PIO4) | |
177 | Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2; | |
178 | break; | |
179 | default: | |
180 | funcresult = FALSE; | |
181 | goto funcexit; | |
182 | break; | |
183 | } | |
482612af | 184 | |
c0a5962f GKH |
185 | result = PCIDeviceIO_WritePCIConfiguration(pdev, |
186 | ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, | |
187 | ATAConfiguration_ID_PrimaryTiming_Size, | |
188 | &ATATimingRegister); | |
189 | if (result == FALSE) { | |
190 | funcresult = FALSE; | |
191 | goto funcexit; | |
192 | } | |
482612af | 193 | |
c0a5962f GKH |
194 | result = PCIDeviceIO_WritePCIConfiguration(pdev, |
195 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
196 | ATAConfiguration_ID_Device1Timing_Size, | |
197 | &Device1TimingRegister); | |
198 | if (result == FALSE) { | |
199 | funcresult = FALSE; | |
200 | goto funcexit; | |
482612af | 201 | } |
c0a5962f GKH |
202 | |
203 | goto funcexit; | |
204 | funcexit: | |
205 | ||
206 | return funcresult; | |
ad41a8a5 KH |
207 | } |
208 | ||
c0a5962f GKH |
209 | static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, |
210 | uint PIOTimingMode, uint DMAEnable, | |
211 | uint PrefetchPostingEnable) | |
ad41a8a5 | 212 | { |
c0a5962f GKH |
213 | uint funcresult; |
214 | uint result; | |
215 | uint ATATimingRegister; | |
216 | uint Device1TimingRegister; | |
482612af | 217 | |
c0a5962f | 218 | funcresult = TRUE; |
482612af | 219 | |
c0a5962f GKH |
220 | ATATimingRegister = 0; |
221 | Device1TimingRegister = 0; | |
482612af | 222 | |
c0a5962f GKH |
223 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
224 | ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, | |
225 | ATAConfiguration_ID_SecondaryTiming_Size, | |
226 | &ATATimingRegister); | |
227 | if (result == FALSE) { | |
228 | funcresult = FALSE; | |
229 | goto funcexit; | |
482612af GKH |
230 | } |
231 | ||
c0a5962f GKH |
232 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, |
233 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
234 | ATAConfiguration_ID_Device1Timing_Size, | |
235 | &Device1TimingRegister); | |
236 | if (result == FALSE) { | |
237 | funcresult = FALSE; | |
238 | goto funcexit; | |
482612af GKH |
239 | } |
240 | ||
c0a5962f | 241 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; |
482612af | 242 | |
c0a5962f GKH |
243 | switch (DeviceID) { |
244 | case 0: | |
245 | /* mask clear */ | |
246 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable | | |
247 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable | | |
248 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable | | |
249 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable | | |
250 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode | | |
251 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode); | |
482612af | 252 | |
c0a5962f GKH |
253 | if (PIOTimingMode > PIO0) |
254 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; | |
482612af | 255 | |
c0a5962f GKH |
256 | if (PIOTimingMode >= PIO3) |
257 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; | |
482612af GKH |
258 | |
259 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) | |
260 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; | |
261 | ||
262 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) | |
263 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; | |
264 | ||
265 | if (PIOTimingMode <= PIO2) | |
266 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; | |
267 | else if (PIOTimingMode == PIO3) | |
268 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; | |
269 | else if (PIOTimingMode == PIO4) | |
270 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; | |
271 | ||
272 | if (PIOTimingMode <= PIO1) | |
273 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; | |
274 | else if (PIOTimingMode == PIO2) | |
275 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; | |
276 | else if (PIOTimingMode <= PIO4) | |
277 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; | |
278 | break; | |
279 | case 1: | |
280 | ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable | | |
281 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable | | |
282 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable | | |
283 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable); | |
284 | ||
285 | if (PIOTimingMode > PIO0) | |
286 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; | |
287 | ||
288 | if (PIOTimingMode >= PIO3) | |
289 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; | |
290 | ||
291 | if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) | |
292 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; | |
293 | ||
294 | if (DMAEnable == TRUE && PIOTimingMode >= PIO2) | |
295 | ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; | |
296 | ||
297 | Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode | | |
298 | ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode); | |
299 | ||
300 | if (PIOTimingMode <= PIO2) | |
301 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0; | |
302 | else if (PIOTimingMode == PIO3) | |
303 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1; | |
304 | else if (PIOTimingMode == PIO4) | |
305 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3; | |
306 | ||
307 | if (PIOTimingMode <= PIO1) | |
308 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0; | |
309 | else if (PIOTimingMode == PIO2) | |
310 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1; | |
311 | else if (PIOTimingMode <= PIO4) | |
312 | Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2; | |
313 | break; | |
314 | default: | |
315 | funcresult = FALSE; | |
316 | goto funcexit; | |
317 | break; | |
318 | } | |
319 | ||
320 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
321 | ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, | |
322 | ATAConfiguration_ID_SecondaryTiming_Size, | |
323 | &ATATimingRegister); | |
324 | if (result == FALSE) { | |
325 | funcresult = FALSE; | |
326 | goto funcexit; | |
327 | } | |
328 | ||
329 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
330 | ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, | |
331 | ATAConfiguration_ID_Device1Timing_Size, | |
332 | &Device1TimingRegister); | |
333 | if (result == FALSE) { | |
334 | funcresult = FALSE; | |
335 | goto funcexit; | |
336 | } | |
337 | ||
338 | goto funcexit; | |
ad41a8a5 | 339 | funcexit: |
482612af | 340 | return funcresult; |
ad41a8a5 KH |
341 | } |
342 | ||
482612af GKH |
343 | static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, |
344 | uint UDMAEnable, uint UDMATimingMode) | |
ad41a8a5 | 345 | { |
482612af GKH |
346 | uint funcresult; |
347 | uint result; | |
348 | uint UDMAControlRegister; | |
349 | uint UDMATimingRegister; | |
350 | ulong IDEIOConfigurationRegister; | |
351 | ||
352 | funcresult = TRUE; | |
353 | UDMAControlRegister = 0; | |
354 | UDMATimingRegister = 0; | |
355 | IDEIOConfigurationRegister = 0; | |
356 | ||
357 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
358 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
359 | ATAConfiguration_ID_UDMAControl_Size, | |
360 | &UDMAControlRegister); | |
361 | if (result == FALSE) { | |
362 | funcresult = FALSE; | |
363 | goto funcexit; | |
364 | } | |
365 | ||
366 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
367 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
368 | ATAConfiguration_ID_UDMATiming_Size, | |
369 | &UDMATimingRegister); | |
370 | if (result == FALSE) { | |
371 | funcresult = FALSE; | |
372 | goto funcexit; | |
373 | } | |
374 | ||
375 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
376 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
377 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
378 | &IDEIOConfigurationRegister); | |
379 | if (result == FALSE) { | |
380 | funcresult = FALSE; | |
381 | goto funcexit; | |
382 | } | |
383 | ||
384 | /*Rom Code will determine the device cable type and ATA 100.*/ | |
385 | /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/ | |
386 | /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/ | |
387 | ||
388 | switch (DeviceID) { | |
389 | case 0: | |
390 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable); | |
391 | if (UDMAEnable == TRUE) | |
392 | UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable; | |
393 | ||
394 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable | | |
395 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable); | |
396 | ||
397 | if (UDMATimingMode >= UDMA5) | |
398 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable; | |
399 | else if (UDMATimingMode >= UDMA3) | |
400 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable; | |
401 | ||
402 | /* if 80 cable report */ | |
403 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime); | |
404 | ||
405 | if (UDMATimingMode == UDMA0) { | |
406 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0; | |
407 | } else if (UDMATimingMode == UDMA1 || | |
408 | UDMATimingMode == UDMA3 || | |
409 | UDMATimingMode == UDMA5) { | |
410 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1; | |
411 | } else if (UDMATimingMode == UDMA2 || | |
412 | UDMATimingMode == UDMA4) { | |
413 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2; | |
414 | } | |
415 | break; | |
416 | case 1: | |
417 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable); | |
418 | if (UDMAEnable == TRUE) | |
419 | UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable; | |
420 | ||
421 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable | | |
422 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable); | |
423 | ||
424 | if (UDMATimingMode >= UDMA5) | |
425 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable; | |
426 | else if (UDMATimingMode >= UDMA3) | |
427 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable; | |
428 | ||
429 | /* if 80 cable report */ | |
430 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime); | |
431 | ||
432 | if (UDMATimingMode == UDMA0) { | |
433 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0; | |
434 | } else if (UDMATimingMode == UDMA1 || | |
435 | UDMATimingMode == UDMA3 || | |
436 | UDMATimingMode == UDMA5) { | |
437 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1; | |
438 | } else if (UDMATimingMode == UDMA2 || | |
439 | UDMATimingMode == UDMA4) { | |
440 | UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2; | |
441 | } | |
442 | break; | |
443 | default: | |
444 | funcresult = FALSE; | |
445 | goto funcexit; | |
446 | break; | |
447 | } | |
448 | ||
449 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
450 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
451 | ATAConfiguration_ID_UDMAControl_Size, | |
452 | &UDMAControlRegister); | |
453 | if (result == FALSE) { | |
454 | funcresult = FALSE; | |
455 | goto funcexit; | |
456 | } | |
457 | ||
458 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
459 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
460 | ATAConfiguration_ID_UDMATiming_Size, | |
461 | &UDMATimingRegister); | |
462 | if (result == FALSE) { | |
463 | funcresult = FALSE; | |
464 | goto funcexit; | |
465 | } | |
466 | ||
467 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
468 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
469 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
470 | &IDEIOConfigurationRegister); | |
471 | if (result == FALSE) { | |
472 | funcresult = FALSE; | |
473 | goto funcexit; | |
474 | } | |
475 | ||
476 | goto funcexit; | |
ad41a8a5 | 477 | funcexit: |
482612af | 478 | return funcresult; |
ad41a8a5 KH |
479 | } |
480 | ||
482612af GKH |
481 | static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, |
482 | uint UDMAEnable, uint UDMATimingMode) | |
ad41a8a5 | 483 | { |
482612af GKH |
484 | uint funcresult; |
485 | uint result; | |
486 | uint UDMAControlRegister; | |
487 | uint UDMATimingRegister; | |
488 | ulong IDEIOConfigurationRegister; | |
489 | ||
490 | funcresult = TRUE; | |
491 | ||
492 | UDMAControlRegister = 0; | |
493 | UDMATimingRegister = 0; | |
494 | IDEIOConfigurationRegister = 0; | |
495 | ||
496 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
497 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
498 | ATAConfiguration_ID_UDMAControl_Size, | |
499 | &UDMAControlRegister); | |
500 | if (result == FALSE) { | |
501 | funcresult = FALSE; | |
502 | goto funcexit; | |
503 | } | |
504 | ||
505 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
506 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
507 | ATAConfiguration_ID_UDMATiming_Size, | |
508 | &UDMATimingRegister); | |
509 | if (result == FALSE) { | |
510 | funcresult = FALSE; | |
511 | goto funcexit; | |
512 | } | |
513 | ||
514 | result = PCIDeviceIO_ReadPCIConfiguration(pdev, | |
515 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
516 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
517 | &IDEIOConfigurationRegister); | |
518 | if (result == FALSE) { | |
519 | funcresult = FALSE; | |
520 | goto funcexit; | |
521 | } | |
522 | ||
523 | /* Rom Code will determine the device cable type and ATA 100. */ | |
524 | /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */ | |
525 | /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */ | |
526 | ||
527 | switch (DeviceID) { | |
528 | case 0: | |
529 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable); | |
530 | if (UDMAEnable == TRUE) | |
531 | UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable; | |
532 | ||
533 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable | | |
534 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable); | |
535 | ||
536 | if (UDMATimingMode >= UDMA5) | |
537 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable; | |
538 | else if (UDMATimingMode >= UDMA3) | |
539 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable; | |
540 | ||
541 | /* if 80 cable report */ | |
542 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime); | |
543 | ||
544 | if (UDMATimingMode == UDMA0) { | |
545 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0; | |
546 | } else if (UDMATimingMode == UDMA1 || | |
547 | UDMATimingMode == UDMA3 || | |
548 | UDMATimingMode == UDMA5) { | |
549 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1; | |
550 | } else if (UDMATimingMode == UDMA2 || | |
551 | UDMATimingMode == UDMA4) { | |
552 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2; | |
553 | } | |
554 | break; | |
555 | case 1: | |
556 | UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable); | |
557 | if (UDMAEnable == TRUE) | |
558 | UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable; | |
559 | ||
560 | IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable | | |
561 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable); | |
562 | ||
563 | if (UDMATimingMode >= UDMA5) | |
564 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable; | |
565 | else if (UDMATimingMode >= UDMA3) | |
566 | IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable; | |
567 | ||
568 | /* if 80 cable report */ | |
569 | UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime); | |
570 | ||
571 | if (UDMATimingMode == UDMA0) { | |
572 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0; | |
573 | } else if (UDMATimingMode == UDMA1 || | |
574 | UDMATimingMode == UDMA3 || | |
575 | UDMATimingMode == UDMA5) { | |
576 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1; | |
577 | } else if (UDMATimingMode == UDMA2 || | |
578 | UDMATimingMode == UDMA4) { | |
579 | UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2; | |
580 | } | |
581 | break; | |
582 | default: | |
583 | funcresult = FALSE; | |
584 | goto funcexit; | |
585 | break; | |
586 | } | |
587 | ||
588 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
589 | ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, | |
590 | ATAConfiguration_ID_UDMAControl_Size, | |
591 | &UDMAControlRegister); | |
592 | if (result == FALSE) { | |
593 | funcresult = FALSE; | |
594 | goto funcexit; | |
595 | } | |
596 | ||
597 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
598 | ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, | |
599 | ATAConfiguration_ID_UDMATiming_Size, | |
600 | &UDMATimingRegister); | |
601 | if (result == FALSE) { | |
602 | funcresult = FALSE; | |
603 | goto funcexit; | |
604 | } | |
605 | ||
606 | result = PCIDeviceIO_WritePCIConfiguration(pdev, | |
607 | ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, | |
608 | ATAConfiguration_ID_IDEIOConfiguration_Size, | |
609 | &IDEIOConfigurationRegister); | |
610 | if (result == FALSE) { | |
611 | funcresult = FALSE; | |
612 | goto funcexit; | |
613 | } | |
614 | ||
615 | goto funcexit; | |
ad41a8a5 | 616 | funcexit: |
482612af | 617 | return funcresult; |
ad41a8a5 | 618 | } |
c0a5962f GKH |
619 | |
620 | /** | |
621 | * Set port up for dma. | |
622 | * @ap: Port to initialize | |
623 | * | |
624 | * Called just after data structures for each port are | |
625 | * initialized. Allocates space for PRD table if the device | |
626 | * is DMA capable SFF. | |
627 | ||
628 | Some drivers also use this entry point as a chance to allocate driverprivate | |
629 | memory for ap->private_data. | |
630 | ||
631 | * | |
632 | * May be used as the port_start() entry in ata_port_operations. | |
633 | * | |
634 | * LOCKING: | |
635 | * Inherited from caller. | |
636 | */ | |
637 | static int rdc_pata_port_start(struct ata_port *ap) | |
638 | { | |
639 | uint Channel; | |
640 | ||
641 | Channel = ap->port_no; | |
da9dbc00 | 642 | dev_dbg(ap->dev, "%s: Channel: %u\n", __func__, Channel); |
c0a5962f GKH |
643 | if (ap->ioaddr.bmdma_addr) { |
644 | return ata_port_start(ap); | |
645 | } else { | |
da9dbc00 | 646 | dev_dbg(ap->dev, "%s: return 0!!!\n", __func__); |
c0a5962f GKH |
647 | return 0; |
648 | } | |
649 | } | |
650 | ||
651 | static void rdc_pata_port_stop(struct ata_port *ap) | |
652 | { | |
653 | uint Channel; | |
654 | ||
655 | Channel = ap->port_no; | |
656 | ||
da9dbc00 | 657 | dev_dbg(ap->dev, "%s Channel: %u\n", __func__, Channel); |
c0a5962f GKH |
658 | } |
659 | ||
660 | /** | |
661 | * prereset for PATA host controller | |
662 | * @link: Target link | |
663 | * @deadline: deadline jiffies for the operation | |
664 | * | |
665 | * LOCKING: | |
666 | * None (inherited from caller). | |
667 | */ | |
668 | static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline) | |
669 | { | |
670 | struct pci_dev *pdev; | |
671 | struct ata_port *ap; | |
672 | uint Channel; | |
673 | ||
da9dbc00 | 674 | dev_dbg(link->ap->dev, "%s\n", __func__); |
c0a5962f GKH |
675 | |
676 | ap = link->ap; | |
677 | pdev = to_pci_dev(ap->host->dev); | |
678 | ||
679 | Channel = ap->port_no; | |
680 | ||
681 | /* test ATA Decode Enable Bits, should be enable. */ | |
682 | if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) { | |
da9dbc00 GKH |
683 | dev_dbg(link->ap->dev, "%s: Channel: %u, Decode Disable\n", |
684 | __func__, Channel); | |
c0a5962f GKH |
685 | return -ENOENT; |
686 | } else { | |
da9dbc00 GKH |
687 | dev_dbg(link->ap->dev, "%s: Channel: %u, Decode Enable\n", |
688 | __func__, Channel); | |
c0a5962f GKH |
689 | return ata_std_prereset(link, deadline); |
690 | } | |
691 | } | |
692 | ||
693 | /** | |
694 | * Probe host controller cable detect info | |
695 | * @ap: Port for which cable detect info is desired | |
696 | * | |
697 | * Read cable indicator from ATA PCI device's PCI config | |
698 | * register. This register is normally set by firmware (BIOS). | |
699 | * | |
700 | * LOCKING: | |
701 | * None (inherited from caller). | |
702 | */ | |
703 | static int rdc_pata_cable_detect(struct ata_port *ap) | |
704 | { | |
705 | struct pci_dev *pdev; | |
706 | uint Channel; | |
707 | uint Mask; | |
708 | u32 u32Value; | |
709 | ||
da9dbc00 | 710 | dev_dbg(ap->dev, "%s\n", __func__); |
c0a5962f GKH |
711 | |
712 | pdev = to_pci_dev(ap->host->dev); | |
713 | ||
714 | Channel = ap->port_no; | |
715 | ||
716 | if (Channel == 0) | |
717 | Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report; | |
718 | else | |
719 | Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report; | |
720 | ||
721 | /* check BIOS cable detect results */ | |
722 | pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value); | |
723 | ||
724 | if ((u32Value & Mask) == 0) { | |
da9dbc00 GKH |
725 | dev_dbg(ap->dev, "%s: Channel: %u, PATA40 \n", |
726 | __func__, Channel); | |
c0a5962f GKH |
727 | return ATA_CBL_PATA40; |
728 | } else { | |
da9dbc00 GKH |
729 | dev_dbg(ap->dev, "%s: Channel: %u, PATA80 \n", |
730 | __func__, Channel); | |
c0a5962f GKH |
731 | return ATA_CBL_PATA80; |
732 | } | |
733 | } | |
734 | ||
735 | /** | |
736 | * Initialize host controller PATA PIO timings | |
737 | * @ap: Port whose timings we are configuring | |
738 | * @adev: um | |
739 | * | |
740 | * Set PIO mode for device, in host controller PCI config space. | |
741 | * | |
742 | * LOCKING: | |
743 | * None (inherited from caller). | |
744 | */ | |
745 | static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
746 | { | |
747 | struct pci_dev *pdev; | |
748 | uint Channel; | |
749 | uint DeviceID; | |
750 | uint PIOTimingMode; | |
751 | uint PrefetchPostingEnable; | |
752 | ||
da9dbc00 | 753 | dev_dbg(ap->dev, "%s\n", __func__); |
c0a5962f GKH |
754 | |
755 | pdev = to_pci_dev(ap->host->dev); | |
756 | ||
757 | Channel = ap->port_no; | |
758 | DeviceID = adev->devno; | |
759 | /* | |
760 | * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, | |
761 | * XFER_PIO_2, XFER_PIO_3... | |
762 | */ | |
763 | PIOTimingMode = adev->pio_mode - XFER_PIO_0; | |
764 | ||
765 | if (adev->class == ATA_DEV_ATA) { | |
766 | PrefetchPostingEnable = TRUE; | |
767 | } else { | |
768 | /* ATAPI, CD DVD Rom */ | |
769 | PrefetchPostingEnable = FALSE; | |
770 | } | |
771 | ||
772 | /* PIO configuration clears DTE unconditionally. It will be | |
773 | * programmed in set_dmamode which is guaranteed to be called | |
774 | * after set_piomode if any DMA mode is available. | |
775 | */ | |
776 | ||
777 | /* Ensure the UDMA bit is off - it will be turned back on if UDMA is | |
778 | * selected */ | |
779 | ||
780 | if (Channel == 0) { | |
781 | ATAHostAdapter_SetPrimaryPIO( | |
782 | pdev, | |
783 | DeviceID, | |
784 | PIOTimingMode, | |
785 | TRUE,/* DMAEnable, */ | |
786 | PrefetchPostingEnable | |
787 | ); | |
788 | ||
789 | ATAHostAdapter_SetPrimaryUDMA( | |
790 | pdev, | |
791 | DeviceID, | |
792 | FALSE,/* UDMAEnable, */ | |
793 | UDMA0 | |
794 | ); | |
795 | } else { | |
796 | ATAHostAdapter_SetSecondaryPIO( | |
797 | pdev, | |
798 | DeviceID, | |
799 | PIOTimingMode, | |
800 | TRUE,/* DMAEnable, */ | |
801 | PrefetchPostingEnable | |
802 | ); | |
803 | ||
804 | ATAHostAdapter_SetSecondaryUDMA( | |
805 | pdev, | |
806 | DeviceID, | |
807 | FALSE,/* UDMAEnable, */ | |
808 | UDMA0 | |
809 | ); | |
810 | } | |
da9dbc00 GKH |
811 | dev_dbg(ap->dev, "%s: Channel: %u, DeviceID: %u, PIO: %d\n", |
812 | __func__, Channel, DeviceID, PIOTimingMode); | |
c0a5962f GKH |
813 | } |
814 | ||
815 | /** | |
816 | * Initialize host controller PATA DMA timings | |
817 | * @ap: Port whose timings we are configuring | |
818 | * @adev: um | |
819 | * | |
820 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
821 | * | |
822 | * LOCKING: | |
823 | * None (inherited from caller). | |
824 | */ | |
825 | static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
826 | { | |
827 | struct pci_dev *pdev; | |
828 | uint Channel; | |
829 | uint DeviceID; | |
830 | uint PIOTimingMode; | |
831 | uint PrefetchPostingEnable; | |
832 | uint DMATimingMode; | |
833 | uint UDMAEnable; | |
834 | ||
da9dbc00 | 835 | dev_dbg(ap->dev, "%s\n", __func__); |
c0a5962f GKH |
836 | |
837 | pdev = to_pci_dev(ap->host->dev); | |
838 | ||
839 | Channel = ap->port_no; | |
840 | DeviceID = adev->devno; | |
841 | PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */ | |
842 | DMATimingMode = adev->dma_mode; /* UDMA or MDMA */ | |
843 | ||
844 | if (adev->class == ATA_DEV_ATA) { | |
845 | PrefetchPostingEnable = TRUE; | |
846 | } else { | |
847 | /* ATAPI, CD DVD Rom */ | |
848 | PrefetchPostingEnable = FALSE; | |
849 | } | |
850 | ||
851 | if (ap->udma_mask == 0) { | |
852 | /* ata_port dont support udma. depend on hardware spec. */ | |
853 | UDMAEnable = FALSE; | |
854 | } else { | |
855 | UDMAEnable = TRUE; | |
856 | } | |
857 | ||
858 | /*if (ap->mdma_mask == 0) { | |
859 | }*/ | |
860 | ||
861 | if (Channel == 0) { | |
862 | if (DMATimingMode >= XFER_UDMA_0) { | |
863 | /* UDMA */ | |
864 | ATAHostAdapter_SetPrimaryPIO(pdev, | |
865 | DeviceID, | |
866 | PIOTimingMode, | |
867 | TRUE,/*DMAEnable,*/ | |
868 | PrefetchPostingEnable); | |
869 | ||
870 | ATAHostAdapter_SetPrimaryUDMA(pdev, | |
871 | DeviceID, | |
872 | UDMAEnable, | |
873 | DMATimingMode - XFER_UDMA_0); | |
da9dbc00 GKH |
874 | dev_dbg(ap->dev, |
875 | "%s: Channel: %u, DeviceID: %u, UDMA: %u\n", | |
876 | __func__, Channel, DeviceID, | |
877 | (uint)(DMATimingMode - XFER_UDMA_0)); | |
c0a5962f GKH |
878 | } else { |
879 | /* MDMA */ | |
880 | ATAHostAdapter_SetPrimaryPIO(pdev, | |
881 | DeviceID, | |
882 | (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */ | |
883 | TRUE,/*DMAEnable,*/ | |
884 | PrefetchPostingEnable); | |
885 | ||
886 | ATAHostAdapter_SetPrimaryUDMA(pdev, | |
887 | DeviceID, | |
888 | FALSE,/*UDMAEnable,*/ | |
889 | UDMA0); | |
da9dbc00 GKH |
890 | dev_dbg(ap->dev, |
891 | "%s: Channel: %u, DeviceID: %u, MDMA: %u\n", | |
892 | __func__, Channel, DeviceID, | |
893 | (uint)(DMATimingMode - XFER_MW_DMA_0)); | |
c0a5962f GKH |
894 | } |
895 | } else { | |
896 | if (DMATimingMode >= XFER_UDMA_0) { | |
897 | /* UDMA */ | |
898 | ATAHostAdapter_SetSecondaryPIO(pdev, | |
899 | DeviceID, | |
900 | PIOTimingMode, | |
901 | TRUE,/*DMAEnable,*/ | |
902 | PrefetchPostingEnable); | |
903 | ||
904 | ATAHostAdapter_SetSecondaryUDMA(pdev, | |
905 | DeviceID, | |
906 | UDMAEnable, | |
907 | DMATimingMode - XFER_UDMA_0); | |
da9dbc00 GKH |
908 | dev_dbg(ap->dev, |
909 | "%s: Channel: %u, DeviceID: %u, UDMA: %u\n", | |
910 | __func__, Channel, DeviceID, | |
911 | (uint)(DMATimingMode - XFER_UDMA_0)); | |
c0a5962f GKH |
912 | } else { |
913 | /* MDMA */ | |
914 | ATAHostAdapter_SetSecondaryPIO(pdev, | |
915 | DeviceID, | |
916 | (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */ | |
917 | TRUE,/*DMAEnable,*/ | |
918 | PrefetchPostingEnable); | |
919 | ||
920 | ATAHostAdapter_SetSecondaryUDMA(pdev, | |
921 | DeviceID, | |
922 | FALSE,/*UDMAEnable,*/ | |
923 | UDMA0); | |
da9dbc00 GKH |
924 | dev_dbg(ap->dev, |
925 | "%s: Channel: %u, DeviceID: %u, MDMA: %u \n", | |
926 | __func__, Channel, DeviceID, | |
927 | (uint)(DMATimingMode - XFER_MW_DMA_0)); | |
c0a5962f GKH |
928 | } |
929 | } | |
930 | } | |
931 | ||
932 | /* pata host template */ | |
933 | static struct scsi_host_template rdc_pata_sht = { | |
0b77ca66 | 934 | ATA_BMDMA_SHT(KBUILD_MODNAME), |
c0a5962f GKH |
935 | }; |
936 | ||
6b23e310 | 937 | static struct ata_port_operations rdc_pata_ops = { |
c0a5962f GKH |
938 | .inherits = &ata_bmdma_port_ops, |
939 | ||
940 | .port_start = rdc_pata_port_start, | |
941 | .port_stop = rdc_pata_port_stop, | |
942 | .prereset = rdc_pata_prereset, | |
943 | .cable_detect = rdc_pata_cable_detect, | |
944 | .set_piomode = rdc_pata_set_piomode, | |
945 | .set_dmamode = rdc_pata_set_dmamode, | |
946 | }; | |
947 | ||
948 | static struct ata_port_info rdc_pata_port_info[] = { | |
949 | [RDC_17F31011] = { | |
950 | .flags = ATA_FLAG_SLAVE_POSS, | |
951 | .pio_mask = 0x1f, /* pio0-4 */ | |
952 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
953 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
954 | .port_ops = &rdc_pata_ops, | |
955 | }, | |
956 | ||
957 | [RDC_17F31012] = { | |
958 | .flags = ATA_FLAG_SLAVE_POSS, | |
959 | .pio_mask = 0x1f, /* pio0-4 */ | |
960 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
961 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
962 | .port_ops = &rdc_pata_ops, | |
963 | }, | |
964 | }; | |
965 | ||
966 | static int __devinit rdc_init_one(struct pci_dev *pdev, | |
967 | const struct pci_device_id *ent) | |
968 | { | |
c0a5962f GKH |
969 | struct ata_port_info port_info[2]; |
970 | const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] }; | |
971 | ||
972 | int rc; | |
973 | ||
da9dbc00 | 974 | dev_dbg(&pdev->dev, "%s\n", __func__); |
c0a5962f | 975 | |
c0a5962f GKH |
976 | port_info[0] = rdc_pata_port_info[ent->driver_data]; |
977 | port_info[1] = rdc_pata_port_info[ent->driver_data]; | |
978 | ||
979 | /* enable device and prepare host */ | |
980 | rc = pci_enable_device(pdev); | |
981 | if (rc) { | |
da9dbc00 | 982 | dev_dbg(&pdev->dev, "%s pci_enable_device failed\n", __func__); |
c0a5962f GKH |
983 | return rc; |
984 | } | |
c0a5962f | 985 | |
da9dbc00 GKH |
986 | /* enable interrupt */ |
987 | pci_intx(pdev, 1); | |
c0a5962f GKH |
988 | |
989 | return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL); | |
990 | } | |
991 | ||
992 | /* a pci driver */ | |
993 | static struct pci_driver rdc_pata_driver = { | |
0b77ca66 | 994 | .name = KBUILD_MODNAME, |
c0a5962f GKH |
995 | .id_table = rdc_pata_id_table, |
996 | .probe = rdc_init_one, | |
997 | .remove = ata_pci_remove_one, | |
998 | #ifdef CONFIG_PM | |
999 | .suspend = ata_pci_device_suspend, | |
1000 | .resume = ata_pci_device_resume, | |
1001 | #endif | |
1002 | }; | |
1003 | ||
1004 | static int __init pata_rdc_init(void) | |
1005 | { | |
da9dbc00 | 1006 | return pci_register_driver(&rdc_pata_driver); |
c0a5962f GKH |
1007 | } |
1008 | ||
1009 | static void __exit pata_rdc_exit(void) | |
1010 | { | |
c0a5962f GKH |
1011 | pci_unregister_driver(&rdc_pata_driver); |
1012 | } | |
1013 | ||
1014 | module_init(pata_rdc_init); | |
1015 | module_exit(pata_rdc_exit); | |
1016 | ||
1017 | MODULE_LICENSE("GPL"); | |
1018 | MODULE_DESCRIPTION("RDC PCI IDE Driver"); |