[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / staging / nanohub / chub.h

/*
 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
 *
 * Boojin Kim <boojin.kim@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __CONTEXTHUB_IPC_H_
#define __CONTEXTHUB_IPC_H_

#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/wakelock.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/semaphore.h>
#include <linux/platform_data/nanohub.h>
#include <linux/sched/clock.h>
#include <linux/sched/signal.h>
#include "chub_ipc.h"
#include "chub_log.h"

#define WAIT_TRY_CNT (3)
#define RESET_WAIT_TRY_CNT (10)
#define WAIT_CHUB_MS (100)

/* utils for nanohub main */
#define wait_event_interruptible_timeout_locked(q, cond, tmo)		\
({									\
	long __ret = (tmo);						\
	DEFINE_WAIT(__wait);						\
	if (!(cond)) {							\
		for (;;) {						\
			__wait.flags &= ~WQ_FLAG_EXCLUSIVE;		\
			if (list_empty(&__wait.entry))			\
				__add_wait_queue_entry_tail(&(q), &__wait);	\
			set_current_state(TASK_INTERRUPTIBLE);		\
			if ((cond))					\
				break;					\
			if (signal_pending(current)) {			\
				__ret = -ERESTARTSYS;			\
				break;					\
			}						\
			spin_unlock_irq(&(q).lock);			\
			__ret = schedule_timeout(__ret);		\
			spin_lock_irq(&(q).lock);			\
			if (!__ret) {					\
				if ((cond))				\
					__ret = 1;			\
				break;					\
			}						\
		}							\
		__set_current_state(TASK_RUNNING);			\
		if (!list_empty(&__wait.entry))				\
			list_del_init(&__wait.entry);			\
		else if (__ret == -ERESTARTSYS &&			\
			 /*reimplementation of wait_abort_exclusive() */\
			 waitqueue_active(&(q)))			\
			__wake_up_locked_key(&(q), TASK_INTERRUPTIBLE,	\
			NULL);						\
	} else {							\
		__ret = 1;						\
	}								\
	__ret;								\
})

#define CHUB_RESET_ENABLE
enum mailbox_event {
	MAILBOX_EVT_UTC_MAX = IPC_DEBUG_UTC_MAX,
	MAILBOX_EVT_DUMP_STATUS = IPC_DEBUG_DUMP_STATUS,
	MAILBOX_EVT_WAKEUP,
	MAILBOX_EVT_WAKEUP_CLR,
	MAILBOX_EVT_ERASE_SHARED,
	MAILBOX_EVT_ENABLE_IRQ,
	MAILBOX_EVT_DISABLE_IRQ,
	MAILBOX_EVT_RESET_EVT_START,
	MAILBOX_EVT_INIT_IPC,
	MAILBOX_EVT_POWER_ON,
	MAILBOX_EVT_CHUB_ALIVE,
	MAILBOX_EVT_SHUTDOWN,
	MAILBOX_EVT_RESET,
	MAILBOX_EVT_MAX,
};

enum chub_status {
	CHUB_ST_NO_POWER,
	CHUB_ST_POWER_ON,
	CHUB_ST_RUN,
	CHUB_ST_SHUTDOWN,
	CHUB_ST_NO_RESPONSE,
	CHUB_ST_ERR,
	CHUB_ST_HANG,
};

struct read_wait {
	atomic_t cnt;
	volatile u32 flag;
	wait_queue_head_t event;
};

struct recv_ctrl {
	unsigned long order;
	volatile unsigned long container[IRQ_EVT_CH_MAX];
};

struct chub_alive {
	unsigned int flag;
	wait_queue_head_t event;
};

#ifdef USE_EXYNOS_LOG
#define CHUB_DBG_DIR "/data/exynos/log/chub"
#else
#define CHUB_DBG_DIR "/data"
#endif

enum chub_err_type {
	CHUB_ERR_NONE,
	CHUB_ERR_EVTQ_EMTPY, /* ap error */
	CHUB_ERR_READ_FAIL,
	CHUB_ERR_WRITE_FAIL,
	CHUB_ERR_EVTQ_NO_HW_TRIGGER,
	CHUB_ERR_CHUB_NO_RESPONSE, /* 5 */
	CHUB_ERR_ITMON,
	CHUB_ERR_FW_FAULT, /* chub error */
	CHUB_ERR_FW_WDT, /* 8 */
	CHUB_ERR_NEED_RESET,
	CHUB_ERR_FW_ERROR = CHUB_ERR_NEED_RESET,
	CHUB_ERR_COMMS_NACK, /* ap comms error */
	CHUB_ERR_COMMS_BUSY,
	CHUB_ERR_COMMS_UNKNOWN,
	CHUB_ERR_COMMS,
	CHUB_ERR_RESET_CNT,
	CHUB_ERR_NANOHUB, /* nanohub dbg error */
	CHUB_ERR_MAX,
};

struct contexthub_baaw_info {
	unsigned int baaw_p_apm_chub_start;
	unsigned int baaw_p_apm_chub_end;
	unsigned int baaw_p_apm_chub_remap;
};

#define CHUB_IRQ_PIN_MAX (5)
struct contexthub_ipc_info {
	struct device *dev;
	struct nanohub_data *data;
	struct nanohub_platform_data *pdata;
	wait_queue_head_t wakeup_wait;
	struct work_struct debug_work;
	struct read_wait read_lock;
#ifdef USE_IPC_BUF
	u8 rxbuf[PACKET_SIZE_MAX];
#endif
	struct chub_alive chub_alive_lock;
	void __iomem *sram;
	void __iomem *mailbox;
	void __iomem *chub_dumpgrp;
	void __iomem *chub_baaw;
	void __iomem *pmu_chub_reset;
	void __iomem *pmu_chub_cpu;
	void __iomem *cmu_chub_qch;
	struct contexthub_baaw_info baaw_info;
	struct ipc_map_area *ipc_map;
	struct log_buffer_info *fw_log;
	struct log_buffer_info *dd_log;
	struct LOG_BUFFER *dd_log_buffer;
	unsigned long clkrate;
	atomic_t chub_status;
	atomic_t in_reset;
	atomic_t irq1_apInt;
	atomic_t wakeup_chub;
	atomic_t in_use_ipc;
	int irq_mailbox;
	int irq_wdt;
	bool irq_wdt_disabled;
	int err_cnt[CHUB_ERR_MAX];
	u32 cur_err;
	int utc_run;
	int powermode;
	int block_reset;
	bool os_load;
	char os_name[MAX_FILE_LEN];
	struct notifier_block itmon_nb;
	u32 irq_pin_len;
	u32 irq_pins[CHUB_IRQ_PIN_MAX];
#ifdef CONFIG_CONTEXTHUB_DEBUG
	struct work_struct utc_work;
#endif
};

/*	PMU CHUB_CPU registers */
#if defined(CONFIG_SOC_EXYNOS9810)
#define REG_CHUB_CPU_STATUS (0x0)
#elif defined(CONFIG_SOC_EXYNOS9610)
#define REG_CHUB_CPU_STATUS (0x4)
#else
/* TODO: Need to check */
#define REG_CHUB_CPU_STATUS (0x0)
#endif
#define REG_CHUB_CPU_STATUS_BIT_STANDBYWFI (28)
#if defined(CONFIG_SOC_EXYNOS9810)
#define REG_CHUB_CPU_OPTION (0x4)
#define ENABLE_SYSRESETREQ BIT(4)
#elif defined(CONFIG_SOC_EXYNOS9610)
#define REG_CHUB_CPU_OPTION (0x8)
#define ENABLE_SYSRESETREQ BIT(9)
#else
/* TODO: Need to check */
#define REG_CHUB_CPU_OPTION (0x0)
#define ENABLE_SYSRESETREQ BIT(0)
#endif
#define REG_CHUB_CPU_DURATION (0x8)

/*	PMU CHUB_RESET registers */
#define REG_CHUB_RESET_CHUB_CONFIGURATION (0x0)
#define REG_CHUB_RESET_CHUB_STATUS (0x4)
#define REG_CHUB_RESET_CHUB_OPTION (0x8)
#if defined(CONFIG_SOC_EXYNOS9810)
#define CHUB_RESET_RELEASE_VALUE (0x10000000)
#elif defined(CONFIG_SOC_EXYNOS9610)
#define CHUB_RESET_RELEASE_VALUE (0x8000)
#else
/* TODO: Need to check */
#define CHUB_RESET_RELEASE_VALUE (0x0)
#endif

/*	CMU CHUB_QCH registers	*/
#if defined(CONFIG_SOC_EXYNOS9610)
#define REG_QCH_CON_CM4_SHUB_QCH (0x8)
#define IGNORE_FORCE_PM_EN BIT(2)
#define CLOCK_REQ BIT(1)
#define ENABLE BIT(0)
#endif

/*	CHUB dump GRP Registers : CHUB BASE + 0x1f000000 */
#define REG_CHUB_DUMPGPR_CTRL (0x0)
#define REG_CHUB_DUMPGPR_PCR  (0x4)
#define REG_CHUB_DUMPGPR_GP0R (0x10)
#define REG_CHUB_DUMPGPR_GP1R (0x14)
#define REG_CHUB_DUMPGPR_GP2R (0x18)
#define REG_CHUB_DUMPGPR_GP3R (0x1c)
#define REG_CHUB_DUMPGPR_GP4R (0x20)
#define REG_CHUB_DUMPGPR_GP5R (0x24)
#define REG_CHUB_DUMPGPR_GP6R (0x28)
#define REG_CHUB_DUMPGPR_GP7R (0x2c)
#define REG_CHUB_DUMPGPR_GP8R (0x30)
#define REG_CHUB_DUMPGPR_GP9R (0x34)
#define REG_CHUB_DUMPGPR_GPAR (0x38)
#define REG_CHUB_DUMPGPR_GPBR (0x3c)
#define REG_CHUB_DUMPGPR_GPCR (0x40)
#define REG_CHUB_DUMPGPR_GPDR (0x44)
#define REG_CHUB_DUMPGPR_GPER (0x48)
#define REG_CHUB_DUMPGPR_GPFR (0x4c)

#define IPC_HW_WRITE_DUMPGPR_CTRL(base, val) \
	__raw_writel((val), (base) + REG_CHUB_DUMPGPR_CTRL)
#define IPC_HW_READ_DUMPGPR_PCR(base) \
	__raw_readl((base) + REG_CHUB_DUMPGPR_PCR)

/*	CHUB BAAW Registers : CHUB BASE + 0x100000 */
#define REG_BAAW_D_CHUB0 (0x0)
#define REG_BAAW_D_CHUB1 (0x4)
#define REG_BAAW_D_CHUB2 (0x8)
#define REG_BAAW_D_CHUB3 (0xc)
#define BAAW_VAL_MAX (4)
#define BAAW_RW_ACCESS_ENABLE 0x80000003

#define IPC_MAX_TIMEOUT (0xffffff)
#define INIT_CHUB_VAL (-1)

#define IPC_HW_WRITE_BAAW_CHUB0(base, val) \
	__raw_writel((val), (base) + REG_BAAW_D_CHUB0)
#define IPC_HW_WRITE_BAAW_CHUB1(base, val) \
	__raw_writel((val), (base) + REG_BAAW_D_CHUB1)
#define IPC_HW_WRITE_BAAW_CHUB2(base, val) \
	__raw_writel((val), (base) + REG_BAAW_D_CHUB2)
#define IPC_HW_WRITE_BAAW_CHUB3(base, val) \
	__raw_writel((val), (base) + REG_BAAW_D_CHUB3)

int contexthub_ipc_write_event(struct contexthub_ipc_info *data,
				enum mailbox_event event);
int contexthub_ipc_read(struct contexthub_ipc_info *ipc,
				uint8_t *rx, int max_length, int timeout);
int contexthub_ipc_write(struct contexthub_ipc_info *ipc,
				uint8_t *tx, int length, int timeout);
int contexthub_poweron(struct contexthub_ipc_info *data);
int contexthub_download_image(struct contexthub_ipc_info *data, enum ipc_region reg);
int contexthub_reset(struct contexthub_ipc_info *ipc, bool force_load, int dump_id);
int contexthub_wakeup(struct contexthub_ipc_info *data, int evt);
int contexthub_request(struct contexthub_ipc_info *ipc);
void contexthub_release(struct contexthub_ipc_info *ipc);
#endif
Commit	Line	Data
0f0cca68 BK	1	/*
	2	* Copyright (c) 2017 Samsung Electronics Co., Ltd.
	3	*
	4	* Boojin Kim <boojin.kim@samsung.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#ifndef __CONTEXTHUB_IPC_H_
	13	#define __CONTEXTHUB_IPC_H_
	14
	15	#include <linux/io.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/workqueue.h>
	21	#include <linux/wakelock.h>
	22	#include <linux/list.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/semaphore.h>
	25	#include <linux/platform_data/nanohub.h>
	26	#include <linux/sched/clock.h>
	27	#include <linux/sched/signal.h>
	28	#include "chub_ipc.h"
	29	#include "chub_log.h"
	30
8d1941e1	31	#define WAIT_TRY_CNT (3)
d6f70cea	32	#define RESET_WAIT_TRY_CNT (10)
8d1941e1 BK	33	#define WAIT_CHUB_MS (100)
8d1941e1 BK	34
0f0cca68 BK	35	/* utils for nanohub main */
	36	#define wait_event_interruptible_timeout_locked(q, cond, tmo) \
	37	({ \
	38	long __ret = (tmo); \
	39	DEFINE_WAIT(__wait); \
	40	if (!(cond)) { \
	41	for (;;) { \
	42	__wait.flags &= ~WQ_FLAG_EXCLUSIVE; \
	43	if (list_empty(&__wait.entry)) \
	44	__add_wait_queue_entry_tail(&(q), &__wait); \
	45	set_current_state(TASK_INTERRUPTIBLE); \
	46	if ((cond)) \
	47	break; \
	48	if (signal_pending(current)) { \
	49	__ret = -ERESTARTSYS; \
	50	break; \
	51	} \
	52	spin_unlock_irq(&(q).lock); \
	53	__ret = schedule_timeout(__ret); \
	54	spin_lock_irq(&(q).lock); \
	55	if (!__ret) { \
	56	if ((cond)) \
	57	__ret = 1; \
	58	break; \
	59	} \
	60	} \
	61	__set_current_state(TASK_RUNNING); \
	62	if (!list_empty(&__wait.entry)) \
	63	list_del_init(&__wait.entry); \
	64	else if (__ret == -ERESTARTSYS && \
	65	/reimplementation of wait_abort_exclusive() /\
	66	waitqueue_active(&(q))) \
	67	__wake_up_locked_key(&(q), TASK_INTERRUPTIBLE, \
	68	NULL); \
	69	} else { \
	70	__ret = 1; \
	71	} \
	72	__ret; \
	73	})
	74
c7deff4d	75	#define CHUB_RESET_ENABLE
0f0cca68 BK	76	enum mailbox_event {
	77	MAILBOX_EVT_UTC_MAX = IPC_DEBUG_UTC_MAX,
	78	MAILBOX_EVT_DUMP_STATUS = IPC_DEBUG_DUMP_STATUS,
0f0cca68 BK	79	MAILBOX_EVT_WAKEUP,
	80	MAILBOX_EVT_WAKEUP_CLR,
	81	MAILBOX_EVT_ERASE_SHARED,
	82	MAILBOX_EVT_ENABLE_IRQ,
	83	MAILBOX_EVT_DISABLE_IRQ,
c7deff4d	84	MAILBOX_EVT_RESET_EVT_START,
0f0cca68	85	MAILBOX_EVT_INIT_IPC,
c7deff4d	86	MAILBOX_EVT_POWER_ON,
0f0cca68	87	MAILBOX_EVT_CHUB_ALIVE,
7370c09f SR	88	MAILBOX_EVT_SHUTDOWN,
7370c09f SR	89	MAILBOX_EVT_RESET,
0f0cca68 BK	90	MAILBOX_EVT_MAX,
	91	};
	92
	93	enum chub_status {
	94	CHUB_ST_NO_POWER,
	95	CHUB_ST_POWER_ON,
	96	CHUB_ST_RUN,
	97	CHUB_ST_SHUTDOWN,
	98	CHUB_ST_NO_RESPONSE,
c7deff4d	99	CHUB_ST_ERR,
6fc7b4c8	100	CHUB_ST_HANG,
0f0cca68 BK	101	};
	102
	103	struct read_wait {
	104	atomic_t cnt;
	105	volatile u32 flag;
	106	wait_queue_head_t event;
	107	};
	108
	109	struct recv_ctrl {
	110	unsigned long order;
	111	volatile unsigned long container[IRQ_EVT_CH_MAX];
	112	};
	113
	114	struct chub_alive {
	115	unsigned int flag;
	116	wait_queue_head_t event;
	117	};
	118
cdf64768	119	#ifdef USE_EXYNOS_LOG
01b22ab4	120	#define CHUB_DBG_DIR "/data/exynos/log/chub"
cdf64768 BK	121	#else
	122	#define CHUB_DBG_DIR "/data"
	123	#endif
01b22ab4	124
9b4a410f	125	enum chub_err_type {
821540c1	126	CHUB_ERR_NONE,
0f0cca68 BK	127	CHUB_ERR_EVTQ_EMTPY, /* ap error */
	128	CHUB_ERR_READ_FAIL,
	129	CHUB_ERR_WRITE_FAIL,
	130	CHUB_ERR_EVTQ_NO_HW_TRIGGER,
c7deff4d	131	CHUB_ERR_CHUB_NO_RESPONSE, /* 5 */
9b4a410f	132	CHUB_ERR_ITMON,
c7deff4d BK	133	CHUB_ERR_FW_FAULT, /* chub error */
	134	CHUB_ERR_FW_WDT, /* 8 */
	135	CHUB_ERR_NEED_RESET,
	136	CHUB_ERR_FW_ERROR = CHUB_ERR_NEED_RESET,
	137	CHUB_ERR_COMMS_NACK, /* ap comms error */
9b4a410f BK	138	CHUB_ERR_COMMS_BUSY,
	139	CHUB_ERR_COMMS_UNKNOWN,
	140	CHUB_ERR_COMMS,
c7deff4d BK	141	CHUB_ERR_RESET_CNT,
c7deff4d BK	142	CHUB_ERR_NANOHUB, /* nanohub dbg error */
0f0cca68 BK	143	CHUB_ERR_MAX,
	144	};
	145
	146	struct contexthub_baaw_info {
	147	unsigned int baaw_p_apm_chub_start;
	148	unsigned int baaw_p_apm_chub_end;
	149	unsigned int baaw_p_apm_chub_remap;
	150	};
	151
cdf64768	152	#define CHUB_IRQ_PIN_MAX (5)
0f0cca68 BK	153	struct contexthub_ipc_info {
	154	struct device *dev;
	155	struct nanohub_data *data;
	156	struct nanohub_platform_data *pdata;
	157	wait_queue_head_t wakeup_wait;
	158	struct work_struct debug_work;
	159	struct read_wait read_lock;
	160	#ifdef USE_IPC_BUF
	161	u8 rxbuf[PACKET_SIZE_MAX];
0f0cca68 BK	162	#endif
	163	struct chub_alive chub_alive_lock;
	164	void __iomem *sram;
	165	void __iomem *mailbox;
	166	void __iomem *chub_dumpgrp;
	167	void __iomem *chub_baaw;
	168	void __iomem *pmu_chub_reset;
	169	void __iomem *pmu_chub_cpu;
	170	void __iomem *cmu_chub_qch;
	171	struct contexthub_baaw_info baaw_info;
	172	struct ipc_map_area *ipc_map;
	173	struct log_buffer_info *fw_log;
	174	struct log_buffer_info *dd_log;
	175	struct LOG_BUFFER *dd_log_buffer;
	176	unsigned long clkrate;
0f0cca68	177	atomic_t chub_status;
9b4a410f	178	atomic_t in_reset;
0f0cca68 BK	179	atomic_t irq1_apInt;
0f0cca68 BK	180	atomic_t wakeup_chub;
d6f70cea	181	atomic_t in_use_ipc;
821540c1 BK	182	int irq_mailbox;
821540c1 BK	183	int irq_wdt;
b8e15746	184	bool irq_wdt_disabled;
0f0cca68	185	int err_cnt[CHUB_ERR_MAX];
c7deff4d	186	u32 cur_err;
0f0cca68 BK	187	int utc_run;
0f0cca68 BK	188	int powermode;
7370c09f	189	int block_reset;
0f0cca68 BK	190	bool os_load;
0f0cca68 BK	191	char os_name[MAX_FILE_LEN];
9b4a410f	192	struct notifier_block itmon_nb;
cdf64768 BK	193	u32 irq_pin_len;
cdf64768 BK	194	u32 irq_pins[CHUB_IRQ_PIN_MAX];
0f0cca68 BK	195	#ifdef CONFIG_CONTEXTHUB_DEBUG
	196	struct work_struct utc_work;
	197	#endif
	198	};
	199
	200	/* PMU CHUB_CPU registers */
	201	#if defined(CONFIG_SOC_EXYNOS9810)
	202	#define REG_CHUB_CPU_STATUS (0x0)
	203	#elif defined(CONFIG_SOC_EXYNOS9610)
	204	#define REG_CHUB_CPU_STATUS (0x4)
	205	#else
	206	/* TODO: Need to check */
	207	#define REG_CHUB_CPU_STATUS (0x0)
	208	#endif
	209	#define REG_CHUB_CPU_STATUS_BIT_STANDBYWFI (28)
	210	#if defined(CONFIG_SOC_EXYNOS9810)
	211	#define REG_CHUB_CPU_OPTION (0x4)
	212	#define ENABLE_SYSRESETREQ BIT(4)
	213	#elif defined(CONFIG_SOC_EXYNOS9610)
	214	#define REG_CHUB_CPU_OPTION (0x8)
	215	#define ENABLE_SYSRESETREQ BIT(9)
	216	#else
	217	/* TODO: Need to check */
	218	#define REG_CHUB_CPU_OPTION (0x0)
	219	#define ENABLE_SYSRESETREQ BIT(0)
	220	#endif
	221	#define REG_CHUB_CPU_DURATION (0x8)
	222
	223	/* PMU CHUB_RESET registers */
	224	#define REG_CHUB_RESET_CHUB_CONFIGURATION (0x0)
	225	#define REG_CHUB_RESET_CHUB_STATUS (0x4)
	226	#define REG_CHUB_RESET_CHUB_OPTION (0x8)
	227	#if defined(CONFIG_SOC_EXYNOS9810)
	228	#define CHUB_RESET_RELEASE_VALUE (0x10000000)
	229	#elif defined(CONFIG_SOC_EXYNOS9610)
	230	#define CHUB_RESET_RELEASE_VALUE (0x8000)
	231	#else
	232	/* TODO: Need to check */
	233	#define CHUB_RESET_RELEASE_VALUE (0x0)
	234	#endif
	235
	236	/* CMU CHUB_QCH registers */
	237	#if defined(CONFIG_SOC_EXYNOS9610)
	238	#define REG_QCH_CON_CM4_SHUB_QCH (0x8)
	239	#define IGNORE_FORCE_PM_EN BIT(2)
	240	#define CLOCK_REQ BIT(1)
	241	#define ENABLE BIT(0)
	242	#endif
	243
	244	/* CHUB dump GRP Registers : CHUB BASE + 0x1f000000 */
	245	#define REG_CHUB_DUMPGPR_CTRL (0x0)
	246	#define REG_CHUB_DUMPGPR_PCR (0x4)
	247	#define REG_CHUB_DUMPGPR_GP0R (0x10)
	248	#define REG_CHUB_DUMPGPR_GP1R (0x14)
	249	#define REG_CHUB_DUMPGPR_GP2R (0x18)
	250	#define REG_CHUB_DUMPGPR_GP3R (0x1c)
	251	#define REG_CHUB_DUMPGPR_GP4R (0x20)
	252	#define REG_CHUB_DUMPGPR_GP5R (0x24)
	253	#define REG_CHUB_DUMPGPR_GP6R (0x28)
	254	#define REG_CHUB_DUMPGPR_GP7R (0x2c)
	255	#define REG_CHUB_DUMPGPR_GP8R (0x30)
	256	#define REG_CHUB_DUMPGPR_GP9R (0x34)
	257	#define REG_CHUB_DUMPGPR_GPAR (0x38)
	258	#define REG_CHUB_DUMPGPR_GPBR (0x3c)
259	#define REG_CHUB_DUMPGPR_GPCR (0x40)
260	#define REG_CHUB_DUMPGPR_GPDR (0x44)
261	#define REG_CHUB_DUMPGPR_GPER (0x48)
262	#define REG_CHUB_DUMPGPR_GPFR (0x4c)
263
264	#define IPC_HW_WRITE_DUMPGPR_CTRL(base, val) \
265	__raw_writel((val), (base) + REG_CHUB_DUMPGPR_CTRL)
266	#define IPC_HW_READ_DUMPGPR_PCR(base) \
267	__raw_readl((base) + REG_CHUB_DUMPGPR_PCR)
268
269	/* CHUB BAAW Registers : CHUB BASE + 0x100000 */
270	#define REG_BAAW_D_CHUB0 (0x0)
271	#define REG_BAAW_D_CHUB1 (0x4)
272	#define REG_BAAW_D_CHUB2 (0x8)
273	#define REG_BAAW_D_CHUB3 (0xc)
274	#define BAAW_VAL_MAX (4)
275	#define BAAW_RW_ACCESS_ENABLE 0x80000003
276
277	#define IPC_MAX_TIMEOUT (0xffffff)
278	#define INIT_CHUB_VAL (-1)
279
280	#define IPC_HW_WRITE_BAAW_CHUB0(base, val) \
281	__raw_writel((val), (base) + REG_BAAW_D_CHUB0)
282	#define IPC_HW_WRITE_BAAW_CHUB1(base, val) \
283	__raw_writel((val), (base) + REG_BAAW_D_CHUB1)
284	#define IPC_HW_WRITE_BAAW_CHUB2(base, val) \
285	__raw_writel((val), (base) + REG_BAAW_D_CHUB2)
286	#define IPC_HW_WRITE_BAAW_CHUB3(base, val) \
287	__raw_writel((val), (base) + REG_BAAW_D_CHUB3)
288
289	int contexthub_ipc_write_event(struct contexthub_ipc_info *data,
290	enum mailbox_event event);
291	int contexthub_ipc_read(struct contexthub_ipc_info *ipc,
292	uint8_t *rx, int max_length, int timeout);
293	int contexthub_ipc_write(struct contexthub_ipc_info *ipc,
294	uint8_t *tx, int length, int timeout);
0f0cca68	295	int contexthub_poweron(struct contexthub_ipc_info *data);
c7deff4d	296	int contexthub_download_image(struct contexthub_ipc_info *data, enum ipc_region reg);
d6f70cea	297	int contexthub_reset(struct contexthub_ipc_info *ipc, bool force_load, int dump_id);
0f0cca68	298	int contexthub_wakeup(struct contexthub_ipc_info *data, int evt);
d6f70cea BK	299	int contexthub_request(struct contexthub_ipc_info *ipc);
d6f70cea BK	300	void contexthub_release(struct contexthub_ipc_info *ipc);
0f0cca68	301	#endif