[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / iio / adc / mxs-lradc.c

/*
 * Freescale i.MX28 LRADC driver
 *
 * Copyright (c) 2012 DENX Software Engineering, GmbH.
 * Marek Vasut <marex@denx.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/stmp_device.h>
#include <linux/bitops.h>
#include <linux/completion.h>

#include <mach/mxs.h>
#include <mach/common.h>

#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#define DRIVER_NAME		"mxs-lradc"

#define LRADC_MAX_DELAY_CHANS	4
#define LRADC_MAX_MAPPED_CHANS	8
#define LRADC_MAX_TOTAL_CHANS	16

#define LRADC_DELAY_TIMER_HZ	2000

/*
 * Make this runtime configurable if necessary. Currently, if the buffered mode
 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
 * seconds. The result is that the samples arrive every 500mS.
 */
#define LRADC_DELAY_TIMER_PER	200
#define LRADC_DELAY_TIMER_LOOP	5

static const char * const mxs_lradc_irq_name[] = {
	"mxs-lradc-touchscreen",
	"mxs-lradc-thresh0",
	"mxs-lradc-thresh1",
	"mxs-lradc-channel0",
	"mxs-lradc-channel1",
	"mxs-lradc-channel2",
	"mxs-lradc-channel3",
	"mxs-lradc-channel4",
	"mxs-lradc-channel5",
	"mxs-lradc-channel6",
	"mxs-lradc-channel7",
	"mxs-lradc-button0",
	"mxs-lradc-button1",
};

struct mxs_lradc_chan {
	uint8_t				slot;
	uint8_t				flags;
};

struct mxs_lradc {
	struct device		*dev;
	void __iomem		*base;
	int			irq[13];

	uint32_t		*buffer;
	struct iio_trigger	*trig;

	struct mutex		lock;

	uint8_t			enable;

	struct completion	completion;
};

#define	LRADC_CTRL0				0x00
#define LRADC_CTRL0_TOUCH_DETECT_ENABLE		(1 << 23)
#define LRADC_CTRL0_TOUCH_SCREEN_TYPE		(1 << 22)

#define	LRADC_CTRL1				0x10
#define	LRADC_CTRL1_LRADC_IRQ(n)		(1 << (n))
#define	LRADC_CTRL1_LRADC_IRQ_MASK		0x1fff
#define	LRADC_CTRL1_LRADC_IRQ_EN(n)		(1 << ((n) + 16))
#define	LRADC_CTRL1_LRADC_IRQ_EN_MASK		(0x1fff << 16)

#define	LRADC_CTRL2				0x20
#define	LRADC_CTRL2_TEMPSENSE_PWD		(1 << 15)

#define	LRADC_CH(n)				(0x50 + (0x10 * (n)))
#define	LRADC_CH_ACCUMULATE			(1 << 29)
#define	LRADC_CH_NUM_SAMPLES_MASK		(0x1f << 24)
#define	LRADC_CH_NUM_SAMPLES_OFFSET		24
#define	LRADC_CH_VALUE_MASK			0x3ffff
#define	LRADC_CH_VALUE_OFFSET			0

#define	LRADC_DELAY(n)				(0xd0 + (0x10 * (n)))
#define	LRADC_DELAY_TRIGGER_LRADCS_MASK		(0xff << 24)
#define	LRADC_DELAY_TRIGGER_LRADCS_OFFSET	24
#define	LRADC_DELAY_KICK			(1 << 20)
#define	LRADC_DELAY_TRIGGER_DELAYS_MASK		(0xf << 16)
#define	LRADC_DELAY_TRIGGER_DELAYS_OFFSET	16
#define	LRADC_DELAY_LOOP_COUNT_MASK		(0x1f << 11)
#define	LRADC_DELAY_LOOP_COUNT_OFFSET		11
#define	LRADC_DELAY_DELAY_MASK			0x7ff
#define	LRADC_DELAY_DELAY_OFFSET		0

#define	LRADC_CTRL4				0x140
#define	LRADC_CTRL4_LRADCSELECT_MASK(n)		(0xf << ((n) * 4))
#define	LRADC_CTRL4_LRADCSELECT_OFFSET(n)	((n) * 4)

/*
 * Raw I/O operations
 */
static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
			const struct iio_chan_spec *chan,
			int *val, int *val2, long m)
{
	struct mxs_lradc *lradc = iio_priv(iio_dev);
	int ret;

	if (m != IIO_CHAN_INFO_RAW)
		return -EINVAL;

	/* Check for invalid channel */
	if (chan->channel > LRADC_MAX_TOTAL_CHANS)
		return -EINVAL;

	/*
	 * See if there is no buffered operation in progess. If there is, simply
	 * bail out. This can be improved to support both buffered and raw IO at
	 * the same time, yet the code becomes horribly complicated. Therefore I
	 * applied KISS principle here.
	 */
	ret = mutex_trylock(&lradc->lock);
	if (!ret)
		return -EBUSY;

	INIT_COMPLETION(lradc->completion);

	/*
	 * No buffered operation in progress, map the channel and trigger it.
	 * Virtual channel 0 is always used here as the others are always not
	 * used if doing raw sampling.
	 */
	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);

	writel(chan->channel, lradc->base + LRADC_CTRL4);
	writel(0, lradc->base + LRADC_CH(0));

	/* Enable the IRQ and start sampling the channel. */
	writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
	writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);

	/* Wait for completion on the channel, 1 second max. */
	ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
	if (!ret)
		ret = -ETIMEDOUT;
	if (ret < 0)
		goto err;

	/* Read the data. */
	*val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
	ret = IIO_VAL_INT;

err:
	writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);

	mutex_unlock(&lradc->lock);

	return ret;
}

static const struct iio_info mxs_lradc_iio_info = {
	.driver_module		= THIS_MODULE,
	.read_raw		= mxs_lradc_read_raw,
};

/*
 * IRQ Handling
 */
static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
{
	struct iio_dev *iio = data;
	struct mxs_lradc *lradc = iio_priv(iio);
	unsigned long reg = readl(lradc->base + LRADC_CTRL1);

	if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK))
		return IRQ_NONE;

	/*
	 * Touchscreen IRQ handling code shall probably have priority
	 * and therefore shall be placed here.
	 */

	if (iio_buffer_enabled(iio))
		iio_trigger_poll(iio->trig, iio_get_time_ns());
	else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
		complete(&lradc->completion);

	writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK,
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);

	return IRQ_HANDLED;
}

/*
 * Trigger handling
 */
static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *iio = pf->indio_dev;
	struct mxs_lradc *lradc = iio_priv(iio);
	const uint32_t chan_value = LRADC_CH_ACCUMULATE |
		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
	unsigned int i, j = 0;

	for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
		lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
		writel(chan_value, lradc->base + LRADC_CH(j));
		lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
		lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
		j++;
	}

	if (iio->scan_timestamp) {
		s64 *timestamp = (s64 *)((u8 *)lradc->buffer +
					ALIGN(j, sizeof(s64)));
		*timestamp = pf->timestamp;
	}

	iio_push_to_buffers(iio, (u8 *)lradc->buffer);

	iio_trigger_notify_done(iio->trig);

	return IRQ_HANDLED;
}

static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
{
	struct iio_dev *iio = trig->private_data;
	struct mxs_lradc *lradc = iio_priv(iio);
	const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;

	writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);

	return 0;
}

static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
	.owner = THIS_MODULE,
	.set_trigger_state = &mxs_lradc_configure_trigger,
};

static int mxs_lradc_trigger_init(struct iio_dev *iio)
{
	int ret;
	struct iio_trigger *trig;

	trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
	if (trig == NULL)
		return -ENOMEM;

	trig->dev.parent = iio->dev.parent;
	trig->private_data = iio;
	trig->ops = &mxs_lradc_trigger_ops;

	ret = iio_trigger_register(trig);
	if (ret) {
		iio_trigger_free(trig);
		return ret;
	}

	iio->trig = trig;

	return 0;
}

static void mxs_lradc_trigger_remove(struct iio_dev *iio)
{
	iio_trigger_unregister(iio->trig);
	iio_trigger_free(iio->trig);
}

static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
{
	struct mxs_lradc *lradc = iio_priv(iio);
	struct iio_buffer *buffer = iio->buffer;
	int ret = 0, chan, ofs = 0, enable = 0;
	uint32_t ctrl4 = 0;
	uint32_t ctrl1_irq = 0;
	const uint32_t chan_value = LRADC_CH_ACCUMULATE |
		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
	const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);

	if (!len)
		return -EINVAL;

	/*
	 * Lock the driver so raw access can not be done during buffered
	 * operation. This simplifies the code a lot.
	 */
	ret = mutex_trylock(&lradc->lock);
	if (!ret)
		return -EBUSY;

	lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
	if (!lradc->buffer) {
		ret = -ENOMEM;
		goto err_mem;
	}

	ret = iio_sw_buffer_preenable(iio);
	if (ret < 0)
		goto err_buf;

	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);

	for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
		ctrl4 |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
		ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
		writel(chan_value, lradc->base + LRADC_CH(ofs));
		enable |= 1 << ofs;
		ofs++;
	}

	writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
		lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);

	writel(ctrl4, lradc->base + LRADC_CTRL4);
	writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);

	writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
		lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);

	return 0;

err_buf:
	kfree(lradc->buffer);
err_mem:
	mutex_unlock(&lradc->lock);
	return ret;
}

static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
{
	struct mxs_lradc *lradc = iio_priv(iio);

	writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
		lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);

	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);

	kfree(lradc->buffer);
	mutex_unlock(&lradc->lock);

	return 0;
}

static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
					const unsigned long *mask)
{
	const int mw = bitmap_weight(mask, iio->masklength);

	return mw <= LRADC_MAX_MAPPED_CHANS;
}

static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
	.preenable = &mxs_lradc_buffer_preenable,
	.postenable = &iio_triggered_buffer_postenable,
	.predisable = &iio_triggered_buffer_predisable,
	.postdisable = &mxs_lradc_buffer_postdisable,
	.validate_scan_mask = &mxs_lradc_validate_scan_mask,
};

/*
 * Driver initialization
 */

#define MXS_ADC_CHAN(idx, chan_type) {				\
	.type = (chan_type),					\
	.indexed = 1,						\
	.scan_index = (idx),					\
	.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT,		\
	.channel = (idx),					\
	.scan_type = {						\
		.sign = 'u',					\
		.realbits = 18,					\
		.storagebits = 32,				\
	},							\
}

static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
	MXS_ADC_CHAN(0, IIO_VOLTAGE),
	MXS_ADC_CHAN(1, IIO_VOLTAGE),
	MXS_ADC_CHAN(2, IIO_VOLTAGE),
	MXS_ADC_CHAN(3, IIO_VOLTAGE),
	MXS_ADC_CHAN(4, IIO_VOLTAGE),
	MXS_ADC_CHAN(5, IIO_VOLTAGE),
	MXS_ADC_CHAN(6, IIO_VOLTAGE),
	MXS_ADC_CHAN(7, IIO_VOLTAGE),	/* VBATT */
	MXS_ADC_CHAN(8, IIO_TEMP),	/* Temp sense 0 */
	MXS_ADC_CHAN(9, IIO_TEMP),	/* Temp sense 1 */
	MXS_ADC_CHAN(10, IIO_VOLTAGE),	/* VDDIO */
	MXS_ADC_CHAN(11, IIO_VOLTAGE),	/* VTH */
	MXS_ADC_CHAN(12, IIO_VOLTAGE),	/* VDDA */
	MXS_ADC_CHAN(13, IIO_VOLTAGE),	/* VDDD */
	MXS_ADC_CHAN(14, IIO_VOLTAGE),	/* VBG */
	MXS_ADC_CHAN(15, IIO_VOLTAGE),	/* VDD5V */
};

static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
{
	int i;
	const uint32_t cfg =
		(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);

	stmp_reset_block(lradc->base);

	for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
		writel(cfg | (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + i)),
			lradc->base + LRADC_DELAY(i));

	/* Start internal temperature sensing. */
	writel(0, lradc->base + LRADC_CTRL2);
}

static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
{
	int i;

	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);

	for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
		writel(0, lradc->base + LRADC_DELAY(i));
}

static int mxs_lradc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct mxs_lradc *lradc;
	struct iio_dev *iio;
	struct resource *iores;
	int ret = 0;
	int i;

	/* Allocate the IIO device. */
	iio = iio_device_alloc(sizeof(*lradc));
	if (!iio) {
		dev_err(dev, "Failed to allocate IIO device\n");
		return -ENOMEM;
	}

	lradc = iio_priv(iio);

	/* Grab the memory area */
	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	lradc->dev = &pdev->dev;
	lradc->base = devm_request_and_ioremap(dev, iores);
	if (!lradc->base) {
		ret = -EADDRNOTAVAIL;
		goto err_addr;
	}

	/* Grab all IRQ sources */
	for (i = 0; i < 13; i++) {
		lradc->irq[i] = platform_get_irq(pdev, i);
		if (lradc->irq[i] < 0) {
			ret = -EINVAL;
			goto err_addr;
		}

		ret = devm_request_irq(dev, lradc->irq[i],
					mxs_lradc_handle_irq, 0,
					mxs_lradc_irq_name[i], iio);
		if (ret)
			goto err_addr;
	}

	platform_set_drvdata(pdev, iio);

	init_completion(&lradc->completion);
	mutex_init(&lradc->lock);

	iio->name = pdev->name;
	iio->dev.parent = &pdev->dev;
	iio->info = &mxs_lradc_iio_info;
	iio->modes = INDIO_DIRECT_MODE;
	iio->channels = mxs_lradc_chan_spec;
	iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);

	ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
				&mxs_lradc_trigger_handler,
				&mxs_lradc_buffer_ops);
	if (ret)
		goto err_addr;

	ret = mxs_lradc_trigger_init(iio);
	if (ret)
		goto err_trig;

	/* Register IIO device. */
	ret = iio_device_register(iio);
	if (ret) {
		dev_err(dev, "Failed to register IIO device\n");
		goto err_dev;
	}

	/* Configure the hardware. */
	mxs_lradc_hw_init(lradc);

	return 0;

err_dev:
	mxs_lradc_trigger_remove(iio);
err_trig:
	iio_triggered_buffer_cleanup(iio);
err_addr:
	iio_device_free(iio);
	return ret;
}

static int mxs_lradc_remove(struct platform_device *pdev)
{
	struct iio_dev *iio = platform_get_drvdata(pdev);
	struct mxs_lradc *lradc = iio_priv(iio);

	mxs_lradc_hw_stop(lradc);

	iio_device_unregister(iio);
	iio_triggered_buffer_cleanup(iio);
	mxs_lradc_trigger_remove(iio);
	iio_device_free(iio);

	return 0;
}

static const struct of_device_id mxs_lradc_dt_ids[] = {
	{ .compatible = "fsl,imx28-lradc", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);

static struct platform_driver mxs_lradc_driver = {
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_lradc_dt_ids,
	},
	.probe	= mxs_lradc_probe,
	.remove	= mxs_lradc_remove,
};

module_platform_driver(mxs_lradc_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bc2c90c9 MV	1	/*
	2	* Freescale i.MX28 LRADC driver
	3	*
	4	* Copyright (c) 2012 DENX Software Engineering, GmbH.
	5	* Marek Vasut <marex@denx.de>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/interrupt.h>
	19	#include <linux/device.h>
	20	#include <linux/kernel.h>
	21	#include <linux/slab.h>
	22	#include <linux/of.h>
	23	#include <linux/of_device.h>
	24	#include <linux/sysfs.h>
	25	#include <linux/list.h>
	26	#include <linux/io.h>
	27	#include <linux/module.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/spinlock.h>
	30	#include <linux/wait.h>
	31	#include <linux/sched.h>
	32	#include <linux/stmp_device.h>
	33	#include <linux/bitops.h>
	34	#include <linux/completion.h>
	35
	36	#include <mach/mxs.h>
	37	#include <mach/common.h>
	38
	39	#include <linux/iio/iio.h>
	40	#include <linux/iio/buffer.h>
	41	#include <linux/iio/trigger.h>
	42	#include <linux/iio/trigger_consumer.h>
	43	#include <linux/iio/triggered_buffer.h>
	44
	45	#define DRIVER_NAME "mxs-lradc"
	46
	47	#define LRADC_MAX_DELAY_CHANS 4
	48	#define LRADC_MAX_MAPPED_CHANS 8
	49	#define LRADC_MAX_TOTAL_CHANS 16
	50
	51	#define LRADC_DELAY_TIMER_HZ 2000
	52
	53	/*
	54	* Make this runtime configurable if necessary. Currently, if the buffered mode
	55	* is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
	56	* triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
	57	* seconds. The result is that the samples arrive every 500mS.
	58	*/
	59	#define LRADC_DELAY_TIMER_PER 200
	60	#define LRADC_DELAY_TIMER_LOOP 5
	61
	62	static const char * const mxs_lradc_irq_name[] = {
	63	"mxs-lradc-touchscreen",
	64	"mxs-lradc-thresh0",
65	"mxs-lradc-thresh1",
66	"mxs-lradc-channel0",
67	"mxs-lradc-channel1",
68	"mxs-lradc-channel2",
69	"mxs-lradc-channel3",
70	"mxs-lradc-channel4",
71	"mxs-lradc-channel5",
72	"mxs-lradc-channel6",
73	"mxs-lradc-channel7",
74	"mxs-lradc-button0",
75	"mxs-lradc-button1",
76	};
77
78	struct mxs_lradc_chan {
79	uint8_t slot;
80	uint8_t flags;
81	};
82
83	struct mxs_lradc {
84	struct device *dev;
85	void __iomem *base;
86	int irq[13];
87
88	uint32_t *buffer;
89	struct iio_trigger *trig;
90
91	struct mutex lock;
92
93	uint8_t enable;
94
95	struct completion completion;
96	};
97
98	#define LRADC_CTRL0 0x00
99	#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
100	#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
101
102	#define LRADC_CTRL1 0x10
103	#define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
104	#define LRADC_CTRL1_LRADC_IRQ_MASK 0x1fff
105	#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
106	#define LRADC_CTRL1_LRADC_IRQ_EN_MASK (0x1fff << 16)
107
108	#define LRADC_CTRL2 0x20
109	#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
110
111	#define LRADC_CH(n) (0x50 + (0x10 * (n)))
112	#define LRADC_CH_ACCUMULATE (1 << 29)
113	#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
114	#define LRADC_CH_NUM_SAMPLES_OFFSET 24
115	#define LRADC_CH_VALUE_MASK 0x3ffff
116	#define LRADC_CH_VALUE_OFFSET 0
117
118	#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
119	#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
120	#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
121	#define LRADC_DELAY_KICK (1 << 20)
122	#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
123	#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
124	#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
125	#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
126	#define LRADC_DELAY_DELAY_MASK 0x7ff
127	#define LRADC_DELAY_DELAY_OFFSET 0
128
129	#define LRADC_CTRL4 0x140
130	#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
131	#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
132
133	/*
134	* Raw I/O operations
135	*/
136	static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
137	const struct iio_chan_spec *chan,
138	int val, int val2, long m)
139	{
140	struct mxs_lradc *lradc = iio_priv(iio_dev);
141	int ret;
142
143	if (m != IIO_CHAN_INFO_RAW)
144	return -EINVAL;
145
146	/* Check for invalid channel */
147	if (chan->channel > LRADC_MAX_TOTAL_CHANS)
148	return -EINVAL;
149
150	/*
151	* See if there is no buffered operation in progess. If there is, simply
152	* bail out. This can be improved to support both buffered and raw IO at
153	* the same time, yet the code becomes horribly complicated. Therefore I
154	* applied KISS principle here.
155	*/
156	ret = mutex_trylock(&lradc->lock);
157	if (!ret)
158	return -EBUSY;
159
160	INIT_COMPLETION(lradc->completion);
161
162	/*
163	* No buffered operation in progress, map the channel and trigger it.
164	* Virtual channel 0 is always used here as the others are always not
165	* used if doing raw sampling.
166	*/
167	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
168	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
169	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
170
171	writel(chan->channel, lradc->base + LRADC_CTRL4);
172	writel(0, lradc->base + LRADC_CH(0));
173
174	/* Enable the IRQ and start sampling the channel. */
175	writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
176	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
177	writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
178
179	/* Wait for completion on the channel, 1 second max. */
180	ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
181	if (!ret)
182	ret = -ETIMEDOUT;
183	if (ret < 0)
184	goto err;
185
186	/* Read the data. */
187	*val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
188	ret = IIO_VAL_INT;
189
190	err:
191	writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
192	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
193
194	mutex_unlock(&lradc->lock);
195
196	return ret;
197	}
198
199	static const struct iio_info mxs_lradc_iio_info = {
200	.driver_module = THIS_MODULE,
201	.read_raw = mxs_lradc_read_raw,
202	};
203
204	/*
205	* IRQ Handling
206	*/
207	static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
208	{
209	struct iio_dev *iio = data;
210	struct mxs_lradc *lradc = iio_priv(iio);
211	unsigned long reg = readl(lradc->base + LRADC_CTRL1);
212
213	if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK))
214	return IRQ_NONE;
215
216	/*
217	* Touchscreen IRQ handling code shall probably have priority
218	* and therefore shall be placed here.
219	*/
220
221	if (iio_buffer_enabled(iio))
222	iio_trigger_poll(iio->trig, iio_get_time_ns());
223	else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
224	complete(&lradc->completion);
225
226	writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK,
227	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
228
229	return IRQ_HANDLED;
230	}
231
232	/*
233	* Trigger handling
234	*/
235	static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
236	{
237	struct iio_poll_func *pf = p;
238	struct iio_dev *iio = pf->indio_dev;
239	struct mxs_lradc *lradc = iio_priv(iio);
bc2c90c9 MV	240	const uint32_t chan_value = LRADC_CH_ACCUMULATE \|
bc2c90c9 MV	241	((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
7b7a4efe	242	unsigned int i, j = 0;
bc2c90c9 MV	243
	244	for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
	245	lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
	246	writel(chan_value, lradc->base + LRADC_CH(j));
	247	lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
	248	lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
	249	j++;
	250	}
	251
	252	if (iio->scan_timestamp) {
	253	s64 timestamp = (s64 )((u8 *)lradc->buffer +
	254	ALIGN(j, sizeof(s64)));
	255	*timestamp = pf->timestamp;
	256	}
	257
84b36ce5	258	iio_push_to_buffers(iio, (u8 *)lradc->buffer);
bc2c90c9 MV	259
	260	iio_trigger_notify_done(iio->trig);
	261
	262	return IRQ_HANDLED;
	263	}
	264
	265	static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
	266	{
	267	struct iio_dev *iio = trig->private_data;
	268	struct mxs_lradc *lradc = iio_priv(iio);
	269	const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
	270
	271	writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);
	272
	273	return 0;
	274	}
	275
	276	static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
	277	.owner = THIS_MODULE,
	278	.set_trigger_state = &mxs_lradc_configure_trigger,
	279	};
	280
	281	static int mxs_lradc_trigger_init(struct iio_dev *iio)
	282	{
	283	int ret;
	284	struct iio_trigger *trig;
	285
	286	trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
	287	if (trig == NULL)
	288	return -ENOMEM;
	289
	290	trig->dev.parent = iio->dev.parent;
	291	trig->private_data = iio;
	292	trig->ops = &mxs_lradc_trigger_ops;
	293
	294	ret = iio_trigger_register(trig);
	295	if (ret) {
	296	iio_trigger_free(trig);
	297	return ret;
	298	}
	299
	300	iio->trig = trig;
	301
	302	return 0;
	303	}
	304
	305	static void mxs_lradc_trigger_remove(struct iio_dev *iio)
	306	{
	307	iio_trigger_unregister(iio->trig);
	308	iio_trigger_free(iio->trig);
	309	}
	310
	311	static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
	312	{
	313	struct mxs_lradc *lradc = iio_priv(iio);
	314	struct iio_buffer *buffer = iio->buffer;
	315	int ret = 0, chan, ofs = 0, enable = 0;
	316	uint32_t ctrl4 = 0;
	317	uint32_t ctrl1_irq = 0;
	318	const uint32_t chan_value = LRADC_CH_ACCUMULATE \|
	319	((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
	320	const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
	321
	322	if (!len)
323	return -EINVAL;
324
325	/*
326	* Lock the driver so raw access can not be done during buffered
327	* operation. This simplifies the code a lot.
328	*/
329	ret = mutex_trylock(&lradc->lock);
330	if (!ret)
331	return -EBUSY;
332
333	lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
334	if (!lradc->buffer) {
335	ret = -ENOMEM;
336	goto err_mem;
337	}
338
339	ret = iio_sw_buffer_preenable(iio);
340	if (ret < 0)
341	goto err_buf;
342
343	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
344	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
345	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
346
347	for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
348	ctrl4 \|= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
349	ctrl1_irq \|= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
350	writel(chan_value, lradc->base + LRADC_CH(ofs));
351	enable \|= 1 << ofs;
352	ofs++;
73327b4c	353	}
bc2c90c9 MV	354
	355	writel(LRADC_DELAY_TRIGGER_LRADCS_MASK \| LRADC_DELAY_KICK,
	356	lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
	357
	358	writel(ctrl4, lradc->base + LRADC_CTRL4);
	359	writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
	360
	361	writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
	362	lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
	363
	364	return 0;
	365
	366	err_buf:
	367	kfree(lradc->buffer);
	368	err_mem:
	369	mutex_unlock(&lradc->lock);
	370	return ret;
	371	}
	372
	373	static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
	374	{
	375	struct mxs_lradc *lradc = iio_priv(iio);
	376
	377	writel(LRADC_DELAY_TRIGGER_LRADCS_MASK \| LRADC_DELAY_KICK,
	378	lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
	379
	380	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
	381	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
	382	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
	383
	384	kfree(lradc->buffer);
	385	mutex_unlock(&lradc->lock);
	386
	387	return 0;
	388	}
	389
	390	static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
	391	const unsigned long *mask)
	392	{
	393	const int mw = bitmap_weight(mask, iio->masklength);
	394
	395	return mw <= LRADC_MAX_MAPPED_CHANS;
	396	}
	397
	398	static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
	399	.preenable = &mxs_lradc_buffer_preenable,
	400	.postenable = &iio_triggered_buffer_postenable,
	401	.predisable = &iio_triggered_buffer_predisable,
	402	.postdisable = &mxs_lradc_buffer_postdisable,
	403	.validate_scan_mask = &mxs_lradc_validate_scan_mask,
	404	};
	405
	406	/*
	407	* Driver initialization
	408	*/
	409
	410	#define MXS_ADC_CHAN(idx, chan_type) { \
	411	.type = (chan_type), \
	412	.indexed = 1, \
	413	.scan_index = (idx), \
	414	.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \
	415	.channel = (idx), \
	416	.scan_type = { \
	417	.sign = 'u', \
418	.realbits = 18, \
419	.storagebits = 32, \
420	}, \
421	}
422
423	static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
424	MXS_ADC_CHAN(0, IIO_VOLTAGE),
425	MXS_ADC_CHAN(1, IIO_VOLTAGE),
426	MXS_ADC_CHAN(2, IIO_VOLTAGE),
427	MXS_ADC_CHAN(3, IIO_VOLTAGE),
428	MXS_ADC_CHAN(4, IIO_VOLTAGE),
429	MXS_ADC_CHAN(5, IIO_VOLTAGE),
430	MXS_ADC_CHAN(6, IIO_VOLTAGE),
431	MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
432	MXS_ADC_CHAN(8, IIO_TEMP), /* Temp sense 0 */
433	MXS_ADC_CHAN(9, IIO_TEMP), /* Temp sense 1 */
434	MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
435	MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
436	MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
437	MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
438	MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
439	MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
440	};
441
442	static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
443	{
444	int i;
445	const uint32_t cfg =
446	(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
447
448	stmp_reset_block(lradc->base);
449
450	for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
451	writel(cfg \| (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + i)),
452	lradc->base + LRADC_DELAY(i));
453
454	/* Start internal temperature sensing. */
455	writel(0, lradc->base + LRADC_CTRL2);
456	}
457
458	static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
459	{
460	int i;
461
462	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
463	lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
464
465	for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
466	writel(0, lradc->base + LRADC_DELAY(i));
467	}
468
4ae1c61f	469	static int mxs_lradc_probe(struct platform_device *pdev)
bc2c90c9 MV	470	{
	471	struct device *dev = &pdev->dev;
	472	struct mxs_lradc *lradc;
	473	struct iio_dev *iio;
	474	struct resource *iores;
	475	int ret = 0;
	476	int i;
	477
	478	/* Allocate the IIO device. */
	479	iio = iio_device_alloc(sizeof(*lradc));
	480	if (!iio) {
	481	dev_err(dev, "Failed to allocate IIO device\n");
	482	return -ENOMEM;
	483	}
	484
	485	lradc = iio_priv(iio);
	486
	487	/* Grab the memory area */
	488	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	489	lradc->dev = &pdev->dev;
	490	lradc->base = devm_request_and_ioremap(dev, iores);
	491	if (!lradc->base) {
	492	ret = -EADDRNOTAVAIL;
	493	goto err_addr;
	494	}
	495
	496	/* Grab all IRQ sources */
	497	for (i = 0; i < 13; i++) {
	498	lradc->irq[i] = platform_get_irq(pdev, i);
	499	if (lradc->irq[i] < 0) {
	500	ret = -EINVAL;
	501	goto err_addr;
	502	}
	503
	504	ret = devm_request_irq(dev, lradc->irq[i],
	505	mxs_lradc_handle_irq, 0,
	506	mxs_lradc_irq_name[i], iio);
	507	if (ret)
	508	goto err_addr;
	509	}
	510
	511	platform_set_drvdata(pdev, iio);
	512
	513	init_completion(&lradc->completion);
	514	mutex_init(&lradc->lock);
	515
	516	iio->name = pdev->name;
	517	iio->dev.parent = &pdev->dev;
	518	iio->info = &mxs_lradc_iio_info;
	519	iio->modes = INDIO_DIRECT_MODE;
	520	iio->channels = mxs_lradc_chan_spec;
	521	iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
	522
	523	ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
	524	&mxs_lradc_trigger_handler,
	525	&mxs_lradc_buffer_ops);
	526	if (ret)
	527	goto err_addr;
	528
	529	ret = mxs_lradc_trigger_init(iio);
	530	if (ret)
	531	goto err_trig;
	532
	533	/* Register IIO device. */
534	ret = iio_device_register(iio);
535	if (ret) {
536	dev_err(dev, "Failed to register IIO device\n");
537	goto err_dev;
538	}
539
540	/* Configure the hardware. */
541	mxs_lradc_hw_init(lradc);
542
543	return 0;
544
545	err_dev:
546	mxs_lradc_trigger_remove(iio);
547	err_trig:
548	iio_triggered_buffer_cleanup(iio);
549	err_addr:
550	iio_device_free(iio);
551	return ret;
552	}
553
447d4f29	554	static int mxs_lradc_remove(struct platform_device *pdev)
bc2c90c9 MV	555	{
	556	struct iio_dev *iio = platform_get_drvdata(pdev);
	557	struct mxs_lradc *lradc = iio_priv(iio);
	558
	559	mxs_lradc_hw_stop(lradc);
	560
	561	iio_device_unregister(iio);
	562	iio_triggered_buffer_cleanup(iio);
	563	mxs_lradc_trigger_remove(iio);
	564	iio_device_free(iio);
	565
	566	return 0;
	567	}
	568
	569	static const struct of_device_id mxs_lradc_dt_ids[] = {
	570	{ .compatible = "fsl,imx28-lradc", },
	571	{ /* sentinel */ }
	572	};
	573	MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
	574
	575	static struct platform_driver mxs_lradc_driver = {
	576	.driver = {
	577	.name = DRIVER_NAME,
	578	.owner = THIS_MODULE,
	579	.of_match_table = mxs_lradc_dt_ids,
	580	},
	581	.probe = mxs_lradc_probe,
e543acf0	582	.remove = mxs_lradc_remove,
bc2c90c9 MV	583	};
	584
	585	module_platform_driver(mxs_lradc_driver);
	586
	587	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	588	MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
	589	MODULE_LICENSE("GPL v2");