Commit | Line | Data |
---|---|---|
aa337ef1 | 1 | /* |
ef97e4ef GKH |
2 | * Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, |
3 | * Jason Lapenta, Scott Smedley | |
4 | * | |
5 | * This file is part of the DT3155 Device Driver. | |
6 | * | |
7 | * The DT3155 Device Driver is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * The DT3155 Device Driver is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General | |
15 | * Public License for more details. | |
16 | */ | |
aa337ef1 | 17 | |
ef97e4ef GKH |
18 | /* |
19 | * This file provides some basic register io routines. It is modified from | |
20 | * demo code provided by Data Translations. | |
21 | */ | |
aa337ef1 | 22 | |
ef97e4ef | 23 | #include <linux/delay.h> |
aa337ef1 SS |
24 | #include "dt3155.h" |
25 | #include "dt3155_io.h" | |
26 | #include "dt3155_drv.h" | |
27 | ||
aa337ef1 SS |
28 | |
29 | /****** local copies of board's 32 bit registers ******/ | |
3a8954e8 HS |
30 | u32 even_dma_start_r; /* bit 0 should always be 0 */ |
31 | u32 odd_dma_start_r; /* .. */ | |
32 | u32 even_dma_stride_r; /* bits 0&1 should always be 0 */ | |
33 | u32 odd_dma_stride_r; /* .. */ | |
34 | u32 even_pixel_fmt_r; | |
35 | u32 odd_pixel_fmt_r; | |
aa337ef1 | 36 | |
ef97e4ef GKH |
37 | FIFO_TRIGGER_R fifo_trigger_r; |
38 | XFER_MODE_R xfer_mode_r; | |
39 | CSR1_R csr1_r; | |
40 | RETRY_WAIT_CNT_R retry_wait_cnt_r; | |
41 | INT_CSR_R int_csr_r; | |
aa337ef1 | 42 | |
3a8954e8 HS |
43 | u32 even_fld_mask_r; |
44 | u32 odd_fld_mask_r; | |
aa337ef1 | 45 | |
ef97e4ef GKH |
46 | MASK_LENGTH_R mask_length_r; |
47 | FIFO_FLAG_CNT_R fifo_flag_cnt_r; | |
48 | IIC_CLK_DUR_R iic_clk_dur_r; | |
49 | IIC_CSR1_R iic_csr1_r; | |
50 | IIC_CSR2_R iic_csr2_r; | |
51 | DMA_UPPER_LMT_R even_dma_upper_lmt_r; | |
52 | DMA_UPPER_LMT_R odd_dma_upper_lmt_r; | |
aa337ef1 SS |
53 | |
54 | ||
55 | ||
56 | /******** local copies of board's 8 bit I2C registers ******/ | |
ef97e4ef GKH |
57 | I2C_CSR2 i2c_csr2; |
58 | I2C_EVEN_CSR i2c_even_csr; | |
59 | I2C_ODD_CSR i2c_odd_csr; | |
60 | I2C_CONFIG i2c_config; | |
61 | u8 i2c_dt_id; | |
62 | u8 i2c_x_clip_start; | |
63 | u8 i2c_y_clip_start; | |
64 | u8 i2c_x_clip_end; | |
65 | u8 i2c_y_clip_end; | |
66 | u8 i2c_ad_addr; | |
67 | u8 i2c_ad_lut; | |
68 | I2C_AD_CMD i2c_ad_cmd; | |
69 | u8 i2c_dig_out; | |
70 | u8 i2c_pm_lut_addr; | |
71 | u8 i2c_pm_lut_data; | |
aa337ef1 | 72 | |
ef97e4ef GKH |
73 | /* |
74 | * wait_ibsyclr() | |
75 | * | |
76 | * This function handles read/write timing and r/w timeout error | |
77 | * | |
78 | * Returns TRUE if NEW_CYCLE clears | |
79 | * Returns FALSE if NEW_CYCLE doesn't clear in roughly 3 msecs, otherwise | |
80 | * returns 0 | |
81 | */ | |
82 | static int wait_ibsyclr(u8 *lpReg) | |
aa337ef1 | 83 | { |
ef97e4ef GKH |
84 | /* wait 100 microseconds */ |
85 | udelay(100L); | |
86 | /* __delay(loops_per_sec/10000); */ | |
87 | if (iic_csr2_r.fld.NEW_CYCLE) { | |
88 | /* if NEW_CYCLE didn't clear */ | |
89 | /* TIMEOUT ERROR */ | |
90 | dt3155_errno = DT_ERR_I2C_TIMEOUT; | |
91 | return FALSE; | |
92 | } else | |
93 | return TRUE; /* no error */ | |
aa337ef1 SS |
94 | } |
95 | ||
ef97e4ef GKH |
96 | /* |
97 | * WriteI2C() | |
98 | * | |
99 | * This function handles writing to 8-bit DT3155 registers | |
100 | * | |
101 | * 1st parameter is pointer to 32-bit register base address | |
102 | * 2nd parameter is reg. index; | |
103 | * 3rd is value to be written | |
104 | * | |
105 | * Returns TRUE - Successful completion | |
106 | * FALSE - Timeout error - cycle did not complete! | |
107 | */ | |
108 | int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal) | |
aa337ef1 | 109 | { |
ef97e4ef | 110 | int writestat; /* status for return */ |
aa337ef1 | 111 | |
ef97e4ef | 112 | /* read 32 bit IIC_CSR2 register data into union */ |
aa337ef1 | 113 | |
ef97e4ef | 114 | ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); |
aa337ef1 | 115 | |
ef97e4ef GKH |
116 | /* for write operation */ |
117 | iic_csr2_r.fld.DIR_RD = 0; | |
118 | /* I2C address of I2C register: */ | |
119 | iic_csr2_r.fld.DIR_ADDR = wIregIndex; | |
120 | /* 8 bit data to be written to I2C reg */ | |
121 | iic_csr2_r.fld.DIR_WR_DATA = byVal; | |
122 | /* will start a direct I2C cycle: */ | |
123 | iic_csr2_r.fld.NEW_CYCLE = 1; | |
aa337ef1 | 124 | |
ef97e4ef GKH |
125 | /* xfer union data into 32 bit IIC_CSR2 register */ |
126 | WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); | |
aa337ef1 | 127 | |
ef97e4ef GKH |
128 | /* wait for IIC cycle to finish */ |
129 | writestat = wait_ibsyclr(lpReg); | |
130 | return writestat; | |
aa337ef1 SS |
131 | } |
132 | ||
ef97e4ef GKH |
133 | /* |
134 | * ReadI2C() | |
135 | * | |
136 | * This function handles reading from 8-bit DT3155 registers | |
137 | * | |
138 | * 1st parameter is pointer to 32-bit register base address | |
139 | * 2nd parameter is reg. index; | |
140 | * 3rd is adrs of value to be read | |
141 | * | |
142 | * Returns TRUE - Successful completion | |
143 | * FALSE - Timeout error - cycle did not complete! | |
144 | */ | |
145 | int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal) | |
aa337ef1 | 146 | { |
ef97e4ef | 147 | int writestat; /* status for return */ |
aa337ef1 | 148 | |
ef97e4ef GKH |
149 | /* read 32 bit IIC_CSR2 register data into union */ |
150 | ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); | |
aa337ef1 | 151 | |
ef97e4ef GKH |
152 | /* for read operation */ |
153 | iic_csr2_r.fld.DIR_RD = 1; | |
aa337ef1 | 154 | |
ef97e4ef GKH |
155 | /* I2C address of I2C register: */ |
156 | iic_csr2_r.fld.DIR_ADDR = wIregIndex; | |
aa337ef1 | 157 | |
ef97e4ef GKH |
158 | /* will start a direct I2C cycle: */ |
159 | iic_csr2_r.fld.NEW_CYCLE = 1; | |
aa337ef1 | 160 | |
ef97e4ef GKH |
161 | /* xfer union's data into 32 bit IIC_CSR2 register */ |
162 | WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); | |
aa337ef1 | 163 | |
ef97e4ef GKH |
164 | /* wait for IIC cycle to finish */ |
165 | writestat = wait_ibsyclr(lpReg); | |
aa337ef1 | 166 | |
ef97e4ef GKH |
167 | /* Next 2 commands read 32 bit IIC_CSR1 register's data into union */ |
168 | /* first read data is in IIC_CSR1 */ | |
169 | ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg); | |
aa337ef1 | 170 | |
ef97e4ef GKH |
171 | /* now get data u8 out of register */ |
172 | *byVal = (u8) iic_csr1_r.fld.RD_DATA; | |
aa337ef1 | 173 | |
ef97e4ef | 174 | return writestat; |
aa337ef1 | 175 | } |