projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
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1 | /* |
| 2 | * $Id: musycc.h,v 1.3 2005/09/28 00:10:08 rickd PMCC4_3_1B $ | |
| 3 | */ | |
| 4 | ||
| 5 | #ifndef _INC_MUSYCC_H_ | |
| 6 | #define _INC_MUSYCC_H_ | |
| 7 | ||
| 8 | /*----------------------------------------------------------------------------- | |
| 9 | * musycc.h - Multichannel Synchronous Communications Controller | |
| 10 | * CN8778/8474A/8472A/8471A | |
| 11 | * | |
| 12 | * Copyright (C) 2002-2005 SBE, Inc. | |
| 13 | * | |
| 14 | * This program is free software; you can redistribute it and/or modify | |
| 15 | * it under the terms of the GNU General Public License as published by | |
| 16 | * the Free Software Foundation; either version 2 of the License, or | |
| 17 | * (at your option) any later version. | |
| 18 | * | |
| 19 | * This program is distributed in the hope that it will be useful, | |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 22 | * GNU General Public License for more details. | |
| 23 | * | |
| 24 | * For further information, contact via email: support@sbei.com | |
| 25 | * SBE, Inc. San Ramon, California U.S.A. | |
| 26 | *----------------------------------------------------------------------------- | |
| 27 | * RCS info: | |
| 28 | * RCS revision: $Revision: 1.3 $ | |
| 29 | * Last changed on $Date: 2005/09/28 00:10:08 $ | |
| 30 | * Changed by $Author: rickd $ | |
| 31 | *----------------------------------------------------------------------------- | |
| 32 | * $Log: musycc.h,v $ | |
| 33 | * Revision 1.3 2005/09/28 00:10:08 rickd | |
| 34 | * Add GNU license info. Add PMCC4 PCI/DevIDs. Implement new | |
| 35 | * musycc reg&bits namings. Use PORTMAP_0 GCD grouping. | |
| 36 | * | |
| 37 | * Revision 1.2 2005/04/28 23:43:04 rickd | |
| 38 | * Add RCS tracking heading. | |
| 39 | * | |
| 40 | *----------------------------------------------------------------------------- | |
| 41 | */ | |
| 42 | ||
| 43 | #if defined (__FreeBSD__) || defined (__NetBSD__) | |
| 44 | #include <sys/types.h> | |
| 45 | #else | |
| 46 | #include <linux/types.h> | |
| 47 | #endif | |
| 48 | ||
| 49 | #define VINT8 volatile u_int8_t | |
| 50 | #define VINT32 volatile u_int32_t | |
| 51 | ||
| 52 | #ifdef __cplusplus | |
| 53 | extern "C" | |
| 54 | { | |
| 55 | #endif | |
| 56 | ||
| 57 | #include "pmcc4_defs.h" | |
| 58 | ||
| 59 | ||
| 60 | /*------------------------------------------------------------------------ | |
| 61 | // Vendor, Board Identification definitions | |
| 62 | //------------------------------------------------------------------------ | |
| 63 | */ | |
| 64 | ||
| 65 | #define PCI_VENDOR_ID_CONEXANT 0x14f1 | |
| 66 | #define PCI_DEVICE_ID_CN8471 0x8471 | |
| 67 | #define PCI_DEVICE_ID_CN8472 0x8472 | |
| 68 | #define PCI_DEVICE_ID_CN8474 0x8474 | |
| 69 | #define PCI_DEVICE_ID_CN8478 0x8478 | |
| 70 | #define PCI_DEVICE_ID_CN8500 0x8500 | |
| 71 | #define PCI_DEVICE_ID_CN8501 0x8501 | |
| 72 | #define PCI_DEVICE_ID_CN8502 0x8502 | |
| 73 | #define PCI_DEVICE_ID_CN8503 0x8503 | |
| 74 | ||
| 75 | #define INT_QUEUE_SIZE MUSYCC_NIQD | |
| 76 | ||
| 77 | /* RAM image of MUSYCC registers layed out as a C structure */ | |
| 78 | struct musycc_groupr | |
| 79 | { | |
| 80 | VINT32 thp[32]; /* Transmit Head Pointer [5-29] */ | |
| 81 | VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */ | |
| 82 | VINT32 rhp[32]; /* Receive Head Pointer [5-29] */ | |
| 83 | VINT32 rmp[32]; /* Receive Message Pointer [5-30] */ | |
| 84 | VINT8 ttsm[128]; /* Time Slot Map [5-22] */ | |
| 85 | VINT8 tscm[256]; /* Subchannel Map [5-24] */ | |
| 86 | VINT32 tcct[32]; /* Channel Configuration [5-26] */ | |
| 87 | VINT8 rtsm[128]; /* Time Slot Map [5-22] */ | |
| 88 | VINT8 rscm[256]; /* Subchannel Map [5-24] */ | |
| 89 | VINT32 rcct[32]; /* Channel Configuration [5-26] */ | |
| 90 | VINT32 __glcd; /* Global Configuration Descriptor [5-10] */ | |
| 91 | VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */ | |
| 92 | VINT32 __iql; /* Interrupt Queue Length [5-36] */ | |
| 93 | VINT32 grcd; /* Group Configuration Descriptor [5-16] */ | |
| 94 | VINT32 mpd; /* Memory Protection Descriptor [5-18] */ | |
| 95 | VINT32 mld; /* Message Length Descriptor [5-20] */ | |
| 96 | VINT32 pcd; /* Port Configuration Descriptor [5-19] */ | |
| 97 | }; | |
| 98 | ||
| 99 | /* hardware MUSYCC registers layed out as a C structure */ | |
| 100 | struct musycc_globalr | |
| 101 | { | |
| 102 | VINT32 gbp; /* Group Base Pointer */ | |
| 103 | VINT32 dacbp; /* Dual Address Cycle Base Pointer */ | |
| 104 | VINT32 srd; /* Service Request Descriptor */ | |
| 105 | VINT32 isd; /* Interrupt Service Descriptor */ | |
| 106 | /* | |
| 107 | * adjust __thp due to above 4 registers, which are not contained | |
| 108 | * within musycc_groupr[]. All __XXX[] are just place holders, | |
| 109 | * anyhow. | |
| 110 | */ | |
| 111 | VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */ | |
| 112 | VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */ | |
| 113 | VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */ | |
| 114 | VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */ | |
| 115 | VINT8 ttsm[128]; /* Time Slot Map [5-22] */ | |
| 116 | VINT8 tscm[256]; /* Subchannel Map [5-24] */ | |
| 117 | VINT32 tcct[32]; /* Channel Configuration [5-26] */ | |
| 118 | VINT8 rtsm[128]; /* Time Slot Map [5-22] */ | |
| 119 | VINT8 rscm[256]; /* Subchannel Map [5-24] */ | |
| 120 | VINT32 rcct[32]; /* Channel Configuration [5-26] */ | |
| 121 | VINT32 glcd; /* Global Configuration Descriptor [5-10] */ | |
| 122 | VINT32 iqp; /* Interrupt Queue Pointer [5-36] */ | |
| 123 | VINT32 iql; /* Interrupt Queue Length [5-36] */ | |
| 124 | VINT32 grcd; /* Group Configuration Descriptor [5-16] */ | |
| 125 | VINT32 mpd; /* Memory Protection Descriptor [5-18] */ | |
| 126 | VINT32 mld; /* Message Length Descriptor [5-20] */ | |
| 127 | VINT32 pcd; /* Port Configuration Descriptor [5-19] */ | |
| 128 | VINT32 rbist; /* Receive BIST status [5-4] */ | |
| 129 | VINT32 tbist; /* Receive BIST status [5-4] */ | |
| 130 | }; | |
| 131 | ||
| 132 | /* Global Config Descriptor bit macros */ | |
| 133 | #define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */ | |
| 134 | #define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */ | |
| 135 | #define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */ | |
| 136 | #define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */ | |
| 137 | #define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit | |
| 138 | * field */ | |
| 139 | #define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit | |
| 140 | * field */ | |
| 141 | #define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit | |
| 142 | * field */ | |
| 143 | #define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */ | |
| 144 | #define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp | |
| 145 | * 4,5,6,7 */ | |
| 146 | #define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3, | |
| 147 | * etc... */ | |
| 148 | #define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2, | |
| 149 | * etc... */ | |
| 150 | ||
| 151 | /* and board specific assignments... */ | |
| 152 | #ifdef SBE_WAN256T3_ENABLE | |
| 153 | #define BLAPSE_VAL 0 | |
| 154 | #define ALAPSE_VAL 0 | |
| 155 | #define ELAPSE_VAL 7 | |
| 156 | #define PORTMAP_VAL MUSYCC_GCD_PORTMAP_2 | |
| 157 | #endif | |
| 158 | ||
| 159 | #ifdef SBE_PMCC4_ENABLE | |
| 160 | #define BLAPSE_VAL 7 | |
| 161 | #define ALAPSE_VAL 3 | |
| 162 | #define ELAPSE_VAL 7 | |
| 163 | #define PORTMAP_VAL MUSYCC_GCD_PORTMAP_0 | |
| 164 | #endif | |
| 165 | ||
| 166 | #define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \ | |
| 167 | ((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \ | |
| 168 | ((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \ | |
| 169 | (MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL) | |
| 170 | ||
| 171 | /* Group Config Descriptor bit macros */ | |
| 172 | #define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */ | |
| 173 | #define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */ | |
| 174 | #define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for | |
| 175 | * subchanneling */ | |
| 176 | #define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message | |
| 177 | * processing disabled all | |
| 178 | * channels */ | |
| 179 | #define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs | |
| 180 | * disabled */ | |
| 181 | #define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment | |
| 182 | * irq disabled */ | |
| 183 | #define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status | |
| 184 | * overwrite disabled */ | |
| 185 | #define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status | |
| 186 | * overwrite disabled */ | |
| 187 | #define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */ | |
| 188 | #define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits | |
| 189 | * copy enable. Conexant sez | |
| 190 | * turn this on */ | |
| 191 | #define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */ | |
| 192 | #define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */ | |
| 193 | #define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */ | |
| 194 | #define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle | |
| 195 | * bit field */ | |
| 196 | #define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM | |
| 197 | * count threshold */ | |
| 198 | ||
| 199 | /* Port Config Descriptor bit macros */ | |
| 200 | #define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */ | |
| 201 | #define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */ | |
| 202 | #define MUSYCC_PCD_NX64_MODE 4 | |
| 203 | #define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK | |
| 204 | * rising edge */ | |
| 205 | #define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on | |
| 206 | * TCLK rising edge */ | |
| 207 | #define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK | |
| 208 | * rising edge */ | |
| 209 | #define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on | |
| 210 | * RCLK rising edge */ | |
| 211 | #define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame | |
| 212 | * signal on RCLK rising edge */ | |
| 213 | #define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes | |
| 214 | * logic 1 on output, else | |
| 215 | * tristate */ | |
| 216 | #define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode | |
| 217 | * between E1 and T1 */ | |
| 218 | ||
| 219 | /* Time Slot Descriptor bit macros */ | |
| 220 | #define MUSYCC_TSD_MODE_64KBPS 4 | |
| 221 | #define MUSYCC_TSD_MODE_56KBPS 5 | |
| 222 | #define MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6 | |
| 223 | #define MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7 | |
| 224 | ||
| 225 | /* Message Descriptor bit macros */ | |
| 226 | #define MUSYCC_MDT_BASE03_ADDR 0x00006000 | |
| 227 | ||
| 228 | /* Channel Config Descriptor bit macros */ | |
| 229 | #define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */ | |
| 230 | #define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */ | |
| 231 | #define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT | |
| 232 | * irqs disabled */ | |
| 233 | #define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs | |
| 234 | * disabled */ | |
| 235 | #define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */ | |
| 236 | #define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */ | |
| 237 | #define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */ | |
| 238 | #define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */ | |
| 239 | #define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with | |
| 240 | * received data */ | |
| 241 | #define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit | |
| 242 | * field */ | |
| 243 | #define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */ | |
| 244 | #define MUSYCC_CCD_SS7 1 | |
| 245 | #define MUSYCC_CCD_HDLC_FCS16 2 | |
| 246 | #define MUSYCC_CCD_HDLC_FCS32 3 | |
| 247 | #define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */ | |
| 248 | #define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */ | |
| 249 | #define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit | |
| 250 | * field */ | |
| 251 | #define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data | |
| 252 | * buffer length */ | |
| 253 | #define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data | |
| 254 | * buffer starting location */ | |
| 255 | ||
| 256 | /**************************************************************************** | |
| 257 | * Interrupt Descriptor Information */ | |
| 258 | ||
| 259 | #define INT_EMPTY_ENTRY 0xfeedface | |
| 260 | #define INT_EMPTY_ENTRY2 0xdeadface | |
| 261 | ||
| 262 | /**************************************************************************** | |
| 263 | * Interrupt Status Descriptor | |
| 264 | * | |
| 265 | * NOTE: One must first fetch the value of the interrupt status descriptor | |
| 266 | * into a local variable, then pass that value into the read macros. This | |
| 267 | * is required to avoid race conditions. | |
| 268 | ***/ | |
| 269 | ||
| 270 | #define INTRPTS_NEXTINT_M 0x7FFF0000 | |
| 271 | #define INTRPTS_NEXTINT_S 16 | |
| 272 | #define INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S) | |
| 273 | ||
| 274 | #define INTRPTS_INTFULL_M 0x00008000 | |
| 275 | #define INTRPTS_INTFULL_S 15 | |
| 276 | #define INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S) | |
| 277 | ||
| 278 | #define INTRPTS_INTCNT_M 0x00007FFF | |
| 279 | #define INTRPTS_INTCNT_S 0 | |
| 280 | #define INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S) | |
| 281 | ||
| 282 | ||
| 283 | /**************************************************************************** | |
| 284 | * Interrupt Descriptor | |
| 285 | ***/ | |
| 286 | ||
| 287 | #define INTRPT_DIR_M 0x80000000 | |
| 288 | #define INTRPT_DIR_S 31 | |
| 289 | #define INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S) | |
| 290 | ||
| 291 | #define INTRPT_GRP_M 0x60000000 | |
| 292 | #define INTRPT_GRP_MSB_M 0x00004000 | |
| 293 | #define INTRPT_GRP_S 29 | |
| 294 | #define INTRPT_GRP_MSB_S 12 | |
| 295 | #define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \ | |
| 296 | ((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S)) | |
| 297 | ||
| 298 | #define INTRPT_CH_M 0x1F000000 | |
| 299 | #define INTRPT_CH_S 24 | |
| 300 | #define INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S) | |
| 301 | ||
| 302 | #define INTRPT_EVENT_M 0x00F00000 | |
| 303 | #define INTRPT_EVENT_S 20 | |
| 304 | #define INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S) | |
| 305 | ||
| 306 | #define INTRPT_ERROR_M 0x000F0000 | |
| 307 | #define INTRPT_ERROR_S 16 | |
| 308 | #define INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S) | |
| 309 | ||
| 310 | #define INTRPT_ILOST_M 0x00008000 | |
| 311 | #define INTRPT_ILOST_S 15 | |
| 312 | #define INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S) | |
| 313 | ||
| 314 | #define INTRPT_PERR_M 0x00004000 | |
| 315 | #define INTRPT_PERR_S 14 | |
| 316 | #define INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S) | |
| 317 | ||
| 318 | #define INTRPT_BLEN_M 0x00003FFF | |
| 319 | #define INTRPT_BLEN_S 0 | |
| 320 | #define INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S) | |
| 321 | ||
| 322 | ||
| 323 | /* Buffer Descriptor bit macros */ | |
| 324 | #define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host | |
| 325 | * owner on receive */ | |
| 326 | #define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */ | |
| 327 | #define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */ | |
| 328 | #define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */ | |
| 329 | #define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */ | |
| 330 | ||
| 331 | #define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer | |
| 332 | * for ownership */ | |
| 333 | #define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of | |
| 334 | * the message */ | |
| 335 | #define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */ | |
| 336 | #define PADFILL_ENABLE 0x01000000 /* Enable padfill */ | |
| 337 | #define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */ | |
| 338 | #define LENGTH_MASK 0X3fff /* This part of status descriptor is | |
| 339 | * length */ | |
| 340 | #define IDLE_CODE 25 /* Position index for idle code (2 | |
| 341 | * bits) */ | |
| 342 | #define EXTRA_FLAGS 16 /* Position index for minimum flags | |
| 343 | * between messages (8 bits) */ | |
| 344 | #define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the | |
| 345 | * pattern is OR'd in */ | |
| 346 | #define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the | |
| 347 | * pattern is OR'd in */ | |
| 348 | #define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on | |
| 349 | * the polled mode descriptor */ | |
| 350 | ||
| 351 | /* Service Request Descriptor bit macros */ | |
| 352 | #define SREQ 8 /* Position index for service request bit | |
| 353 | * field */ | |
| 354 | #define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */ | |
| 355 | #define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */ | |
| 356 | #define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */ | |
| 357 | #define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global | |
| 358 | * config deswc and interrupt | |
| 359 | * queue desc */ | |
| 360 | #define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot | |
| 361 | * and Subchannel maps, | |
| 362 | * Channel Config, */ | |
| 363 | /* | |
| 364 | * Group Config, Memory Protect, Message Length, and Port Config | |
| 365 | * Descriptors | |
| 366 | */ | |
| 367 | #define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head | |
| 368 | * Pointer, process first | |
| 369 | * Message Descriptor */ | |
| 370 | #define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */ | |
| 371 | #define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */ | |
| 372 | #define SR_JUMP (10<<(SREQ)) /* a: Process new Message | |
| 373 | * List */ | |
| 374 | #define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel | |
| 375 | * Configuration Descriptor */ | |
| 376 | #define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global | |
| 377 | * Configuration Descriptor */ | |
| 378 | #define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue | |
| 379 | * Descriptor */ | |
| 380 | #define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group | |
| 381 | * Configuration Descriptor */ | |
| 382 | #define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection | |
| 383 | * Descriptor */ | |
| 384 | #define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length | |
| 385 | * Descriptor */ | |
| 386 | #define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port | |
| 387 | * Configuration Descriptor */ | |
| 388 | #define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */ | |
| 389 | #define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */ | |
| 390 | #define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel | |
| 391 | * Configuration Table for | |
| 392 | * the group */ | |
| 393 | #define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit. | |
| 394 | * Bit off indicates receive | |
| 395 | * direction */ | |
| 396 | #define SR_RX_DIRECTION 0x00000000 | |
| 397 | ||
| 398 | /* Interrupt Descriptor bit macros */ | |
| 399 | #define GROUP10 29 /* Position index for the 2 LS group | |
| 400 | * bits */ | |
| 401 | #define CHANNEL 24 /* Position index for channel bits */ | |
| 402 | #define INT_IQD_TX 0x80000000 | |
| 403 | #define INT_IQD_GRP 0x60000000 | |
| 404 | #define INT_IQD_CHAN 0x1f000000 | |
| 405 | #define INT_IQD_EVENT 0x00f00000 | |
| 406 | #define INT_IQD_ERROR 0x000f0000 | |
| 407 | #define INT_IQD_ILOST 0x00008000 | |
| 408 | #define INT_IQD_PERR 0x00004000 | |
| 409 | #define INT_IQD_BLEN 0x00003fff | |
| 410 | ||
| 411 | /* Interrupt Descriptor Events */ | |
| 412 | #define EVE_EVENT 20 /* Position index for event bits */ | |
| 413 | #define EVE_NONE 0 /* No event to report in this | |
| 414 | * interrupt */ | |
| 415 | #define EVE_SACK 1 /* Service Request acknowledge */ | |
| 416 | #define EVE_EOB 2 /* End of Buffer */ | |
| 417 | #define EVE_EOM 3 /* End of Message */ | |
| 418 | #define EVE_EOP 4 /* End of Padfill */ | |
| 419 | #define EVE_CHABT 5 /* Change to Abort Code */ | |
| 420 | #define EVE_CHIC 6 /* Change to Idle Code */ | |
| 421 | #define EVE_FREC 7 /* Frame Recovery */ | |
| 422 | #define EVE_SINC 8 /* MTP2 SUERM Increment */ | |
| 423 | #define EVE_SDEC 9 /* MTP2 SUERM Decrement */ | |
| 424 | #define EVE_SFILT 10 /* MTP2 SUERM Filtered Message */ | |
| 425 | /* Interrupt Descriptor Errors */ | |
| 426 | #define ERR_ERRORS 16 /* Position index for error bits */ | |
| 427 | #define ERR_BUF 1 /* Buffer Error */ | |
| 428 | #define ERR_COFA 2 /* Change of Frame Alignment Error */ | |
| 429 | #define ERR_ONR 3 /* Owner Bit Error */ | |
| 430 | #define ERR_PROT 4 /* Memory Protection Error */ | |
| 431 | #define ERR_OOF 8 /* Out of Frame Error */ | |
| 432 | #define ERR_FCS 9 /* FCS Error */ | |
| 433 | #define ERR_ALIGN 10 /* Octet Alignment Error */ | |
| 434 | #define ERR_ABT 11 /* Abort Termination */ | |
| 435 | #define ERR_LNG 12 /* Long Message Error */ | |
| 436 | #define ERR_SHT 13 /* Short Message Error */ | |
| 437 | #define ERR_SUERR 14 /* SUERM threshold exceeded */ | |
| 438 | #define ERR_PERR 15 /* PCI Parity Error */ | |
| 439 | /* Other Stuff */ | |
| 440 | #define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off | |
| 441 | * indicates receive direction */ | |
| 442 | #define ILOST 0x00008000 /* Interrupt Lost */ | |
| 443 | #define GROUPMSB 0x00004000 /* Group number MSB */ | |
| 444 | #define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */ | |
| 445 | #define INITIAL_STATUS 0x10000 /* IRQ status should be this after | |
| 446 | * reset */ | |
| 447 | ||
| 448 | /* This must be defined on an entire channel group (Port) basis */ | |
| 449 | #define SUERM_THRESHOLD 0x1f | |
| 450 | ||
| 451 | #ifdef __cplusplus | |
| 452 | } | |
| 453 | #endif | |
| 454 | ||
| 455 | #undef VINT32 | |
| 456 | #undef VINT8 | |
| 457 | ||
| 458 | #endif /*** _INC_MUSYCC_H_ ***/ | |
| 459 | ||
| 460 | /*** End-of-File ***/ |