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50ee11fe BB |
1 | /* Copyright (C) 2003-2005 SBE, Inc. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License as published by | |
5 | * the Free Software Foundation; either version 2 of the License, or | |
6 | * (at your option) any later version. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
e6e4d05d JP |
14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
15 | ||
50ee11fe BB |
16 | #include <linux/slab.h> |
17 | #include <asm/io.h> | |
18 | #include <asm/byteorder.h> | |
19 | #include <linux/netdevice.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/hdlc.h> | |
22 | #include "pmcc4_sysdep.h" | |
23 | #include "sbecom_inline_linux.h" | |
24 | #include "libsbew.h" | |
25 | #include "pmcc4.h" | |
26 | ||
27 | ||
28 | #ifdef SBE_INCLUDE_SYMBOLS | |
29 | #define STATIC | |
30 | #else | |
31 | #define STATIC static | |
32 | #endif | |
33 | ||
34 | #if defined(CONFIG_SBE_HDLC_V7) || defined(CONFIG_SBE_WAN256T3_HDLC_V7) || \ | |
35 | defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE) | |
36 | #define _v7_hdlc_ 1 | |
37 | #else | |
38 | #define _v7_hdlc_ 0 | |
39 | #endif | |
40 | ||
41 | #if _v7_hdlc_ | |
42 | #define V7(x) (x ## _v7) | |
43 | extern int hdlc_netif_rx_v7 (hdlc_device *, struct sk_buff *); | |
44 | extern int register_hdlc_device_v7 (hdlc_device *); | |
45 | extern int unregister_hdlc_device_v7 (hdlc_device *); | |
46 | ||
47 | #else | |
48 | #define V7(x) x | |
49 | #endif | |
50 | ||
51 | ||
52 | #ifndef USE_MAX_INT_DELAY | |
53 | static int dummy = 0; | |
54 | ||
55 | #endif | |
56 | ||
57 | extern int log_level; | |
58 | extern int drvr_state; | |
59 | ||
60 | ||
61 | #if 1 | |
62 | u_int32_t | |
63 | pci_read_32 (u_int32_t *p) | |
64 | { | |
65 | #ifdef FLOW_DEBUG | |
66 | u_int32_t v; | |
67 | ||
68 | FLUSH_PCI_READ (); | |
69 | v = le32_to_cpu (*p); | |
70 | if (log_level >= LOG_DEBUG) | |
694a9807 | 71 | pr_info("pci_read : %x = %x\n", (u_int32_t) p, v); |
50ee11fe BB |
72 | return v; |
73 | #else | |
74 | FLUSH_PCI_READ (); /* */ | |
75 | return le32_to_cpu (*p); | |
76 | #endif | |
77 | } | |
78 | ||
79 | void | |
80 | pci_write_32 (u_int32_t *p, u_int32_t v) | |
81 | { | |
82 | #ifdef FLOW_DEBUG | |
83 | if (log_level >= LOG_DEBUG) | |
694a9807 | 84 | pr_info("pci_write: %x = %x\n", (u_int32_t) p, v); |
50ee11fe BB |
85 | #endif |
86 | *p = cpu_to_le32 (v); | |
87 | FLUSH_PCI_WRITE (); /* This routine is called from routines | |
88 | * which do multiple register writes | |
89 | * which themselves need flushing between | |
90 | * writes in order to guarantee write | |
91 | * ordering. It is less code-cumbersome | |
92 | * to flush here-in then to investigate | |
93 | * and code the many other register | |
94 | * writing routines. */ | |
95 | } | |
96 | #endif | |
97 | ||
98 | ||
99 | void | |
100 | pci_flush_write (ci_t * ci) | |
101 | { | |
102 | volatile u_int32_t v; | |
103 | ||
104 | /* issue a PCI read to flush PCI write thru bridge */ | |
105 | v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */ | |
106 | ||
107 | /* | |
108 | * return nothing, this just reads PCI bridge interface to flush | |
109 | * previously written data | |
110 | */ | |
111 | } | |
112 | ||
113 | ||
114 | STATIC void | |
115 | watchdog_func (unsigned long arg) | |
116 | { | |
117 | struct watchdog *wd = (void *) arg; | |
118 | ||
119 | if (drvr_state != SBE_DRVR_AVAILABLE) | |
120 | { | |
121 | if (log_level >= LOG_MONITOR) | |
e6e4d05d | 122 | pr_warning("%s: drvr not available (%x)\n", __func__, drvr_state); |
50ee11fe BB |
123 | return; |
124 | } | |
125 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) | |
126 | /* Initialize the tq entry only the first time */ | |
127 | if (wd->init_tq) | |
128 | { | |
129 | wd->init_tq = 0; | |
130 | wd->tq.routine = wd->func; | |
131 | wd->tq.sync = 0; | |
132 | wd->tq.data = wd->softc; | |
133 | } | |
134 | schedule_task (&wd->tq); | |
135 | #else | |
136 | schedule_work (&wd->work); | |
137 | #endif | |
138 | mod_timer (&wd->h, jiffies + wd->ticks); | |
139 | } | |
140 | ||
141 | int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *c, int usec) | |
142 | { | |
143 | wdp->func = f; | |
144 | wdp->softc = c; | |
145 | wdp->ticks = (HZ) * (usec / 1000) / 1000; | |
146 | INIT_WORK(&wdp->work, (void *)f); | |
147 | init_timer (&wdp->h); | |
148 | { | |
149 | ci_t *ci = (ci_t *) c; | |
150 | ||
151 | wdp->h.data = (unsigned long) &ci->wd; | |
152 | } | |
153 | wdp->h.function = watchdog_func; | |
154 | return 0; | |
155 | } | |
156 | ||
157 | void | |
158 | OS_uwait (int usec, char *description) | |
159 | { | |
160 | int tmp; | |
161 | ||
162 | if (usec >= 1000) | |
163 | { | |
164 | mdelay (usec / 1000); | |
165 | /* now delay residual */ | |
166 | tmp = (usec / 1000) * 1000; /* round */ | |
167 | tmp = usec - tmp; /* residual */ | |
168 | if (tmp) | |
169 | { /* wait on residual */ | |
170 | udelay (tmp); | |
171 | } | |
172 | } else | |
173 | { | |
174 | udelay (usec); | |
175 | } | |
176 | } | |
177 | ||
178 | /* dummy short delay routine called as a subroutine so that compiler | |
179 | * does not optimize/remove its intent (a short delay) | |
180 | */ | |
181 | ||
182 | void | |
183 | OS_uwait_dummy (void) | |
184 | { | |
185 | #ifndef USE_MAX_INT_DELAY | |
186 | dummy++; | |
187 | #else | |
188 | udelay (1); | |
189 | #endif | |
190 | } | |
191 | ||
192 | ||
193 | void | |
194 | OS_sem_init (void *sem, int state) | |
195 | { | |
196 | switch (state) | |
197 | { | |
198 | case SEM_TAKEN: | |
199 | init_MUTEX_LOCKED ((struct semaphore *) sem); | |
200 | break; | |
201 | case SEM_AVAILABLE: | |
202 | init_MUTEX ((struct semaphore *) sem); | |
203 | break; | |
204 | default: /* otherwise, set sem.count to state's | |
205 | * value */ | |
206 | sema_init (sem, state); | |
207 | break; | |
208 | } | |
209 | } | |
210 | ||
211 | ||
212 | int | |
213 | sd_line_is_ok (void *user) | |
214 | { | |
215 | struct net_device *ndev = (struct net_device *) user; | |
216 | ||
217 | return (netif_carrier_ok (ndev)); | |
218 | } | |
219 | ||
220 | void | |
221 | sd_line_is_up (void *user) | |
222 | { | |
223 | struct net_device *ndev = (struct net_device *) user; | |
224 | ||
225 | netif_carrier_on (ndev); | |
226 | return; | |
227 | } | |
228 | ||
229 | void | |
230 | sd_line_is_down (void *user) | |
231 | { | |
232 | struct net_device *ndev = (struct net_device *) user; | |
233 | ||
234 | netif_carrier_off (ndev); | |
235 | return; | |
236 | } | |
237 | ||
238 | void | |
239 | sd_disable_xmit (void *user) | |
240 | { | |
241 | struct net_device *dev = (struct net_device *) user; | |
242 | ||
243 | netif_stop_queue (dev); | |
244 | return; | |
245 | } | |
246 | ||
247 | void | |
248 | sd_enable_xmit (void *user) | |
249 | { | |
250 | struct net_device *dev = (struct net_device *) user; | |
251 | ||
252 | netif_wake_queue (dev); | |
253 | return; | |
254 | } | |
255 | ||
256 | int | |
257 | sd_queue_stopped (void *user) | |
258 | { | |
259 | struct net_device *ndev = (struct net_device *) user; | |
260 | ||
261 | return (netif_queue_stopped (ndev)); | |
262 | } | |
263 | ||
264 | void sd_recv_consume(void *token, size_t len, void *user) | |
265 | { | |
266 | struct net_device *ndev = user; | |
267 | struct sk_buff *skb = token; | |
268 | ||
269 | skb->dev = ndev; | |
270 | skb_put (skb, len); | |
271 | skb->protocol = hdlc_type_trans(skb, ndev); | |
272 | netif_rx(skb); | |
273 | } | |
274 | ||
275 | ||
276 | /** | |
277 | ** Read some reserved location w/in the COMET chip as a usable | |
278 | ** VMETRO trigger point or other trace marking event. | |
279 | **/ | |
280 | ||
281 | #include "comet.h" | |
282 | ||
283 | extern ci_t *CI; /* dummy pointer to board ZERO's data */ | |
284 | void | |
285 | VMETRO_TRACE (void *x) | |
286 | { | |
287 | u_int32_t y = (u_int32_t) x; | |
288 | ||
289 | pci_write_32 ((u_int32_t *) &CI->cpldbase->leds, y); | |
290 | } | |
291 | ||
292 | ||
293 | void | |
294 | VMETRO_TRIGGER (ci_t * ci, int x) | |
295 | { | |
296 | comet_t *comet; | |
297 | volatile u_int32_t data; | |
298 | ||
299 | comet = ci->port[0].cometbase; /* default to COMET # 0 */ | |
300 | ||
301 | switch (x) | |
302 | { | |
303 | default: | |
304 | case 0: | |
305 | data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */ | |
306 | break; | |
307 | case 1: | |
308 | data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */ | |
309 | break; | |
310 | case 2: | |
311 | data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */ | |
312 | break; | |
313 | case 3: | |
314 | data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */ | |
315 | break; | |
316 | case 4: | |
317 | data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */ | |
318 | break; | |
319 | case 5: | |
320 | data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */ | |
321 | break; | |
322 | case 6: | |
323 | data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */ | |
324 | break; | |
325 | case 7: | |
326 | data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */ | |
327 | break; | |
328 | case 8: | |
329 | data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */ | |
330 | break; | |
331 | case 9: | |
332 | data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */ | |
333 | break; | |
334 | case 10: | |
335 | data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */ | |
336 | break; | |
337 | case 11: | |
338 | data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */ | |
339 | break; | |
340 | case 12: | |
341 | data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */ | |
342 | break; | |
343 | case 13: | |
344 | data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */ | |
345 | break; | |
346 | case 14: | |
347 | data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */ | |
348 | break; | |
349 | case 15: | |
350 | data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */ | |
351 | break; | |
352 | case 16: | |
353 | data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */ | |
354 | break; | |
355 | case 17: | |
356 | data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */ | |
357 | break; | |
358 | case 18: | |
359 | data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */ | |
360 | break; | |
361 | case 19: | |
362 | data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */ | |
363 | break; | |
364 | } | |
365 | } | |
366 | ||
367 | ||
368 | /*** End-of-File ***/ |