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7963eb43 JW |
1 | /*************************************************************************** |
2 | * Copyright (c) 2005-2009, Broadcom Corporation. | |
3 | * | |
4 | * Name: crystalhd_hw . h | |
5 | * | |
6 | * Description: | |
7 | * BCM70012 Linux driver hardware layer. | |
8 | * | |
9 | * HISTORY: | |
10 | * | |
11 | ********************************************************************** | |
12 | * This file is part of the crystalhd device driver. | |
13 | * | |
14 | * This driver is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation, version 2 of the License. | |
17 | * | |
18 | * This driver is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this driver. If not, see <http://www.gnu.org/licenses/>. | |
25 | **********************************************************************/ | |
26 | ||
27 | #ifndef _CRYSTALHD_HW_H_ | |
28 | #define _CRYSTALHD_HW_H_ | |
29 | ||
30 | #include "crystalhd_misc.h" | |
31 | #include "crystalhd_fw_if.h" | |
32 | ||
33 | /* HW constants..*/ | |
34 | #define DMA_ENGINE_CNT 2 | |
35 | #define MAX_PIB_Q_DEPTH 64 | |
36 | #define MIN_PIB_Q_DEPTH 2 | |
37 | #define WR_POINTER_OFF 4 | |
38 | ||
39 | #define ASPM_L1_ENABLE (BC_BIT(27)) | |
40 | ||
41 | /************************************************* | |
42 | 7412 Decoder Registers. | |
43 | **************************************************/ | |
44 | #define FW_CMD_BUFF_SZ 64 | |
45 | #define TS_Host2CpuSnd 0x00000100 | |
46 | #define Hst2CpuMbx1 0x00100F00 | |
47 | #define Cpu2HstMbx1 0x00100F04 | |
48 | #define MbxStat1 0x00100F08 | |
49 | #define Stream2Host_Intr_Sts 0x00100F24 | |
50 | #define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ | |
51 | ||
52 | /* TS input status register */ | |
53 | #define TS_StreamAFIFOStatus 0x0010044C | |
54 | #define TS_StreamBFIFOStatus 0x0010084C | |
55 | ||
56 | /*UART Selection definitions*/ | |
57 | #define UartSelectA 0x00100300 | |
58 | #define UartSelectB 0x00100304 | |
59 | ||
60 | #define BSVS_UART_DEC_NONE 0x00 | |
61 | #define BSVS_UART_DEC_OUTER 0x01 | |
62 | #define BSVS_UART_DEC_INNER 0x02 | |
63 | #define BSVS_UART_STREAM 0x03 | |
64 | ||
65 | /* Code-In fifo */ | |
66 | #define REG_DecCA_RegCinCTL 0xa00 | |
67 | #define REG_DecCA_RegCinBase 0xa0c | |
68 | #define REG_DecCA_RegCinEnd 0xa10 | |
69 | #define REG_DecCA_RegCinWrPtr 0xa04 | |
70 | #define REG_DecCA_RegCinRdPtr 0xa08 | |
71 | ||
72 | #define REG_Dec_TsUser0Base 0x100864 | |
73 | #define REG_Dec_TsUser0Rdptr 0x100868 | |
74 | #define REG_Dec_TsUser0Wrptr 0x10086C | |
75 | #define REG_Dec_TsUser0End 0x100874 | |
76 | ||
77 | /* ASF Case ...*/ | |
78 | #define REG_Dec_TsAudCDB2Base 0x10036c | |
79 | #define REG_Dec_TsAudCDB2Rdptr 0x100378 | |
80 | #define REG_Dec_TsAudCDB2Wrptr 0x100374 | |
81 | #define REG_Dec_TsAudCDB2End 0x100370 | |
82 | ||
83 | /* DRAM bringup Registers */ | |
84 | #define SDRAM_PARAM 0x00040804 | |
85 | #define SDRAM_PRECHARGE 0x000408B0 | |
86 | #define SDRAM_EXT_MODE 0x000408A4 | |
87 | #define SDRAM_MODE 0x000408A0 | |
88 | #define SDRAM_REFRESH 0x00040890 | |
89 | #define SDRAM_REF_PARAM 0x00040808 | |
90 | ||
91 | #define DecHt_PllACtl 0x34000C | |
92 | #define DecHt_PllBCtl 0x340010 | |
93 | #define DecHt_PllCCtl 0x340014 | |
94 | #define DecHt_PllDCtl 0x340034 | |
95 | #define DecHt_PllECtl 0x340038 | |
96 | #define AUD_DSP_MISC_SOFT_RESET 0x00240104 | |
97 | #define AIO_MISC_PLL_RESET 0x0026000C | |
98 | #define PCIE_CLK_REQ_REG 0xDC | |
99 | #define PCI_CLK_REQ_ENABLE (BC_BIT(8)) | |
100 | ||
101 | /************************************************* | |
102 | F/W Copy engine definitions.. | |
103 | **************************************************/ | |
104 | #define BC_FWIMG_ST_ADDR 0x00000000 | |
105 | /* FIXME: jarod: there's a kernel function that'll do this for us... */ | |
106 | #define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n))) | |
107 | #define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) | |
108 | ||
109 | #define DecHt_HostSwReset 0x340000 | |
110 | #define BC_DRAM_FW_CFG_ADDR 0x001c2000 | |
111 | ||
abfc768d | 112 | union addr_64 { |
7963eb43 JW |
113 | struct { |
114 | uint32_t low_part; | |
115 | uint32_t high_part; | |
116 | }; | |
117 | ||
118 | uint64_t full_addr; | |
119 | ||
abfc768d | 120 | }; |
7963eb43 | 121 | |
abfc768d | 122 | union intr_mask_reg { |
7963eb43 JW |
123 | struct { |
124 | uint32_t mask_tx_done:1; | |
125 | uint32_t mask_tx_err:1; | |
126 | uint32_t mask_rx_done:1; | |
127 | uint32_t mask_rx_err:1; | |
128 | uint32_t mask_pcie_err:1; | |
129 | uint32_t mask_pcie_rbusmast_err:1; | |
130 | uint32_t mask_pcie_rgr_bridge:1; | |
131 | uint32_t reserved:25; | |
132 | }; | |
133 | ||
134 | uint32_t whole_reg; | |
135 | ||
abfc768d | 136 | }; |
7963eb43 | 137 | |
abfc768d | 138 | union link_misc_perst_deco_ctrl { |
7963eb43 JW |
139 | struct { |
140 | uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ | |
141 | uint32_t reserved0:3; /* Reserved.No Effect*/ | |
142 | uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ | |
143 | uint32_t reserved1:27; /* Reseved. No Effect*/ | |
144 | }; | |
145 | ||
146 | uint32_t whole_reg; | |
147 | ||
abfc768d | 148 | }; |
7963eb43 | 149 | |
abfc768d | 150 | union link_misc_perst_clk_ctrl { |
7963eb43 JW |
151 | struct { |
152 | uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ | |
153 | uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ | |
154 | uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set | |
155 | to select an alternate clock before setting this bit.*/ | |
156 | uint32_t reserved0:5; /* Reserved */ | |
157 | uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ | |
158 | uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ | |
159 | uint32_t reserved1:12; /* Reserved */ | |
160 | }; | |
161 | ||
162 | uint32_t whole_reg; | |
163 | ||
abfc768d | 164 | }; |
7963eb43 | 165 | |
abfc768d | 166 | union link_misc_perst_decoder_ctrl { |
7963eb43 JW |
167 | struct { |
168 | uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ | |
169 | uint32_t res0:3; /* Reserved.No Effect*/ | |
170 | uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ | |
171 | uint32_t res1:27; /* Reseved. No Effect */ | |
172 | }; | |
173 | ||
174 | uint32_t whole_reg; | |
175 | ||
abfc768d | 176 | }; |
7963eb43 | 177 | |
abfc768d | 178 | union desc_low_addr_reg { |
7963eb43 JW |
179 | struct { |
180 | uint32_t list_valid:1; | |
181 | uint32_t reserved:4; | |
182 | uint32_t low_addr:27; | |
183 | }; | |
184 | ||
185 | uint32_t whole_reg; | |
186 | ||
abfc768d | 187 | }; |
7963eb43 | 188 | |
abfc768d | 189 | struct dma_descriptor { /* 8 32-bit values */ |
7963eb43 JW |
190 | /* 0th u32 */ |
191 | uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ | |
192 | uint32_t res0:4; /* bits 28-31: Reserved */ | |
193 | ||
194 | /* 1st u32 */ | |
195 | uint32_t buff_addr_low; /* 1 buffer address low */ | |
196 | uint32_t buff_addr_high; /* 2 buffer address high */ | |
197 | ||
198 | /* 3rd u32 */ | |
199 | uint32_t res2:2; /* 0-1 - Reserved */ | |
200 | uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ | |
201 | uint32_t res3:6; /* 25-30 reserved */ | |
202 | uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ | |
203 | ||
204 | /* 4th u32 */ | |
205 | uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ | |
206 | uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ | |
207 | uint32_t res4:25; /* 3 - 27 Reserved bits */ | |
208 | uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ | |
209 | uint32_t dma_dir:1; /* 30 bit DMA Direction */ | |
210 | uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ | |
211 | ||
212 | /* 5th u32 */ | |
213 | uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ | |
214 | ||
215 | /* 6th u32 */ | |
216 | uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ | |
217 | ||
218 | /* 7th u32 */ | |
219 | uint32_t res8; /* Last 32bits reserved */ | |
220 | ||
abfc768d | 221 | }; |
7963eb43 JW |
222 | |
223 | /* | |
224 | * We will allocate the memory in 4K pages | |
225 | * the linked list will be a list of 32 byte descriptors. | |
226 | * The virtual address will determine what should be freed. | |
227 | */ | |
abfc768d LD |
228 | struct dma_desc_mem { |
229 | struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ | |
7963eb43 JW |
230 | dma_addr_t phy_addr; /* physical address of each DMA desc */ |
231 | uint32_t sz; | |
232 | struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ | |
233 | ||
abfc768d | 234 | }; |
7963eb43 | 235 | |
abfc768d | 236 | enum list_sts { |
7963eb43 JW |
237 | sts_free = 0, |
238 | ||
239 | /* RX-Y Bits 0:7 */ | |
240 | rx_waiting_y_intr = 0x00000001, | |
241 | rx_y_error = 0x00000004, | |
242 | ||
243 | /* RX-UV Bits 8:16 */ | |
244 | rx_waiting_uv_intr = 0x0000100, | |
245 | rx_uv_error = 0x0000400, | |
246 | ||
247 | rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr), | |
248 | rx_sts_error = (rx_y_error|rx_uv_error), | |
249 | ||
250 | rx_y_mask = 0x000000FF, | |
251 | rx_uv_mask = 0x0000FF00, | |
abfc768d | 252 | }; |
7963eb43 | 253 | |
abfc768d LD |
254 | struct tx_dma_pkt { |
255 | struct dma_desc_mem desc_mem; | |
7963eb43 | 256 | hw_comp_callback call_back; |
abfc768d | 257 | struct crystalhd_dio_req *dio_req; |
7963eb43 JW |
258 | wait_queue_head_t *cb_event; |
259 | uint32_t list_tag; | |
abfc768d | 260 | }; |
7963eb43 | 261 | |
abfc768d LD |
262 | struct crystalhd_rx_dma_pkt { |
263 | struct dma_desc_mem desc_mem; | |
264 | struct crystalhd_dio_req *dio_req; | |
7963eb43 JW |
265 | uint32_t pkt_tag; |
266 | uint32_t flags; | |
abfc768d | 267 | struct BC_PIC_INFO_BLOCK pib; |
7963eb43 | 268 | dma_addr_t uv_phy_addr; |
abfc768d LD |
269 | struct crystalhd_rx_dma_pkt *next; |
270 | }; | |
7963eb43 | 271 | |
abfc768d | 272 | struct crystalhd_hw_stats { |
7963eb43 JW |
273 | uint32_t rx_errors; |
274 | uint32_t tx_errors; | |
275 | uint32_t freeq_count; | |
276 | uint32_t rdyq_count; | |
277 | uint32_t num_interrupts; | |
278 | uint32_t dev_interrupts; | |
279 | uint32_t cin_busy; | |
280 | uint32_t pause_cnt; | |
281 | }; | |
282 | ||
283 | struct crystalhd_hw { | |
abfc768d | 284 | struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; |
7963eb43 JW |
285 | spinlock_t lock; |
286 | ||
287 | uint32_t tx_ioq_tag_seed; | |
288 | uint32_t tx_list_post_index; | |
289 | ||
abfc768d | 290 | struct crystalhd_rx_dma_pkt *rx_pkt_pool_head; |
7963eb43 JW |
291 | uint32_t rx_pkt_tag_seed; |
292 | ||
293 | bool dev_started; | |
294 | void *adp; | |
295 | ||
296 | wait_queue_head_t *pfw_cmd_event; | |
297 | int fwcmd_evt_sts; | |
298 | ||
299 | uint32_t pib_del_Q_addr; | |
300 | uint32_t pib_rel_Q_addr; | |
301 | ||
abfc768d LD |
302 | struct crystalhd_dioq *tx_freeq; |
303 | struct crystalhd_dioq *tx_actq; | |
7963eb43 JW |
304 | |
305 | /* Rx DMA Engine Specific Locks */ | |
306 | spinlock_t rx_lock; | |
307 | uint32_t rx_list_post_index; | |
abfc768d LD |
308 | enum list_sts rx_list_sts[DMA_ENGINE_CNT]; |
309 | struct crystalhd_dioq *rx_rdyq; | |
310 | struct crystalhd_dioq *rx_freeq; | |
311 | struct crystalhd_dioq *rx_actq; | |
7963eb43 JW |
312 | uint32_t stop_pending; |
313 | ||
314 | /* HW counters.. */ | |
315 | struct crystalhd_hw_stats stats; | |
316 | ||
317 | /* Core clock in MHz */ | |
318 | uint32_t core_clock_mhz; | |
319 | uint32_t prev_n; | |
320 | uint32_t pwr_lock; | |
321 | }; | |
322 | ||
323 | /* Clock defines for power control */ | |
324 | #define CLOCK_PRESET 175 | |
325 | ||
326 | /* DMA engine register BIT mask wrappers.. */ | |
327 | #define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK | |
328 | ||
329 | #define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ | |
330 | INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ | |
331 | INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ | |
332 | INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ | |
333 | INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ | |
334 | INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ | |
335 | INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ | |
336 | INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) | |
337 | ||
338 | #define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ | |
339 | MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ | |
340 | MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ | |
341 | MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) | |
342 | ||
343 | #define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ | |
344 | MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ | |
345 | MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ | |
346 | MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) | |
347 | ||
348 | #define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ | |
349 | MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ | |
350 | MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ | |
351 | MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) | |
352 | ||
353 | #define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ | |
354 | MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ | |
355 | MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ | |
356 | MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) | |
357 | ||
358 | ||
359 | /**** API Exposed to the other layers ****/ | |
abfc768d | 360 | enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, |
7963eb43 | 361 | void *buffer, uint32_t sz); |
abfc768d | 362 | enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd); |
7963eb43 | 363 | bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw); |
abfc768d LD |
364 | enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *); |
365 | enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *); | |
366 | enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *); | |
367 | enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *); | |
7963eb43 JW |
368 | |
369 | ||
abfc768d | 370 | enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, |
7963eb43 JW |
371 | hw_comp_callback call_back, |
372 | wait_queue_head_t *cb_event, | |
373 | uint32_t *list_id, uint8_t data_flags); | |
374 | ||
abfc768d LD |
375 | enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw); |
376 | enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw); | |
377 | enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); | |
378 | enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); | |
379 | enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, | |
380 | struct crystalhd_dio_req *ioreq, bool en_post); | |
381 | enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, | |
382 | struct BC_PIC_INFO_BLOCK *pib, | |
383 | struct crystalhd_dio_req **ioreq); | |
384 | enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw); | |
385 | enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); | |
7963eb43 JW |
386 | void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); |
387 | ||
388 | /* API to program the core clock on the decoder */ | |
abfc768d | 389 | enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *); |
7963eb43 JW |
390 | |
391 | #endif |