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11e865c1 GP |
1 | /* |
2 | comedi/drivers/s626.h | |
3 | Sensoray s626 Comedi driver, header file | |
4 | ||
5 | COMEDI - Linux Control and Measurement Device Interface | |
6 | Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | ||
8 | Based on Sensoray Model 626 Linux driver Version 0.2 | |
9 | Copyright (C) 2002-2004 Sensoray Co., Inc. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | ||
25 | */ | |
26 | ||
27 | /* | |
28 | Driver: s626.o (s626.ko) | |
29 | Description: Sensoray 626 driver | |
30 | Devices: Sensoray s626 | |
31 | Authors: Gianluca Palli <gpalli@deis.unibo.it>, | |
32 | Updated: Thu, 12 Jul 2005 | |
33 | Status: experimental | |
34 | ||
35 | Configuration Options: | |
36 | analog input: | |
37 | none | |
38 | ||
39 | analog output: | |
40 | none | |
41 | ||
42 | digital channel: | |
43 | s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels | |
44 | supported configuration options: | |
45 | INSN_CONFIG_DIO_QUERY | |
46 | COMEDI_INPUT | |
47 | COMEDI_OUTPUT | |
48 | ||
49 | encoder: | |
50 | Every channel must be configured before reading. | |
51 | ||
52 | Example code | |
53 | ||
b6c77757 BP |
54 | insn.insn=INSN_CONFIG; // configuration instruction |
55 | insn.n=1; // number of operation (must be 1) | |
56 | insn.data=&initialvalue; // initial value loaded into encoder | |
57 | // during configuration | |
58 | insn.subdev=5; // encoder subdevice | |
59 | insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); // encoder_channel | |
60 | // to configure | |
61 | ||
62 | comedi_do_insn(cf,&insn); // executing configuration | |
11e865c1 GP |
63 | */ |
64 | ||
65 | #ifdef _DEBUG_ | |
5f74ea14 | 66 | #define DEBUG(...); printk(__VA_ARGS__); |
11e865c1 GP |
67 | #else |
68 | #define DEBUG(...) | |
69 | #endif | |
70 | ||
71 | #if !defined(TRUE) | |
72 | #define TRUE (1) | |
73 | #endif | |
74 | ||
75 | #if !defined(FALSE) | |
76 | #define FALSE (0) | |
77 | #endif | |
78 | ||
11e865c1 GP |
79 | #if !defined(INLINE) |
80 | #define INLINE static __inline | |
81 | #endif | |
82 | ||
11e865c1 GP |
83 | #include<linux/slab.h> |
84 | ||
85 | #define S626_SIZE 0x0200 | |
86 | #define SIZEOF_ADDRESS_SPACE 0x0200 | |
b6c77757 | 87 | #define DMABUF_SIZE 4096 /* 4k pages */ |
11e865c1 GP |
88 | |
89 | #define S626_ADC_CHANNELS 16 | |
90 | #define S626_DAC_CHANNELS 4 | |
91 | #define S626_ENCODER_CHANNELS 6 | |
92 | #define S626_DIO_CHANNELS 48 | |
b6c77757 BP |
93 | #define S626_DIO_BANKS 3 /* Number of DIO groups. */ |
94 | #define S626_DIO_EXTCHANS 40 /* Number of */ | |
95 | /* extended-capability */ | |
96 | /* DIO channels. */ | |
11e865c1 | 97 | |
b6c77757 | 98 | #define NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ |
11e865c1 | 99 | |
b6c77757 BP |
100 | /* PCI bus interface types. */ |
101 | #define INTEL 1 /* Intel bus type. */ | |
102 | #define MOTOROLA 2 /* Motorola bus type. */ | |
11e865c1 | 103 | |
b6c77757 | 104 | #define PLATFORM INTEL /* *** SELECT PLATFORM TYPE *** */ |
11e865c1 | 105 | |
b6c77757 BP |
106 | #define RANGE_5V 0x10 /* +/-5V range */ |
107 | #define RANGE_10V 0x00 /* +/-10V range */ | |
11e865c1 | 108 | |
b6c77757 BP |
109 | #define EOPL 0x80 /* End of ADC poll list marker. */ |
110 | #define GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar range. */ | |
111 | #define GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar range. */ | |
11e865c1 | 112 | |
b6c77757 BP |
113 | /* Error codes that must be visible to this base class. */ |
114 | #define ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter value was specified. */ | |
115 | #define ERR_I2C 0x00020000 /* I2C error. */ | |
116 | #define ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for counter channel. */ | |
117 | #define ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ | |
11e865c1 | 118 | |
b6c77757 BP |
119 | /* Organization (physical order) and size (in DWORDs) of logical DMA buffers contained by ANA_DMABUF. */ |
120 | #define ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, plus pre/post garbage samples. */ | |
121 | #define DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single sample. */ | |
11e865c1 | 122 | |
b6c77757 | 123 | /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ |
11e865c1 | 124 | |
b6c77757 | 125 | /* Address offsets, in DWORDS, from base of DMA buffer. */ |
11e865c1 GP |
126 | #define DAC_WDMABUF_OS ADC_DMABUF_DWORDS |
127 | ||
b6c77757 | 128 | /* Interrupt enab bit in ISR and IER. */ |
0a85b6f0 | 129 | #define IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ |
11e865c1 | 130 | #define IRQ_RPS1 0x10000000 |
b6c77757 BP |
131 | #define ISR_AFOU 0x00000800 |
132 | /* Audio fifo under/overflow detected. */ | |
133 | ||
0a85b6f0 MT |
134 | #define IRQ_COINT1A 0x0400 /* conter 1A overflow interrupt mask */ |
135 | #define IRQ_COINT1B 0x0800 /* conter 1B overflow interrupt mask */ | |
136 | #define IRQ_COINT2A 0x1000 /* conter 2A overflow interrupt mask */ | |
137 | #define IRQ_COINT2B 0x2000 /* conter 2B overflow interrupt mask */ | |
138 | #define IRQ_COINT3A 0x4000 /* conter 3A overflow interrupt mask */ | |
139 | #define IRQ_COINT3B 0x8000 /* conter 3B overflow interrupt mask */ | |
b6c77757 BP |
140 | |
141 | /* RPS command codes. */ | |
142 | #define RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ | |
143 | #define RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ | |
144 | #define RPS_NOP 0x00000000 /* NOP */ | |
145 | #define RPS_PAUSE 0x20000000 /* PAUSE */ | |
146 | #define RPS_UPLOAD 0x40000000 /* UPLOAD */ | |
147 | #define RPS_JUMP 0x80000000 /* JUMP */ | |
148 | #define RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ | |
149 | #define RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ | |
150 | #define RPS_STOP 0x50000000 /* STOP */ | |
151 | #define RPS_IRQ 0x60000000 /* IRQ */ | |
152 | ||
153 | #define RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ | |
154 | #define RPS_INVERT 0x04000000 /* Test for negated semaphores. */ | |
155 | #define RPS_DEBI 0x00000002 /* DEBI done */ | |
156 | ||
157 | #define RPS_SIG0 0x00200000 /* RPS semaphore 0 (used by ADC). */ | |
158 | #define RPS_SIG1 0x00400000 /* RPS semaphore 1 (used by DAC). */ | |
159 | #define RPS_SIG2 0x00800000 /* RPS semaphore 2 (not used). */ | |
160 | #define RPS_GPIO2 0x00080000 /* RPS GPIO2 */ | |
161 | #define RPS_GPIO3 0x00100000 /* RPS GPIO3 */ | |
162 | ||
163 | #define RPS_SIGADC RPS_SIG0 /* Trigger/status for ADC's RPS program. */ | |
164 | #define RPS_SIGDAC RPS_SIG1 /* Trigger/status for DAC's RPS program. */ | |
165 | ||
166 | /* RPS clock parameters. */ | |
167 | #define RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */ | |
6a98d36e | 168 | #define RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */ |
b6c77757 BP |
169 | |
170 | /* Event counter source addresses. */ | |
171 | #define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ | |
172 | ||
173 | /* GPIO constants. */ | |
174 | #define GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out. */ | |
175 | #define GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ | |
176 | #define GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ | |
177 | ||
178 | /* Primary Status Register (PSR) constants. */ | |
179 | #define PSR_DEBI_E 0x00040000 /* DEBI event flag. */ | |
180 | #define PSR_DEBI_S 0x00080000 /* DEBI status flag. */ | |
181 | #define PSR_A2_IN 0x00008000 /* Audio output DMA2 protection address reached. */ | |
182 | #define PSR_AFOU 0x00000800 /* Audio FIFO under/overflow detected. */ | |
183 | #define PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 1=AdcIdle. */ | |
184 | #define PSR_EC0S 0x00000001 /* Event counter 0 threshold reached. */ | |
185 | ||
186 | /* Secondary Status Register (SSR) constants. */ | |
187 | #define SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO under/overflow detected. */ | |
188 | ||
189 | /* Master Control Register 1 (MC1) constants. */ | |
190 | #define MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ | |
191 | #define MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled enables. */ | |
192 | ||
193 | #define MC1_ERPS1 0x2000 /* enab/disable RPS task 1. */ | |
194 | #define MC1_ERPS0 0x1000 /* enab/disable RPS task 0. */ | |
195 | #define MC1_DEBI 0x0800 /* enab/disable DEBI pins. */ | |
196 | #define MC1_AUDIO 0x0200 /* enab/disable audio port pins. */ | |
197 | #define MC1_I2C 0x0100 /* enab/disable I2C interface. */ | |
198 | #define MC1_A2OUT 0x0008 /* enab/disable transfer on A2 out. */ | |
199 | #define MC1_A2IN 0x0004 /* enab/disable transfer on A2 in. */ | |
200 | #define MC1_A1IN 0x0001 /* enab/disable transfer on A1 in. */ | |
201 | ||
202 | /* Master Control Register 2 (MC2) constants. */ | |
203 | #define MC2_UPLD_DEBIq 0x00020002 /* Upload DEBI registers. */ | |
204 | #define MC2_UPLD_IICq 0x00010001 /* Upload I2C registers. */ | |
205 | #define MC2_RPSSIG2_ONq 0x20002000 /* Assert RPS_SIG2. */ | |
206 | #define MC2_RPSSIG1_ONq 0x10001000 /* Assert RPS_SIG1. */ | |
207 | #define MC2_RPSSIG0_ONq 0x08000800 /* Assert RPS_SIG0. */ | |
208 | #define MC2_UPLD_DEBI_MASKq 0x00000002 /* Upload DEBI mask. */ | |
209 | #define MC2_UPLD_IIC_MASKq 0x00000001 /* Upload I2C mask. */ | |
210 | #define MC2_RPSSIG2_MASKq 0x00002000 /* RPS_SIG2 bit mask. */ | |
211 | #define MC2_RPSSIG1_MASKq 0x00001000 /* RPS_SIG1 bit mask. */ | |
212 | #define MC2_RPSSIG0_MASKq 0x00000800 /* RPS_SIG0 bit mask. */ | |
11e865c1 GP |
213 | |
214 | #define MC2_DELAYTRIG_4USq MC2_RPSSIG1_ON | |
215 | #define MC2_DELAYBUSY_4USq MC2_RPSSIG1_MASK | |
216 | ||
217 | #define MC2_DELAYTRIG_6USq MC2_RPSSIG2_ON | |
218 | #define MC2_DELAYBUSY_6USq MC2_RPSSIG2_MASK | |
219 | ||
b6c77757 BP |
220 | #define MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ |
221 | #define MC2_UPLD_IIC 0x0001 /* Upload I2C. */ | |
222 | #define MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ | |
223 | #define MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ | |
224 | #define MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ | |
225 | ||
226 | #define MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */ | |
227 | #define MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */ | |
228 | ||
229 | /* ***** oldies ***** */ | |
230 | #define MC2_UPLD_DEBIQ 0x00020002 /* Upload DEBI registers. */ | |
231 | #define MC2_UPLD_IICQ 0x00010001 /* Upload I2C registers. */ | |
232 | ||
233 | /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ | |
234 | #define P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ | |
235 | #define P_DEBICFG 0x007C /* DEBI configuration. */ | |
236 | #define P_DEBICMD 0x0080 /* DEBI command. */ | |
237 | #define P_DEBIPAGE 0x0084 /* DEBI page. */ | |
238 | #define P_DEBIAD 0x0088 /* DEBI target address. */ | |
239 | #define P_I2CCTRL 0x008C /* I2C control. */ | |
240 | #define P_I2CSTAT 0x0090 /* I2C status. */ | |
241 | #define P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf | |
242 | * address. */ | |
243 | #define P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf | |
244 | * protection address. */ | |
245 | #define P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ | |
246 | #define P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf | |
247 | * address. */ | |
248 | #define P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf | |
249 | * protection address. */ | |
250 | #define P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ | |
251 | #define P_RPSPAGE0 0x00C4 /* RPS0 page. */ | |
252 | #define P_RPSPAGE1 0x00C8 /* RPS1 page. */ | |
253 | #define P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ | |
254 | #define P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ | |
255 | #define P_IER 0x00DC /* Interrupt enable. */ | |
256 | #define P_GPIO 0x00E0 /* General-purpose I/O. */ | |
257 | #define P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ | |
258 | #define P_ECT1R 0x00EC /* Event counter threshold set 1. */ | |
259 | #define P_ACON1 0x00F4 /* Audio control 1. */ | |
260 | #define P_ACON2 0x00F8 /* Audio control 2. */ | |
261 | #define P_MC1 0x00FC /* Master control 1. */ | |
262 | #define P_MC2 0x0100 /* Master control 2. */ | |
263 | #define P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ | |
264 | #define P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ | |
265 | #define P_ISR 0x010C /* Interrupt status. */ | |
266 | #define P_PSR 0x0110 /* Primary status. */ | |
267 | #define P_SSR 0x0114 /* Secondary status. */ | |
268 | #define P_EC1R 0x0118 /* Event counter set 1. */ | |
269 | #define P_ADP4 0x0138 /* Logical audio DMA pointer of audio | |
270 | * input FIFO A2_IN. */ | |
271 | #define P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ | |
272 | #define P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ | |
273 | #define P_TSL1 0x0180 /* Audio time slot list 1. */ | |
274 | #define P_TSL2 0x01C0 /* Audio time slot list 2. */ | |
275 | ||
276 | /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ | |
277 | /* Analog I/O registers: */ | |
278 | #define LP_DACPOL 0x0082 /* Write DAC polarity. */ | |
279 | #define LP_GSEL 0x0084 /* Write ADC gain. */ | |
280 | #define LP_ISEL 0x0086 /* Write ADC channel select. */ | |
281 | /* Digital I/O (write only): */ | |
282 | #define LP_WRINTSELA 0x0042 /* Write A interrupt enable. */ | |
283 | #define LP_WREDGSELA 0x0044 /* Write A edge selection. */ | |
284 | #define LP_WRCAPSELA 0x0046 /* Write A capture enable. */ | |
285 | #define LP_WRDOUTA 0x0048 /* Write A digital output. */ | |
286 | #define LP_WRINTSELB 0x0052 /* Write B interrupt enable. */ | |
287 | #define LP_WREDGSELB 0x0054 /* Write B edge selection. */ | |
288 | #define LP_WRCAPSELB 0x0056 /* Write B capture enable. */ | |
289 | #define LP_WRDOUTB 0x0058 /* Write B digital output. */ | |
290 | #define LP_WRINTSELC 0x0062 /* Write C interrupt enable. */ | |
291 | #define LP_WREDGSELC 0x0064 /* Write C edge selection. */ | |
292 | #define LP_WRCAPSELC 0x0066 /* Write C capture enable. */ | |
293 | #define LP_WRDOUTC 0x0068 /* Write C digital output. */ | |
294 | ||
295 | /* Digital I/O (read only): */ | |
296 | #define LP_RDDINA 0x0040 /* Read digital input. */ | |
297 | #define LP_RDCAPFLGA 0x0048 /* Read edges captured. */ | |
298 | #define LP_RDINTSELA 0x004A /* Read interrupt enable register. */ | |
299 | #define LP_RDEDGSELA 0x004C /* Read edge selection register. */ | |
300 | #define LP_RDCAPSELA 0x004E /* Read capture enable register. */ | |
301 | #define LP_RDDINB 0x0050 /* Read digital input. */ | |
302 | #define LP_RDCAPFLGB 0x0058 /* Read edges captured. */ | |
303 | #define LP_RDINTSELB 0x005A /* Read interrupt enable register. */ | |
304 | #define LP_RDEDGSELB 0x005C /* Read edge selection register. */ | |
305 | #define LP_RDCAPSELB 0x005E /* Read capture enable register. */ | |
306 | #define LP_RDDINC 0x0060 /* Read digital input. */ | |
307 | #define LP_RDCAPFLGC 0x0068 /* Read edges captured. */ | |
308 | #define LP_RDINTSELC 0x006A /* Read interrupt enable register. */ | |
309 | #define LP_RDEDGSELC 0x006C /* Read edge selection register. */ | |
310 | #define LP_RDCAPSELC 0x006E /* Read capture enable register. */ | |
311 | ||
312 | /* Counter Registers (read/write): */ | |
313 | #define LP_CR0A 0x0000 /* 0A setup register. */ | |
314 | #define LP_CR0B 0x0002 /* 0B setup register. */ | |
315 | #define LP_CR1A 0x0004 /* 1A setup register. */ | |
316 | #define LP_CR1B 0x0006 /* 1B setup register. */ | |
317 | #define LP_CR2A 0x0008 /* 2A setup register. */ | |
318 | #define LP_CR2B 0x000A /* 2B setup register. */ | |
319 | ||
320 | /* Counter PreLoad (write) and Latch (read) Registers: */ | |
321 | #define LP_CNTR0ALSW 0x000C /* 0A lsw. */ | |
322 | #define LP_CNTR0AMSW 0x000E /* 0A msw. */ | |
323 | #define LP_CNTR0BLSW 0x0010 /* 0B lsw. */ | |
324 | #define LP_CNTR0BMSW 0x0012 /* 0B msw. */ | |
325 | #define LP_CNTR1ALSW 0x0014 /* 1A lsw. */ | |
326 | #define LP_CNTR1AMSW 0x0016 /* 1A msw. */ | |
327 | #define LP_CNTR1BLSW 0x0018 /* 1B lsw. */ | |
328 | #define LP_CNTR1BMSW 0x001A /* 1B msw. */ | |
329 | #define LP_CNTR2ALSW 0x001C /* 2A lsw. */ | |
330 | #define LP_CNTR2AMSW 0x001E /* 2A msw. */ | |
331 | #define LP_CNTR2BLSW 0x0020 /* 2B lsw. */ | |
332 | #define LP_CNTR2BMSW 0x0022 /* 2B msw. */ | |
333 | ||
334 | /* Miscellaneous Registers (read/write): */ | |
335 | #define LP_MISC1 0x0088 /* Read/write Misc1. */ | |
336 | #define LP_WRMISC2 0x0090 /* Write Misc2. */ | |
337 | #define LP_RDMISC2 0x0082 /* Read Misc2. */ | |
338 | ||
339 | /* Bit masks for MISC1 register that are the same for reads and writes. */ | |
340 | #define MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear | |
341 | * Watchdog bit). */ | |
342 | #define MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ | |
343 | #define MISC1_EDCAP 0x1000 /* enab edge capture on DIO chans | |
344 | * specified by LP_WRCAPSELx. */ | |
345 | #define MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified | |
346 | * DIO chans. */ | |
347 | ||
348 | /* Bit masks for MISC1 register reads. */ | |
349 | #define RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ | |
350 | ||
351 | /* Bit masks for MISC2 register writes. */ | |
352 | #define WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ | |
353 | #define WRMISC2_CHARGE_ENABLE 0x4000 /* enab battery trickle charging. */ | |
354 | ||
355 | /* Bit masks for MISC2 register that are the same for reads and writes. */ | |
356 | #define MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ | |
357 | #define MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ | |
358 | #define MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval */ | |
359 | /* select mask. */ | |
360 | ||
361 | /* Bit masks for ACON1 register. */ | |
362 | #define A2_RUN 0x40000000 /* Run A2 based on TSL2. */ | |
363 | #define A1_RUN 0x20000000 /* Run A1 based on TSL1. */ | |
364 | #define A1_SWAP 0x00200000 /* Use big-endian for A1. */ | |
365 | #define A2_SWAP 0x00100000 /* Use big-endian for A2. */ | |
366 | #define WS_MODES 0x00019999 /* WS0 = TSL1 trigger */ | |
367 | /* input, WS1-WS4 = */ | |
368 | /* CS* outputs. */ | |
369 | ||
370 | #if PLATFORM == INTEL /* Base ACON1 config: always run A1 based | |
371 | * on TSL1. */ | |
6a98d36e | 372 | #define ACON1_BASE (WS_MODES | A1_RUN) |
11e865c1 | 373 | #elif PLATFORM == MOTOROLA |
6a98d36e | 374 | #define ACON1_BASE (WS_MODES | A1_RUN | A1_SWAP | A2_SWAP) |
11e865c1 GP |
375 | #endif |
376 | ||
b6c77757 BP |
377 | #define ACON1_ADCSTART ACON1_BASE /* Start ADC: run A1 |
378 | * based on TSL1. */ | |
6a98d36e | 379 | #define ACON1_DACSTART (ACON1_BASE | A2_RUN) |
b6c77757 BP |
380 | /* Start transmit to DAC: run A2 based on TSL2. */ |
381 | #define ACON1_DACSTOP ACON1_BASE /* Halt A2. */ | |
382 | ||
383 | /* Bit masks for ACON2 register. */ | |
384 | #define A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ | |
385 | #define A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 (DACs). */ | |
386 | #define A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 (DACs). */ | |
387 | #define A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 (DACs). */ | |
388 | #define INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ | |
389 | #define BCLK2_OE 0x00040000 /* enab BCLK2 (DACs). */ | |
390 | #define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */ | |
391 | /* active-low bits. */ | |
11e865c1 | 392 | |
6a98d36e | 393 | #define ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE)) |
11e865c1 | 394 | |
b6c77757 BP |
395 | /* Bit masks for timeslot records. */ |
396 | #define WS1 0x40000000 /* WS output to assert. */ | |
11e865c1 GP |
397 | #define WS2 0x20000000 |
398 | #define WS3 0x10000000 | |
399 | #define WS4 0x08000000 | |
b6c77757 BP |
400 | #define RSD1 0x01000000 /* Shift A1 data in on SD1. */ |
401 | #define SDW_A1 0x00800000 /* Store rcv'd char at next | |
402 | * char slot of DWORD1 buffer. */ | |
403 | #define SIB_A1 0x00400000 /* Store rcv'd char at next | |
404 | * char slot of FB1 buffer. */ | |
405 | #define SF_A1 0x00200000 /* Write unsigned long | |
406 | * buffer to input FIFO. */ | |
407 | ||
408 | /* Select parallel-to-serial converter's data source: */ | |
409 | #define XFIFO_0 0x00000000 /* Data fifo byte 0. */ | |
410 | #define XFIFO_1 0x00000010 /* Data fifo byte 1. */ | |
411 | #define XFIFO_2 0x00000020 /* Data fifo byte 2. */ | |
412 | #define XFIFO_3 0x00000030 /* Data fifo byte 3. */ | |
413 | #define XFB0 0x00000040 /* FB_BUFFER byte 0. */ | |
414 | #define XFB1 0x00000050 /* FB_BUFFER byte 1. */ | |
415 | #define XFB2 0x00000060 /* FB_BUFFER byte 2. */ | |
416 | #define XFB3 0x00000070 /* FB_BUFFER byte 3. */ | |
417 | #define SIB_A2 0x00000200 /* Store next dword from A2's | |
418 | * input shifter to FB2 buffer. */ | |
419 | #define SF_A2 0x00000100 /* Store next dword from A2's | |
420 | * input shifter to its input | |
421 | * fifo. */ | |
422 | #define LF_A2 0x00000080 /* Load next dword from A2's | |
423 | * output fifo into its | |
424 | * output dword buffer. */ | |
425 | #define XSD2 0x00000008 /* Shift data out on SD2. */ | |
426 | #define RSD3 0x00001800 /* Shift data in on SD3. */ | |
427 | #define RSD2 0x00001000 /* Shift data in on SD2. */ | |
428 | #define LOW_A2 0x00000002 /* Drive last SD low */ | |
429 | /* for 7 clks, then */ | |
430 | /* tri-state. */ | |
431 | #define EOS 0x00000001 /* End of superframe. */ | |
432 | ||
b6c77757 BP |
433 | /* I2C configuration constants. */ |
434 | #define I2C_CLKSEL 0x0400 | |
435 | /* I2C bit rate = PCIclk/480 = 68.75 KHz. */ | |
436 | ||
437 | #define I2C_BITRATE 68.75 | |
438 | /* I2C bus data bit rate (determined by I2C_CLKSEL) in KHz. */ | |
439 | ||
440 | #define I2C_WRTIME 15.0 | |
441 | /* Worst case time, in msec, for EEPROM internal write op. */ | |
442 | ||
443 | /* I2C manifest constants. */ | |
444 | ||
445 | /* Max retries to wait for EEPROM write. */ | |
6a98d36e | 446 | #define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0) |
b6c77757 BP |
447 | #define I2C_ERR 0x0002 /* I2C control/status */ |
448 | /* flag ERROR. */ | |
449 | #define I2C_BUSY 0x0001 /* I2C control/status */ | |
450 | /* flag BUSY. */ | |
451 | #define I2C_ABORT 0x0080 /* I2C status flag ABORT. */ | |
452 | #define I2C_ATTRSTART 0x3 /* I2C attribute START. */ | |
453 | #define I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ | |
454 | #define I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ | |
455 | #define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ | |
456 | ||
457 | /* I2C read command | EEPROM address. */ | |
6a98d36e | 458 | #define I2CR (devpriv->I2CAdrs | 1) |
11e865c1 | 459 | |
b6c77757 | 460 | /* I2C write command | EEPROM address. */ |
6a98d36e | 461 | #define I2CW (devpriv->I2CAdrs) |
11e865c1 | 462 | |
b6c77757 | 463 | /* Code macros used for constructing I2C command bytes. */ |
6a98d36e BP |
464 | #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) |
465 | #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) | |
466 | #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) | |
11e865c1 | 467 | |
b6c77757 BP |
468 | /* oldest */ |
469 | #define P_DEBICFGq 0x007C /* DEBI configuration. */ | |
470 | #define P_DEBICMDq 0x0080 /* DEBI command. */ | |
471 | #define P_DEBIPAGEq 0x0084 /* DEBI page. */ | |
472 | #define P_DEBIADq 0x0088 /* DEBI target address. */ | |
473 | ||
474 | #define DEBI_CFG_TOQ 0x03C00000 /* timeout (15 PCI cycles) */ | |
475 | #define DEBI_CFG_FASTQ 0x10000000 /* fast mode enable */ | |
476 | #define DEBI_CFG_16Q 0x00080000 /* 16-bit access enable */ | |
477 | #define DEBI_CFG_INCQ 0x00040000 /* enable address increment */ | |
478 | #define DEBI_CFG_TIMEROFFQ 0x00010000 /* disable timer */ | |
479 | #define DEBI_CMD_RDQ 0x00050000 /* read immediate 2 bytes */ | |
480 | #define DEBI_CMD_WRQ 0x00040000 /* write immediate 2 bytes */ | |
481 | #define DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */ | |
482 | ||
483 | /* DEBI command constants. */ | |
6a98d36e | 484 | #define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */ |
b6c77757 BP |
485 | /* always 2 bytes. */ |
486 | #define DEBI_CMD_READ 0x00010000 /* Read operation. */ | |
487 | #define DEBI_CMD_WRITE 0x00000000 /* Write operation. */ | |
488 | ||
489 | /* Read immediate 2 bytes. */ | |
6a98d36e | 490 | #define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16) |
11e865c1 | 491 | |
b6c77757 | 492 | /* Write immediate 2 bytes. */ |
6a98d36e | 493 | #define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16) |
11e865c1 | 494 | |
b6c77757 BP |
495 | /* DEBI configuration constants. */ |
496 | #define DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */ | |
497 | /* interrupt on GPIO3. */ | |
498 | #define DEBI_CFG_XRESUME 0x40000000 /* Resume block */ | |
499 | /* transfer when XIRQ */ | |
500 | /* deasserted. */ | |
501 | #define DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ | |
502 | ||
503 | /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ | |
504 | #define DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after */ | |
505 | /* this many clocks. */ | |
506 | ||
507 | /* 2-bit field that specifies Endian byte lane steering: */ | |
508 | #define DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't */ | |
509 | /* swap any bytes */ | |
510 | /* (Intel). */ | |
511 | #define DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ | |
512 | #define DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ | |
513 | #define DEBI_CFG_16 0x00080000 /* Slave is able to */ | |
514 | /* serve 16-bit */ | |
515 | /* cycles. */ | |
516 | ||
517 | #define DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to */ | |
518 | /* serve 16-bit */ | |
519 | /* cycles. */ | |
520 | #define DEBI_CFG_INC 0x00040000 /* enab address */ | |
521 | /* increment for block */ | |
522 | /* transfers. */ | |
523 | #define DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ | |
524 | #define DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ | |
11e865c1 GP |
525 | |
526 | #if PLATFORM == INTEL | |
527 | ||
b6c77757 BP |
528 | #define DEBI_TOUT 7 /* Wait 7 PCI clocks */ |
529 | /* (212 ns) before */ | |
530 | /* polling RDY. */ | |
11e865c1 | 531 | |
b6c77757 | 532 | /* Intel byte lane steering (pass through all byte lanes). */ |
11e865c1 GP |
533 | #define DEBI_SWAP DEBI_CFG_SWAP_NONE |
534 | ||
535 | #elif PLATFORM == MOTOROLA | |
536 | ||
b6c77757 BP |
537 | #define DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) */ |
538 | /* maximum before timing out. */ | |
539 | #define DEBI_SWAP DEBI_CFG_SWAP_2 /* Motorola byte lane steering. */ | |
11e865c1 GP |
540 | |
541 | #endif | |
542 | ||
b6c77757 BP |
543 | /* DEBI page table constants. */ |
544 | #define DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ | |
545 | ||
546 | /* ******* EXTRA FROM OTHER SANSORAY * .h ******* */ | |
547 | ||
548 | /* LoadSrc values: */ | |
549 | #define LOADSRC_INDX 0 /* Preload core in response to */ | |
550 | /* Index. */ | |
551 | #define LOADSRC_OVER 1 /* Preload core in response to */ | |
552 | /* Overflow. */ | |
553 | #define LOADSRCB_OVERA 2 /* Preload B core in response */ | |
554 | /* to A Overflow. */ | |
555 | #define LOADSRC_NONE 3 /* Never preload core. */ | |
556 | ||
557 | /* IntSrc values: */ | |
558 | #define INTSRC_NONE 0 /* Interrupts disabled. */ | |
559 | #define INTSRC_OVER 1 /* Interrupt on Overflow. */ | |
560 | #define INTSRC_INDX 2 /* Interrupt on Index. */ | |
561 | #define INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ | |
562 | ||
563 | /* LatchSrc values: */ | |
564 | #define LATCHSRC_AB_READ 0 /* Latch on read. */ | |
565 | #define LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ | |
566 | #define LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ | |
567 | #define LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ | |
568 | ||
569 | /* IndxSrc values: */ | |
570 | #define INDXSRC_HARD 0 /* Hardware or software index. */ | |
571 | #define INDXSRC_SOFT 1 /* Software index only. */ | |
572 | ||
573 | /* IndxPol values: */ | |
574 | #define INDXPOL_POS 0 /* Index input is active high. */ | |
575 | #define INDXPOL_NEG 1 /* Index input is active low. */ | |
576 | ||
577 | /* ClkSrc values: */ | |
578 | #define CLKSRC_COUNTER 0 /* Counter mode. */ | |
579 | #define CLKSRC_TIMER 2 /* Timer mode. */ | |
580 | #define CLKSRC_EXTENDER 3 /* Extender mode. */ | |
581 | ||
582 | /* ClkPol values: */ | |
583 | #define CLKPOL_POS 0 /* Counter/Extender clock is */ | |
584 | /* active high. */ | |
585 | #define CLKPOL_NEG 1 /* Counter/Extender clock is */ | |
586 | /* active low. */ | |
587 | #define CNTDIR_UP 0 /* Timer counts up. */ | |
588 | #define CNTDIR_DOWN 1 /* Timer counts down. */ | |
589 | ||
590 | /* ClkEnab values: */ | |
591 | #define CLKENAB_ALWAYS 0 /* Clock always enabled. */ | |
592 | #define CLKENAB_INDEX 1 /* Clock is enabled by index. */ | |
593 | ||
594 | /* ClkMult values: */ | |
595 | #define CLKMULT_4X 0 /* 4x clock multiplier. */ | |
596 | #define CLKMULT_2X 1 /* 2x clock multiplier. */ | |
597 | #define CLKMULT_1X 2 /* 1x clock multiplier. */ | |
598 | ||
599 | /* Bit Field positions in COUNTER_SETUP structure: */ | |
600 | #define BF_LOADSRC 9 /* Preload trigger. */ | |
601 | #define BF_INDXSRC 7 /* Index source. */ | |
602 | #define BF_INDXPOL 6 /* Index polarity. */ | |
603 | #define BF_CLKSRC 4 /* Clock source. */ | |
604 | #define BF_CLKPOL 3 /* Clock polarity/count direction. */ | |
605 | #define BF_CLKMULT 1 /* Clock multiplier. */ | |
606 | #define BF_CLKENAB 0 /* Clock enable. */ | |
607 | ||
608 | /* Enumerated counter operating modes specified by ClkSrc bit field in */ | |
609 | /* a COUNTER_SETUP. */ | |
610 | ||
611 | #define CLKSRC_COUNTER 0 /* Counter: ENC_C clock, ENC_D */ | |
612 | /* direction. */ | |
613 | #define CLKSRC_TIMER 2 /* Timer: SYS_C clock, */ | |
614 | /* direction specified by */ | |
615 | /* ClkPol. */ | |
616 | #define CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, */ | |
617 | /* ENC_D direction. */ | |
618 | ||
619 | /* Enumerated counter clock multipliers. */ | |
620 | ||
621 | #define MULT_X0 0x0003 /* Supports no multipliers; */ | |
622 | /* fixed physical multiplier = */ | |
623 | /* 3. */ | |
624 | #define MULT_X1 0x0002 /* Supports multiplier x1; */ | |
625 | /* fixed physical multiplier = */ | |
626 | /* 2. */ | |
627 | #define MULT_X2 0x0001 /* Supports multipliers x1, */ | |
628 | /* x2; physical multipliers = */ | |
629 | /* 1 or 2. */ | |
630 | #define MULT_X4 0x0000 /* Supports multipliers x1, */ | |
631 | /* x2, x4; physical */ | |
632 | /* multipliers = 0, 1 or 2. */ | |
633 | ||
634 | /* Sanity-check limits for parameters. */ | |
635 | ||
636 | #define NUM_COUNTERS 6 /* Maximum valid counter */ | |
637 | /* logical channel number. */ | |
11e865c1 GP |
638 | #define NUM_INTSOURCES 4 |
639 | #define NUM_LATCHSOURCES 4 | |
640 | #define NUM_CLKMULTS 4 | |
641 | #define NUM_CLKSOURCES 4 | |
642 | #define NUM_CLKPOLS 2 | |
643 | #define NUM_INDEXPOLS 2 | |
644 | #define NUM_INDEXSOURCES 2 | |
645 | #define NUM_LOADTRIGS 4 | |
646 | ||
b6c77757 BP |
647 | /* Bit field positions in CRA and CRB counter control registers. */ |
648 | ||
649 | /* Bit field positions in CRA: */ | |
650 | #define CRABIT_INDXSRC_B 14 /* B index source. */ | |
651 | #define CRABIT_CLKSRC_B 12 /* B clock source. */ | |
652 | #define CRABIT_INDXPOL_A 11 /* A index polarity. */ | |
653 | #define CRABIT_LOADSRC_A 9 /* A preload trigger. */ | |
654 | #define CRABIT_CLKMULT_A 7 /* A clock multiplier. */ | |
655 | #define CRABIT_INTSRC_A 5 /* A interrupt source. */ | |
656 | #define CRABIT_CLKPOL_A 4 /* A clock polarity. */ | |
657 | #define CRABIT_INDXSRC_A 2 /* A index source. */ | |
658 | #define CRABIT_CLKSRC_A 0 /* A clock source. */ | |
659 | ||
660 | /* Bit field positions in CRB: */ | |
661 | #define CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */ | |
662 | #define CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */ | |
663 | #define CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */ | |
664 | #define CRBBIT_CLKENAB_A 12 /* A clock enable. */ | |
665 | #define CRBBIT_INTSRC_B 10 /* B interrupt source. */ | |
666 | #define CRBBIT_LATCHSRC 8 /* A/B latch source. */ | |
667 | #define CRBBIT_LOADSRC_B 6 /* B preload trigger. */ | |
668 | #define CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ | |
669 | #define CRBBIT_CLKENAB_B 2 /* B clock enable. */ | |
670 | #define CRBBIT_INDXPOL_B 1 /* B index polarity. */ | |
671 | #define CRBBIT_CLKPOL_B 0 /* B clock polarity. */ | |
672 | ||
673 | /* Bit field masks for CRA and CRB. */ | |
11e865c1 | 674 | |
6a98d36e BP |
675 | #define CRAMSK_INDXSRC_B ((uint16_t)(3 << CRABIT_INDXSRC_B)) |
676 | #define CRAMSK_CLKSRC_B ((uint16_t)(3 << CRABIT_CLKSRC_B)) | |
677 | #define CRAMSK_INDXPOL_A ((uint16_t)(1 << CRABIT_INDXPOL_A)) | |
678 | #define CRAMSK_LOADSRC_A ((uint16_t)(3 << CRABIT_LOADSRC_A)) | |
679 | #define CRAMSK_CLKMULT_A ((uint16_t)(3 << CRABIT_CLKMULT_A)) | |
680 | #define CRAMSK_INTSRC_A ((uint16_t)(3 << CRABIT_INTSRC_A)) | |
681 | #define CRAMSK_CLKPOL_A ((uint16_t)(3 << CRABIT_CLKPOL_A)) | |
682 | #define CRAMSK_INDXSRC_A ((uint16_t)(3 << CRABIT_INDXSRC_A)) | |
683 | #define CRAMSK_CLKSRC_A ((uint16_t)(3 << CRABIT_CLKSRC_A)) | |
684 | ||
685 | #define CRBMSK_INTRESETCMD ((uint16_t)(1 << CRBBIT_INTRESETCMD)) | |
686 | #define CRBMSK_INTRESET_B ((uint16_t)(1 << CRBBIT_INTRESET_B)) | |
687 | #define CRBMSK_INTRESET_A ((uint16_t)(1 << CRBBIT_INTRESET_A)) | |
688 | #define CRBMSK_CLKENAB_A ((uint16_t)(1 << CRBBIT_CLKENAB_A)) | |
689 | #define CRBMSK_INTSRC_B ((uint16_t)(3 << CRBBIT_INTSRC_B)) | |
690 | #define CRBMSK_LATCHSRC ((uint16_t)(3 << CRBBIT_LATCHSRC)) | |
691 | #define CRBMSK_LOADSRC_B ((uint16_t)(3 << CRBBIT_LOADSRC_B)) | |
692 | #define CRBMSK_CLKMULT_B ((uint16_t)(3 << CRBBIT_CLKMULT_B)) | |
693 | #define CRBMSK_CLKENAB_B ((uint16_t)(1 << CRBBIT_CLKENAB_B)) | |
694 | #define CRBMSK_INDXPOL_B ((uint16_t)(1 << CRBBIT_INDXPOL_B)) | |
695 | #define CRBMSK_CLKPOL_B ((uint16_t)(1 << CRBBIT_CLKPOL_B)) | |
696 | ||
697 | #define CRBMSK_INTCTRL (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) /* Interrupt reset control bits. */ | |
11e865c1 | 698 | |
b6c77757 | 699 | /* Bit field positions for standardized SETUP structure. */ |
11e865c1 GP |
700 | |
701 | #define STDBIT_INTSRC 13 | |
702 | #define STDBIT_LATCHSRC 11 | |
703 | #define STDBIT_LOADSRC 9 | |
704 | #define STDBIT_INDXSRC 7 | |
705 | #define STDBIT_INDXPOL 6 | |
706 | #define STDBIT_CLKSRC 4 | |
707 | #define STDBIT_CLKPOL 3 | |
708 | #define STDBIT_CLKMULT 1 | |
709 | #define STDBIT_CLKENAB 0 | |
710 | ||
b6c77757 | 711 | /* Bit field masks for standardized SETUP structure. */ |
11e865c1 | 712 | |
6a98d36e BP |
713 | #define STDMSK_INTSRC ((uint16_t)(3 << STDBIT_INTSRC)) |
714 | #define STDMSK_LATCHSRC ((uint16_t)(3 << STDBIT_LATCHSRC)) | |
715 | #define STDMSK_LOADSRC ((uint16_t)(3 << STDBIT_LOADSRC)) | |
716 | #define STDMSK_INDXSRC ((uint16_t)(1 << STDBIT_INDXSRC)) | |
717 | #define STDMSK_INDXPOL ((uint16_t)(1 << STDBIT_INDXPOL)) | |
718 | #define STDMSK_CLKSRC ((uint16_t)(3 << STDBIT_CLKSRC)) | |
719 | #define STDMSK_CLKPOL ((uint16_t)(1 << STDBIT_CLKPOL)) | |
720 | #define STDMSK_CLKMULT ((uint16_t)(3 << STDBIT_CLKMULT)) | |
721 | #define STDMSK_CLKENAB ((uint16_t)(1 << STDBIT_CLKENAB)) | |
11e865c1 | 722 | |
4753d235 | 723 | struct bufferDMA { |
11e865c1 GP |
724 | dma_addr_t PhysicalBase; |
725 | void *LogicalBase; | |
726 | uint32_t DMAHandle; | |
4753d235 | 727 | }; |