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3d9f0739 DC |
1 | /* |
2 | comedi/drivers/rtd520.h | |
3 | Comedi driver defines for Real Time Devices (RTD) PCI4520/DM7520 | |
4 | ||
5 | COMEDI - Linux Control and Measurement Device Interface | |
6 | Copyright (C) 2001 David A. Schleef <ds@schleef.org> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | Created by Dan Christian, NASA Ames Research Center. | |
25 | See board notes in rtd520.c | |
26 | */ | |
27 | ||
28 | /* | |
29 | LAS0 Runtime Area | |
30 | Local Address Space 0 Offset Read Function Write Function | |
31 | */ | |
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32 | #define LAS0_SPARE_00 0x0000 /* - - */ |
33 | #define LAS0_SPARE_04 0x0004 /* - - */ | |
34 | #define LAS0_USER_IO 0x0008 /* Read User Inputs Write User Outputs */ | |
35 | #define LAS0_SPARE_0C 0x000C /* - - */ | |
36 | #define LAS0_ADC 0x0010 /* Read FIFO Status Software A/D Start */ | |
37 | #define LAS0_DAC1 0x0014 /* - Software D/A1 Update */ | |
38 | #define LAS0_DAC2 0x0018 /* - Software D/A2 Update */ | |
39 | #define LAS0_SPARE_1C 0x001C /* - - */ | |
40 | #define LAS0_SPARE_20 0x0020 /* - - */ | |
41 | #define LAS0_DAC 0x0024 /* - Software Simultaneous D/A1 and D/A2 Update */ | |
42 | #define LAS0_PACER 0x0028 /* Software Pacer Start Software Pacer Stop */ | |
43 | #define LAS0_TIMER 0x002C /* Read Timer Counters Status HDIN Software Trigger */ | |
44 | #define LAS0_IT 0x0030 /* Read Interrupt Status Write Interrupt Enable Mask Register */ | |
45 | #define LAS0_CLEAR 0x0034 /* Clear ITs set by Clear Mask Set Interrupt Clear Mask */ | |
46 | #define LAS0_OVERRUN 0x0038 /* Read pending interrupts Clear Overrun Register */ | |
47 | #define LAS0_SPARE_3C 0x003C /* - - */ | |
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48 | |
49 | /* | |
50 | LAS0 Runtime Area Timer/Counter,Dig.IO | |
51 | Name Local Address Function | |
52 | */ | |
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53 | #define LAS0_PCLK 0x0040 /* Pacer Clock value (24bit) Pacer Clock load (24bit) */ |
54 | #define LAS0_BCLK 0x0044 /* Burst Clock value (10bit) Burst Clock load (10bit) */ | |
55 | #define LAS0_ADC_SCNT 0x0048 /* A/D Sample counter value (10bit) A/D Sample counter load (10bit) */ | |
56 | #define LAS0_DAC1_UCNT 0x004C /* D/A1 Update counter value (10 bit) D/A1 Update counter load (10bit) */ | |
57 | #define LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter value (10 bit) D/A2 Update counter load (10bit) */ | |
58 | #define LAS0_DCNT 0x0054 /* Delay counter value (16 bit) Delay counter load (16bit) */ | |
59 | #define LAS0_ACNT 0x0058 /* About counter value (16 bit) About counter load (16bit) */ | |
60 | #define LAS0_DAC_CLK 0x005C /* DAC clock value (16bit) DAC clock load (16bit) */ | |
61 | #define LAS0_UTC0 0x0060 /* 8254 TC Counter 0 User TC 0 value Load count in TC Counter 0 */ | |
62 | #define LAS0_UTC1 0x0064 /* 8254 TC Counter 1 User TC 1 value Load count in TC Counter 1 */ | |
63 | #define LAS0_UTC2 0x0068 /* 8254 TC Counter 2 User TC 2 value Load count in TC Counter 2 */ | |
64 | #define LAS0_UTC_CTRL 0x006C /* 8254 TC Control Word Program counter mode for TC */ | |
65 | #define LAS0_DIO0 0x0070 /* Digital I/O Port 0 Read Port Digital I/O Port 0 Write Port */ | |
66 | #define LAS0_DIO1 0x0074 /* Digital I/O Port 1 Read Port Digital I/O Port 1 Write Port */ | |
67 | #define LAS0_DIO0_CTRL 0x0078 /* Clear digital IRQ status flag/read Clear digital chip/program Port 0 */ | |
68 | #define LAS0_DIO_STATUS 0x007C /* Read Digital I/O Status word Program digital control register & */ | |
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69 | |
70 | /* | |
71 | LAS0 Setup Area | |
72 | Name Local Address Function | |
73 | */ | |
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74 | #define LAS0_BOARD_RESET 0x0100 /* Board reset */ |
75 | #define LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */ | |
76 | #define LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */ | |
77 | #define LAS0_ADC_CONVERSION 0x010C /* A/D Conversion Signal select */ | |
78 | #define LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */ | |
79 | #define LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */ | |
80 | #define LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */ | |
81 | #define LAS0_ACNT_STOP_ENABLE 0x011C /* About Counter Stop Enable */ | |
82 | #define LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */ | |
83 | #define LAS0_DIN_START 0x0124 /* High Speed Digital Input Sampling Signal select */ | |
84 | #define LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */ | |
85 | #define LAS0_ADC_FIFO_CLEAR 0x012C /* A/D FIFO Clear */ | |
86 | #define LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */ | |
87 | #define LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */ | |
88 | #define LAS0_CG_DATA 0x0138 /* Digital Table Write */ | |
89 | #define LAS0_CGT_ENABLE 0x013C /* Channel Gain Table Enable */ | |
90 | #define LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */ | |
91 | #define LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */ | |
92 | #define LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */ | |
93 | #define LAS0_CGT_CLEAR 0x014C /* Clear Channel Gain Table */ | |
94 | #define LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */ | |
95 | #define LAS0_DAC1_SRC 0x0154 /* D/A1 update source */ | |
96 | #define LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */ | |
97 | #define LAS0_DAC1_RESET 0x015C /* D/A1 FIFO reset */ | |
98 | #define LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */ | |
99 | #define LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */ | |
100 | #define LAS0_DAC2_SRC 0x0168 /* D/A2 update source */ | |
101 | #define LAS0_DAC2_CYCLE 0x016C /* D/A2 cycle mode */ | |
102 | #define LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */ | |
103 | #define LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */ | |
104 | #define LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */ | |
105 | #define LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */ | |
106 | #define LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */ | |
107 | #define LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */ | |
108 | #define LAS0_SBUS1_SRC 0x018C /* SyncBus 1 Source select */ | |
109 | #define LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */ | |
110 | #define LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */ | |
111 | #define LAS0_SBUS2_ENABLE 0x019C /* SyncBus 2 enable */ | |
112 | #define LAS0_ETRG_POLARITY 0x01A4 /* External Trigger polarity select */ | |
113 | #define LAS0_EINT_POLARITY 0x01A8 /* External Interrupt polarity select */ | |
114 | #define LAS0_UTC0_CLOCK 0x01AC /* UTC0 Clock select */ | |
115 | #define LAS0_UTC0_GATE 0x01B0 /* UTC0 Gate select */ | |
116 | #define LAS0_UTC1_CLOCK 0x01B4 /* UTC1 Clock select */ | |
117 | #define LAS0_UTC1_GATE 0x01B8 /* UTC1 Gate select */ | |
118 | #define LAS0_UTC2_CLOCK 0x01BC /* UTC2 Clock select */ | |
119 | #define LAS0_UTC2_GATE 0x01C0 /* UTC2 Gate select */ | |
120 | #define LAS0_UOUT0_SELECT 0x01C4 /* User Output 0 source select */ | |
121 | #define LAS0_UOUT1_SELECT 0x01C8 /* User Output 1 source select */ | |
122 | #define LAS0_DMA0_RESET 0x01CC /* DMA0 Request state machine reset */ | |
123 | #define LAS0_DMA1_RESET 0x01D0 /* DMA1 Request state machine reset */ | |
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124 | |
125 | /* | |
126 | LAS1 | |
127 | Name Local Address Function | |
128 | */ | |
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129 | #define LAS1_ADC_FIFO 0x0000 /* Read A/D FIFO (16bit) - */ |
130 | #define LAS1_HDIO_FIFO 0x0004 /* Read High Speed Digital Input FIFO (16bit) - */ | |
131 | #define LAS1_DAC1_FIFO 0x0008 /* - Write D/A1 FIFO (16bit) */ | |
132 | #define LAS1_DAC2_FIFO 0x000C /* - Write D/A2 FIFO (16bit) */ | |
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133 | |
134 | /* | |
135 | LCFG: PLX 9080 local config & runtime registers | |
136 | Name Local Address Function | |
137 | */ | |
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138 | #define LCFG_ITCSR 0x0068 /* INTCSR, Interrupt Control/Status Register */ |
139 | #define LCFG_DMAMODE0 0x0080 /* DMA Channel 0 Mode Register */ | |
140 | #define LCFG_DMAPADR0 0x0084 /* DMA Channel 0 PCI Address Register */ | |
141 | #define LCFG_DMALADR0 0x0088 /* DMA Channel 0 Local Address Reg */ | |
142 | #define LCFG_DMASIZ0 0x008C /* DMA Channel 0 Transfer Size (Bytes) Register */ | |
143 | #define LCFG_DMADPR0 0x0090 /* DMA Channel 0 Descriptor Pointer Register */ | |
144 | #define LCFG_DMAMODE1 0x0094 /* DMA Channel 1 Mode Register */ | |
145 | #define LCFG_DMAPADR1 0x0098 /* DMA Channel 1 PCI Address Register */ | |
146 | #define LCFG_DMALADR1 0x009C /* DMA Channel 1 Local Address Register */ | |
147 | #define LCFG_DMASIZ1 0x00A0 /* DMA Channel 1 Transfer Size (Bytes) Register */ | |
148 | #define LCFG_DMADPR1 0x00A4 /* DMA Channel 1 Descriptor Pointer Register */ | |
149 | #define LCFG_DMACSR0 0x00A8 /* DMA Channel 0 Command/Status Register */ | |
150 | #define LCFG_DMACSR1 0x00A9 /* DMA Channel 0 Command/Status Register */ | |
151 | #define LCFG_DMAARB 0x00AC /* DMA Arbitration Register */ | |
152 | #define LCFG_DMATHR 0x00B0 /* DMA Threshold Register */ | |
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153 | |
154 | /*====================================================================== | |
155 | Resister bit definitions | |
156 | ======================================================================*/ | |
157 | ||
b6c77757 BP |
158 | /* FIFO Status Word Bits (RtdFifoStatus) */ |
159 | #define FS_DAC1_NOT_EMPTY 0x0001 /* D0 - DAC1 FIFO not empty */ | |
160 | #define FS_DAC1_HEMPTY 0x0002 /* D1 - DAC1 FIFO half empty */ | |
161 | #define FS_DAC1_NOT_FULL 0x0004 /* D2 - DAC1 FIFO not full */ | |
162 | #define FS_DAC2_NOT_EMPTY 0x0010 /* D4 - DAC2 FIFO not empty */ | |
163 | #define FS_DAC2_HEMPTY 0x0020 /* D5 - DAC2 FIFO half empty */ | |
164 | #define FS_DAC2_NOT_FULL 0x0040 /* D6 - DAC2 FIFO not full */ | |
165 | #define FS_ADC_NOT_EMPTY 0x0100 /* D8 - ADC FIFO not empty */ | |
166 | #define FS_ADC_HEMPTY 0x0200 /* D9 - ADC FIFO half empty */ | |
167 | #define FS_ADC_NOT_FULL 0x0400 /* D10 - ADC FIFO not full */ | |
168 | #define FS_DIN_NOT_EMPTY 0x1000 /* D12 - DIN FIFO not empty */ | |
169 | #define FS_DIN_HEMPTY 0x2000 /* D13 - DIN FIFO half empty */ | |
170 | #define FS_DIN_NOT_FULL 0x4000 /* D14 - DIN FIFO not full */ | |
171 | ||
172 | /* Timer Status Word Bits (GetTimerStatus) */ | |
3d9f0739 | 173 | #define TS_PCLK_GATE 0x0001 |
b6c77757 | 174 | /* D0 - Pacer Clock Gate [0 - gated, 1 - enabled] */ |
3d9f0739 | 175 | #define TS_BCLK_GATE 0x0002 |
b6c77757 | 176 | /* D1 - Burst Clock Gate [0 - disabled, 1 - running] */ |
3d9f0739 | 177 | #define TS_DCNT_GATE 0x0004 |
b6c77757 BP |
178 | /* D2 - Pacer Clock Delayed Start Trigger [0 - delay over, 1 - delay in */ |
179 | /* progress] */ | |
3d9f0739 | 180 | #define TS_ACNT_GATE 0x0008 |
b6c77757 | 181 | /* D3 - Pacer Clock About Trigger [0 - completed, 1 - in progress] */ |
3d9f0739 | 182 | #define TS_PCLK_RUN 0x0010 |
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183 | /* D4 - Pacer Clock Shutdown Flag [0 - Pacer Clock cannot be start */ |
184 | /* triggered only by Software Pacer Start Command, 1 - Pacer Clock can */ | |
185 | /* be start triggered] */ | |
186 | ||
187 | /* External Trigger polarity select */ | |
188 | /* External Interrupt polarity select */ | |
189 | #define POL_POSITIVE 0x0 /* positive edge */ | |
190 | #define POL_NEGATIVE 0x1 /* negative edge */ | |
191 | ||
192 | /* User Output Signal select (SetUout0Source, SetUout1Source) */ | |
193 | #define UOUT_ADC 0x0 /* A/D Conversion Signal */ | |
194 | #define UOUT_DAC1 0x1 /* D/A1 Update */ | |
195 | #define UOUT_DAC2 0x2 /* D/A2 Update */ | |
196 | #define UOUT_SOFTWARE 0x3 /* Software Programmable */ | |
197 | ||
198 | /* Pacer clock select (SetPacerSource) */ | |
199 | #define PCLK_INTERNAL 1 /* Internal Pacer Clock */ | |
200 | #define PCLK_EXTERNAL 0 /* External Pacer Clock */ | |
201 | ||
202 | /* A/D Sample Counter Sources (SetAdcntSource, SetupSampleCounter) */ | |
203 | #define ADC_SCNT_CGT_RESET 0x0 /* needs restart with StartPacer */ | |
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204 | #define ADC_SCNT_FIFO_WRITE 0x1 |
205 | ||
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206 | /* A/D Conversion Signal Select (for SetConversionSelect) */ |
207 | #define ADC_START_SOFTWARE 0x0 /* Software A/D Start */ | |
208 | #define ADC_START_PCLK 0x1 /* Pacer Clock (Ext. Int. see Func.509) */ | |
209 | #define ADC_START_BCLK 0x2 /* Burst Clock */ | |
210 | #define ADC_START_DIGITAL_IT 0x3 /* Digital Interrupt */ | |
211 | #define ADC_START_DAC1_MARKER1 0x4 /* D/A 1 Data Marker 1 */ | |
212 | #define ADC_START_DAC2_MARKER1 0x5 /* D/A 2 Data Marker 1 */ | |
213 | #define ADC_START_SBUS0 0x6 /* SyncBus 0 */ | |
214 | #define ADC_START_SBUS1 0x7 /* SyncBus 1 */ | |
215 | #define ADC_START_SBUS2 0x8 /* SyncBus 2 */ | |
216 | ||
217 | /* Burst Clock start trigger select (SetBurstStart) */ | |
218 | #define BCLK_START_SOFTWARE 0x0 /* Software A/D Start (StartBurst) */ | |
219 | #define BCLK_START_PCLK 0x1 /* Pacer Clock */ | |
220 | #define BCLK_START_ETRIG 0x2 /* External Trigger */ | |
221 | #define BCLK_START_DIGITAL_IT 0x3 /* Digital Interrupt */ | |
222 | #define BCLK_START_SBUS0 0x4 /* SyncBus 0 */ | |
223 | #define BCLK_START_SBUS1 0x5 /* SyncBus 1 */ | |
224 | #define BCLK_START_SBUS2 0x6 /* SyncBus 2 */ | |
225 | ||
226 | /* Pacer Clock start trigger select (SetPacerStart) */ | |
227 | #define PCLK_START_SOFTWARE 0x0 /* Software Pacer Start (StartPacer) */ | |
228 | #define PCLK_START_ETRIG 0x1 /* External trigger */ | |
229 | #define PCLK_START_DIGITAL_IT 0x2 /* Digital interrupt */ | |
230 | #define PCLK_START_UTC2 0x3 /* User TC 2 out */ | |
231 | #define PCLK_START_SBUS0 0x4 /* SyncBus 0 */ | |
232 | #define PCLK_START_SBUS1 0x5 /* SyncBus 1 */ | |
233 | #define PCLK_START_SBUS2 0x6 /* SyncBus 2 */ | |
234 | #define PCLK_START_D_SOFTWARE 0x8 /* Delayed Software Pacer Start */ | |
235 | #define PCLK_START_D_ETRIG 0x9 /* Delayed external trigger */ | |
236 | #define PCLK_START_D_DIGITAL_IT 0xA /* Delayed digital interrupt */ | |
237 | #define PCLK_START_D_UTC2 0xB /* Delayed User TC 2 out */ | |
238 | #define PCLK_START_D_SBUS0 0xC /* Delayed SyncBus 0 */ | |
239 | #define PCLK_START_D_SBUS1 0xD /* Delayed SyncBus 1 */ | |
240 | #define PCLK_START_D_SBUS2 0xE /* Delayed SyncBus 2 */ | |
241 | #define PCLK_START_ETRIG_GATED 0xF /* External Trigger Gated controlled mode */ | |
242 | ||
243 | /* Pacer Clock Stop Trigger select (SetPacerStop) */ | |
244 | #define PCLK_STOP_SOFTWARE 0x0 /* Software Pacer Stop (StopPacer) */ | |
245 | #define PCLK_STOP_ETRIG 0x1 /* External Trigger */ | |
246 | #define PCLK_STOP_DIGITAL_IT 0x2 /* Digital Interrupt */ | |
247 | #define PCLK_STOP_ACNT 0x3 /* About Counter */ | |
248 | #define PCLK_STOP_UTC2 0x4 /* User TC2 out */ | |
249 | #define PCLK_STOP_SBUS0 0x5 /* SyncBus 0 */ | |
250 | #define PCLK_STOP_SBUS1 0x6 /* SyncBus 1 */ | |
251 | #define PCLK_STOP_SBUS2 0x7 /* SyncBus 2 */ | |
252 | #define PCLK_STOP_A_SOFTWARE 0x8 /* About Software Pacer Stop */ | |
253 | #define PCLK_STOP_A_ETRIG 0x9 /* About External Trigger */ | |
254 | #define PCLK_STOP_A_DIGITAL_IT 0xA /* About Digital Interrupt */ | |
255 | #define PCLK_STOP_A_UTC2 0xC /* About User TC2 out */ | |
256 | #define PCLK_STOP_A_SBUS0 0xD /* About SyncBus 0 */ | |
257 | #define PCLK_STOP_A_SBUS1 0xE /* About SyncBus 1 */ | |
258 | #define PCLK_STOP_A_SBUS2 0xF /* About SyncBus 2 */ | |
259 | ||
260 | /* About Counter Stop Enable */ | |
261 | #define ACNT_STOP 0x0 /* stop enable */ | |
262 | #define ACNT_NO_STOP 0x1 /* stop disabled */ | |
263 | ||
264 | /* DAC update source (SetDAC1Start & SetDAC2Start) */ | |
265 | #define DAC_START_SOFTWARE 0x0 /* Software Update */ | |
266 | #define DAC_START_CGT 0x1 /* CGT controlled Update */ | |
267 | #define DAC_START_DAC_CLK 0x2 /* D/A Clock */ | |
268 | #define DAC_START_EPCLK 0x3 /* External Pacer Clock */ | |
269 | #define DAC_START_SBUS0 0x4 /* SyncBus 0 */ | |
270 | #define DAC_START_SBUS1 0x5 /* SyncBus 1 */ | |
271 | #define DAC_START_SBUS2 0x6 /* SyncBus 2 */ | |
272 | ||
273 | /* DAC Cycle Mode (SetDAC1Cycle, SetDAC2Cycle, SetupDAC) */ | |
274 | #define DAC_CYCLE_SINGLE 0x0 /* not cycle */ | |
275 | #define DAC_CYCLE_MULTI 0x1 /* cycle */ | |
276 | ||
277 | /* 8254 Operation Modes (Set8254Mode, SetupTimerCounter) */ | |
278 | #define M8254_EVENT_COUNTER 0 /* Event Counter */ | |
279 | #define M8254_HW_ONE_SHOT 1 /* Hardware-Retriggerable One-Shot */ | |
280 | #define M8254_RATE_GENERATOR 2 /* Rate Generator */ | |
281 | #define M8254_SQUARE_WAVE 3 /* Square Wave Mode */ | |
282 | #define M8254_SW_STROBE 4 /* Software Triggered Strobe */ | |
283 | #define M8254_HW_STROBE 5 /* Hardware Triggered Strobe (Retriggerable) */ | |
284 | ||
285 | /* User Timer/Counter 0 Clock Select (SetUtc0Clock) */ | |
286 | #define CUTC0_8MHZ 0x0 /* 8MHz */ | |
287 | #define CUTC0_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */ | |
288 | #define CUTC0_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */ | |
289 | #define CUTC0_EXT_PCLK 0x3 /* Ext. Pacer Clock */ | |
290 | ||
291 | /* User Timer/Counter 1 Clock Select (SetUtc1Clock) */ | |
292 | #define CUTC1_8MHZ 0x0 /* 8MHz */ | |
293 | #define CUTC1_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */ | |
294 | #define CUTC1_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */ | |
295 | #define CUTC1_EXT_PCLK 0x3 /* Ext. Pacer Clock */ | |
296 | #define CUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */ | |
297 | #define CUTC1_DIN_SIGNAL 0x5 /* High-Speed Digital Input Sampling signal */ | |
298 | ||
299 | /* User Timer/Counter 2 Clock Select (SetUtc2Clock) */ | |
300 | #define CUTC2_8MHZ 0x0 /* 8MHz */ | |
301 | #define CUTC2_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */ | |
302 | #define CUTC2_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */ | |
303 | #define CUTC2_EXT_PCLK 0x3 /* Ext. Pacer Clock */ | |
304 | #define CUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */ | |
305 | ||
306 | /* User Timer/Counter 0 Gate Select (SetUtc0Gate) */ | |
307 | #define GUTC0_NOT_GATED 0x0 /* Not gated */ | |
308 | #define GUTC0_GATED 0x1 /* Gated */ | |
309 | #define GUTC0_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */ | |
310 | #define GUTC0_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */ | |
311 | ||
312 | /* User Timer/Counter 1 Gate Select (SetUtc1Gate) */ | |
313 | #define GUTC1_NOT_GATED 0x0 /* Not gated */ | |
314 | #define GUTC1_GATED 0x1 /* Gated */ | |
315 | #define GUTC1_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */ | |
316 | #define GUTC1_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */ | |
317 | #define GUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */ | |
318 | ||
319 | /* User Timer/Counter 2 Gate Select (SetUtc2Gate) */ | |
320 | #define GUTC2_NOT_GATED 0x0 /* Not gated */ | |
321 | #define GUTC2_GATED 0x1 /* Gated */ | |
322 | #define GUTC2_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */ | |
323 | #define GUTC2_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */ | |
324 | #define GUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */ | |
325 | ||
326 | /* Interrupt Source Masks (SetITMask, ClearITMask, GetITStatus) */ | |
327 | #define IRQM_ADC_FIFO_WRITE 0x0001 /* ADC FIFO Write */ | |
328 | #define IRQM_CGT_RESET 0x0002 /* Reset CGT */ | |
329 | #define IRQM_CGT_PAUSE 0x0008 /* Pause CGT */ | |
330 | #define IRQM_ADC_ABOUT_CNT 0x0010 /* About Counter out */ | |
331 | #define IRQM_ADC_DELAY_CNT 0x0020 /* Delay Counter out */ | |
332 | #define IRQM_ADC_SAMPLE_CNT 0x0040 /* ADC Sample Counter */ | |
333 | #define IRQM_DAC1_UCNT 0x0080 /* DAC1 Update Counter */ | |
334 | #define IRQM_DAC2_UCNT 0x0100 /* DAC2 Update Counter */ | |
335 | #define IRQM_UTC1 0x0200 /* User TC1 out */ | |
336 | #define IRQM_UTC1_INV 0x0400 /* User TC1 out, inverted */ | |
337 | #define IRQM_UTC2 0x0800 /* User TC2 out */ | |
338 | #define IRQM_DIGITAL_IT 0x1000 /* Digital Interrupt */ | |
339 | #define IRQM_EXTERNAL_IT 0x2000 /* External Interrupt */ | |
340 | #define IRQM_ETRIG_RISING 0x4000 /* External Trigger rising-edge */ | |
341 | #define IRQM_ETRIG_FALLING 0x8000 /* External Trigger falling-edge */ | |
342 | ||
343 | /* DMA Request Sources (LAS0) */ | |
344 | #define DMAS_DISABLED 0x0 /* DMA Disabled */ | |
345 | #define DMAS_ADC_SCNT 0x1 /* ADC Sample Counter */ | |
346 | #define DMAS_DAC1_UCNT 0x2 /* D/A1 Update Counter */ | |
347 | #define DMAS_DAC2_UCNT 0x3 /* D/A2 Update Counter */ | |
348 | #define DMAS_UTC1 0x4 /* User TC1 out */ | |
349 | #define DMAS_ADFIFO_HALF_FULL 0x8 /* A/D FIFO half full */ | |
350 | #define DMAS_DAC1_FIFO_HALF_EMPTY 0x9 /* D/A1 FIFO half empty */ | |
351 | #define DMAS_DAC2_FIFO_HALF_EMPTY 0xA /* D/A2 FIFO half empty */ | |
352 | ||
353 | /* DMA Local Addresses (0x40000000+LAS1 offset) */ | |
354 | #define DMALADDR_ADC 0x40000000 /* A/D FIFO */ | |
355 | #define DMALADDR_HDIN 0x40000004 /* High Speed Digital Input FIFO */ | |
356 | #define DMALADDR_DAC1 0x40000008 /* D/A1 FIFO */ | |
357 | #define DMALADDR_DAC2 0x4000000C /* D/A2 FIFO */ | |
358 | ||
359 | /* Port 0 compare modes (SetDIO0CompareMode) */ | |
360 | #define DIO_MODE_EVENT 0 /* Event Mode */ | |
361 | #define DIO_MODE_MATCH 1 /* Match Mode */ | |
362 | ||
363 | /* Digital Table Enable (Port 1 disable) */ | |
364 | #define DTBL_DISABLE 0 /* Enable Digital Table */ | |
365 | #define DTBL_ENABLE 1 /* Disable Digital Table */ | |
366 | ||
367 | /* Sampling Signal for High Speed Digital Input (SetHdinStart) */ | |
368 | #define HDIN_SOFTWARE 0x0 /* Software Trigger */ | |
369 | #define HDIN_ADC 0x1 /* A/D Conversion Signal */ | |
370 | #define HDIN_UTC0 0x2 /* User TC out 0 */ | |
371 | #define HDIN_UTC1 0x3 /* User TC out 1 */ | |
372 | #define HDIN_UTC2 0x4 /* User TC out 2 */ | |
373 | #define HDIN_EPCLK 0x5 /* External Pacer Clock */ | |
374 | #define HDIN_ETRG 0x6 /* External Trigger */ | |
375 | ||
376 | /* Channel Gain Table / Channel Gain Latch */ | |
377 | #define CSC_LATCH 0 /* Channel Gain Latch mode */ | |
378 | #define CSC_CGT 1 /* Channel Gain Table mode */ | |
379 | ||
380 | /* Channel Gain Table Pause Enable */ | |
381 | #define CGT_PAUSE_DISABLE 0 /* Channel Gain Table Pause Disable */ | |
382 | #define CGT_PAUSE_ENABLE 1 /* Channel Gain Table Pause Enable */ | |
383 | ||
384 | /* DAC output type/range (p63) */ | |
385 | #define AOUT_UNIP5 0 /* 0..+5 Volt */ | |
386 | #define AOUT_UNIP10 1 /* 0..+10 Volt */ | |
387 | #define AOUT_BIP5 2 /* -5..+5 Volt */ | |
388 | #define AOUT_BIP10 3 /* -10..+10 Volt */ | |
389 | ||
390 | /* Ghannel Gain Table field definitions (p61) */ | |
391 | /* Gain */ | |
3d9f0739 DC |
392 | #define GAIN1 0 |
393 | #define GAIN2 1 | |
394 | #define GAIN4 2 | |
395 | #define GAIN8 3 | |
396 | #define GAIN16 4 | |
397 | #define GAIN32 5 | |
398 | #define GAIN64 6 | |
399 | #define GAIN128 7 | |
400 | ||
b6c77757 BP |
401 | /* Input range/polarity */ |
402 | #define AIN_BIP5 0 /* -5..+5 Volt */ | |
403 | #define AIN_BIP10 1 /* -10..+10 Volt */ | |
404 | #define AIN_UNIP10 2 /* 0..+10 Volt */ | |
3d9f0739 | 405 | |
b6c77757 BP |
406 | /* non referenced single ended select bit */ |
407 | #define NRSE_AGND 0 /* AGND referenced SE input */ | |
408 | #define NRSE_AINS 1 /* AIN SENSE referenced SE input */ | |
3d9f0739 | 409 | |
b6c77757 BP |
410 | /* single ended vs differential */ |
411 | #define GND_SE 0 /* Single-Ended */ | |
412 | #define GND_DIFF 1 /* Differential */ |