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cb7859a9 FMH |
1 | /* |
2 | drivers/ni_tio.h | |
3 | Header file for NI general purpose counter support code (ni_tio.c) | |
4 | ||
5 | COMEDI - Linux Control and Measurement Device Interface | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | ||
21 | */ | |
22 | ||
23 | #ifndef _COMEDI_NI_TIO_H | |
24 | #define _COMEDI_NI_TIO_H | |
25 | ||
26 | #include "../comedidev.h" | |
27 | ||
2696fb57 | 28 | /* forward declarations */ |
cb7859a9 FMH |
29 | struct mite_struct; |
30 | struct ni_gpct_device; | |
31 | ||
32 | enum ni_gpct_register { | |
33 | NITIO_G0_Autoincrement_Reg, | |
34 | NITIO_G1_Autoincrement_Reg, | |
35 | NITIO_G2_Autoincrement_Reg, | |
36 | NITIO_G3_Autoincrement_Reg, | |
37 | NITIO_G0_Command_Reg, | |
38 | NITIO_G1_Command_Reg, | |
39 | NITIO_G2_Command_Reg, | |
40 | NITIO_G3_Command_Reg, | |
41 | NITIO_G0_HW_Save_Reg, | |
42 | NITIO_G1_HW_Save_Reg, | |
43 | NITIO_G2_HW_Save_Reg, | |
44 | NITIO_G3_HW_Save_Reg, | |
45 | NITIO_G0_SW_Save_Reg, | |
46 | NITIO_G1_SW_Save_Reg, | |
47 | NITIO_G2_SW_Save_Reg, | |
48 | NITIO_G3_SW_Save_Reg, | |
49 | NITIO_G0_Mode_Reg, | |
50 | NITIO_G1_Mode_Reg, | |
51 | NITIO_G2_Mode_Reg, | |
52 | NITIO_G3_Mode_Reg, | |
53 | NITIO_G0_LoadA_Reg, | |
54 | NITIO_G1_LoadA_Reg, | |
55 | NITIO_G2_LoadA_Reg, | |
56 | NITIO_G3_LoadA_Reg, | |
57 | NITIO_G0_LoadB_Reg, | |
58 | NITIO_G1_LoadB_Reg, | |
59 | NITIO_G2_LoadB_Reg, | |
60 | NITIO_G3_LoadB_Reg, | |
61 | NITIO_G0_Input_Select_Reg, | |
62 | NITIO_G1_Input_Select_Reg, | |
63 | NITIO_G2_Input_Select_Reg, | |
64 | NITIO_G3_Input_Select_Reg, | |
65 | NITIO_G0_Counting_Mode_Reg, | |
66 | NITIO_G1_Counting_Mode_Reg, | |
67 | NITIO_G2_Counting_Mode_Reg, | |
68 | NITIO_G3_Counting_Mode_Reg, | |
69 | NITIO_G0_Second_Gate_Reg, | |
70 | NITIO_G1_Second_Gate_Reg, | |
71 | NITIO_G2_Second_Gate_Reg, | |
72 | NITIO_G3_Second_Gate_Reg, | |
73 | NITIO_G01_Status_Reg, | |
74 | NITIO_G23_Status_Reg, | |
75 | NITIO_G01_Joint_Reset_Reg, | |
76 | NITIO_G23_Joint_Reset_Reg, | |
77 | NITIO_G01_Joint_Status1_Reg, | |
78 | NITIO_G23_Joint_Status1_Reg, | |
79 | NITIO_G01_Joint_Status2_Reg, | |
80 | NITIO_G23_Joint_Status2_Reg, | |
81 | NITIO_G0_DMA_Config_Reg, | |
82 | NITIO_G1_DMA_Config_Reg, | |
83 | NITIO_G2_DMA_Config_Reg, | |
84 | NITIO_G3_DMA_Config_Reg, | |
85 | NITIO_G0_DMA_Status_Reg, | |
86 | NITIO_G1_DMA_Status_Reg, | |
87 | NITIO_G2_DMA_Status_Reg, | |
88 | NITIO_G3_DMA_Status_Reg, | |
89 | NITIO_G0_ABZ_Reg, | |
90 | NITIO_G1_ABZ_Reg, | |
91 | NITIO_G0_Interrupt_Acknowledge_Reg, | |
92 | NITIO_G1_Interrupt_Acknowledge_Reg, | |
93 | NITIO_G2_Interrupt_Acknowledge_Reg, | |
94 | NITIO_G3_Interrupt_Acknowledge_Reg, | |
95 | NITIO_G0_Status_Reg, | |
96 | NITIO_G1_Status_Reg, | |
97 | NITIO_G2_Status_Reg, | |
98 | NITIO_G3_Status_Reg, | |
99 | NITIO_G0_Interrupt_Enable_Reg, | |
100 | NITIO_G1_Interrupt_Enable_Reg, | |
101 | NITIO_G2_Interrupt_Enable_Reg, | |
102 | NITIO_G3_Interrupt_Enable_Reg, | |
103 | NITIO_Num_Registers, | |
104 | }; | |
105 | ||
106 | enum ni_gpct_variant { | |
107 | ni_gpct_variant_e_series, | |
108 | ni_gpct_variant_m_series, | |
109 | ni_gpct_variant_660x | |
110 | }; | |
111 | ||
112 | struct ni_gpct { | |
113 | struct ni_gpct_device *counter_dev; | |
114 | unsigned counter_index; | |
115 | unsigned chip_index; | |
116 | uint64_t clock_period_ps; /* clock period in picoseconds */ | |
117 | struct mite_channel *mite_chan; | |
118 | spinlock_t lock; | |
119 | }; | |
120 | ||
121 | struct ni_gpct_device { | |
71b5f4f1 | 122 | struct comedi_device *dev; |
0a85b6f0 MT |
123 | void (*write_register) (struct ni_gpct * counter, unsigned bits, |
124 | enum ni_gpct_register reg); | |
125 | unsigned (*read_register) (struct ni_gpct * counter, | |
126 | enum ni_gpct_register reg); | |
cb7859a9 FMH |
127 | enum ni_gpct_variant variant; |
128 | struct ni_gpct *counters; | |
129 | unsigned num_counters; | |
130 | unsigned regs[NITIO_Num_Registers]; | |
131 | spinlock_t regs_lock; | |
132 | }; | |
133 | ||
0a85b6f0 MT |
134 | extern struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device |
135 | *dev, | |
136 | void (*write_register) | |
137 | (struct ni_gpct * | |
138 | counter, unsigned bits, | |
139 | enum ni_gpct_register | |
140 | reg), | |
141 | unsigned (*read_register) | |
142 | (struct ni_gpct * | |
143 | counter, | |
144 | enum ni_gpct_register | |
145 | reg), | |
146 | enum ni_gpct_variant | |
147 | variant, | |
148 | unsigned num_counters); | |
cb7859a9 FMH |
149 | extern void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev); |
150 | extern void ni_tio_init_counter(struct ni_gpct *counter); | |
151 | extern int ni_tio_rinsn(struct ni_gpct *counter, | |
0a85b6f0 | 152 | struct comedi_insn *insn, unsigned int *data); |
cb7859a9 | 153 | extern int ni_tio_insn_config(struct ni_gpct *counter, |
0a85b6f0 | 154 | struct comedi_insn *insn, unsigned int *data); |
cb7859a9 | 155 | extern int ni_tio_winsn(struct ni_gpct *counter, |
0a85b6f0 | 156 | struct comedi_insn *insn, unsigned int *data); |
d163679c | 157 | extern int ni_tio_cmd(struct ni_gpct *counter, struct comedi_async *async); |
0a85b6f0 | 158 | extern int ni_tio_cmdtest(struct ni_gpct *counter, struct comedi_cmd *cmd); |
cb7859a9 FMH |
159 | extern int ni_tio_cancel(struct ni_gpct *counter); |
160 | extern void ni_tio_handle_interrupt(struct ni_gpct *counter, | |
0a85b6f0 | 161 | struct comedi_subdevice *s); |
cb7859a9 | 162 | extern void ni_tio_set_mite_channel(struct ni_gpct *counter, |
0a85b6f0 | 163 | struct mite_channel *mite_chan); |
cb7859a9 | 164 | extern void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, |
0a85b6f0 MT |
165 | int *gate_error, int *tc_error, |
166 | int *perm_stale_data, | |
167 | int *stale_data); | |
cb7859a9 | 168 | |
0a85b6f0 | 169 | static inline struct ni_gpct *subdev_to_counter(struct comedi_subdevice *s) |
cb7859a9 FMH |
170 | { |
171 | return s->private; | |
172 | } | |
173 | ||
174 | #endif /* _COMEDI_NI_TIO_H */ |