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Staging: comedi: Remove comedi_devconfig typedef
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_pcimio.c
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c4beb34e
DS		 1/*
2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22/*
23Driver: ni_pcimio
24Description: National Instruments PCI-MIO-E series and M series (all boards)
25Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
27Status: works
28Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
51e290fd
IA		 32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225,
33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
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DS		 34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
38 PCI-6143, PXI-6143
51e290fd 39Updated: Wed, 03 Dec 2008 10:51:47 +0000
c4beb34e
DS		 40
41These boards are almost identical to the AT-MIO E series, except that
42they use the PCI bus instead of ISA (i.e., AT). See the notes for
43the ni_atmio.o driver for additional information about these boards.
44
45Autocalibration is supported on many of the devices, using the
46comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47M-Series boards do analog input and analog output calibration entirely
48in software. The software calibration corrects
49the analog input for offset, gain and
50nonlinearity. The analog outputs are corrected for offset and gain.
51See the comedilib documentation on comedi_get_softcal_converter() for
52more information.
53
54By default, the driver uses DMA to transfer analog input data to
55memory. When DMA is enabled, not all triggering features are
56supported.
57
58Digital I/O may not work on 673x.
59
60Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61With this board all of the convertors perform one simultaineous sample during
62a scan interval. The period for a scan is used for the convert time in a
63Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
64
65The RTSI trigger bus is supported on these cards on
66subdevice 10. See the comedilib documentation for details.
67
68Information (number of channels, bits, etc.) for some devices may be
69incorrect. Please check this and submit a bug if there are problems
70for your device.
71
72SCXI is probably broken for m-series boards.
73
74Bugs:
75 - When DMA is enabled, COMEDI_EV_CONVERT does
76 not work correctly.
77
78*/
79/*
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
82
83 References:
84
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
87
88 322080b.pdf 6711/6713/6715 User Manual
89
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92
93 ISSUES:
94
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
97
98 deal with at-mio-16de-10 revision D to N changes, etc.
99
100 need to add other CALDAC type
101
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use comedi_udelay(). Timing specs: (clock)
105 AD8522 30ns
106 DAC8043 120ns
107 DAC8800 60ns
108 MB88341 ?
109
110*/
111
112#include "../comedidev.h"
113
f8db88ef 114#include <asm/byteorder.h>
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DS		 115#include <linux/delay.h>
116
117#include "ni_stc.h"
118#include "mite.h"
119
120//#define PCI_DEBUG
121
122#define PCIDMA
123
124#define PCIMIO 1
125#undef ATMIO
126
127#define MAX_N_CALDACS (16+16+2)
128
129#define DRV_NAME "ni_pcimio"
130
131/* The following two tables must be in the same order */
132static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
133 {PCI_VENDOR_ID_NATINST, 0x0162, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
134 {PCI_VENDOR_ID_NATINST, 0x1170, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NATINST, 0x1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
136 {PCI_VENDOR_ID_NATINST, 0x1190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NATINST, 0x11b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
138 {PCI_VENDOR_ID_NATINST, 0x11c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NATINST, 0x11d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
140 {PCI_VENDOR_ID_NATINST, 0x1270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NATINST, 0x1330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
142 {PCI_VENDOR_ID_NATINST, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NATINST, 0x1350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
144 {PCI_VENDOR_ID_NATINST, 0x14e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NATINST, 0x14f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 {PCI_VENDOR_ID_NATINST, 0x1580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NATINST, 0x15b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
148 {PCI_VENDOR_ID_NATINST, 0x1880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NATINST, 0x1870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
150 {PCI_VENDOR_ID_NATINST, 0x18b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NATINST, 0x18c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
152 {PCI_VENDOR_ID_NATINST, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NATINST, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
154 {PCI_VENDOR_ID_NATINST, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NATINST, 0x2890, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
156 {PCI_VENDOR_ID_NATINST, 0x28c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NATINST, 0x2a60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
158 {PCI_VENDOR_ID_NATINST, 0x2a70, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NATINST, 0x2a80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
160 {PCI_VENDOR_ID_NATINST, 0x2ab0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NATINST, 0x2b80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 {PCI_VENDOR_ID_NATINST, 0x2b90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NATINST, 0x2c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
164 {PCI_VENDOR_ID_NATINST, 0x2ca0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NATINST, 0x70aa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
166 {PCI_VENDOR_ID_NATINST, 0x70ab, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NATINST, 0x70ac, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
168 {PCI_VENDOR_ID_NATINST, 0x70af, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NATINST, 0x70b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
170 {PCI_VENDOR_ID_NATINST, 0x70b4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NATINST, 0x70b6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
172 {PCI_VENDOR_ID_NATINST, 0x70b7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NATINST, 0x70b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
174 {PCI_VENDOR_ID_NATINST, 0x70bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NATINST, 0x70bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
176 {PCI_VENDOR_ID_NATINST, 0x70bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NATINST, 0x70c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {PCI_VENDOR_ID_NATINST, 0x70f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NATINST, 0x710d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
180 {PCI_VENDOR_ID_NATINST, 0x716c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NATINST, 0x717f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
182 {PCI_VENDOR_ID_NATINST, 0x71bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NATINST, 0x717d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
184 {0}
185};
186
187MODULE_DEVICE_TABLE(pci, ni_pci_table);
188
189/* These are not all the possible ao ranges for 628x boards.
190 They can do OFFSET +- REFERENCE where OFFSET can be
191 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
192 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
193 63 different possibilities. An AO channel
194 can not act as it's own OFFSET or REFERENCE.
195*/
9ced1de6 196static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
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DS		 197 RANGE(-10, 10),
198 RANGE(-5, 5),
199 RANGE(-2, 2),
200 RANGE(-1, 1),
201 RANGE(-5, 15),
202 RANGE(0, 10),
203 RANGE(3, 7),
204 RANGE(4, 6),
205 RANGE_ext(-1, 1)
206 }
207};
9ced1de6 208static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
c4beb34e
DS		 209 RANGE(-10, 10),
210 RANGE(-5, 5),
211 RANGE_ext(-1, 1)
212 }
213};
9ced1de6 214static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
c4beb34e
DS		 215 RANGE(-10, 10),
216 }
217};
218
219static const ni_board ni_boards[] = {
220 {
221 .device_id = 0x0162, // NI also says 0x1620. typo?
222 .name = "pci-mio-16xe-50",
223 .n_adchan = 16,
224 .adbits = 16,
225 .ai_fifo_depth = 2048,
226 .alwaysdither = 1,
227 .gainlkup = ai_gain_8,
228 .ai_speed = 50000,
229 .n_aochan = 2,
230 .aobits = 12,
231 .ao_fifo_depth = 0,
232 .ao_range_table = &range_bipolar10,
233 .ao_unipolar = 0,
234 .ao_speed = 50000,
235 .num_p0_dio_channels = 8,
236 .caldac = {dac8800, dac8043},
237 .has_8255 = 0,
238 },
239 {
240 .device_id = 0x1170,
241 .name = "pci-mio-16xe-10", // aka pci-6030E
242 .n_adchan = 16,
243 .adbits = 16,
244 .ai_fifo_depth = 512,
245 .alwaysdither = 1,
246 .gainlkup = ai_gain_14,
247 .ai_speed = 10000,
248 .n_aochan = 2,
249 .aobits = 16,
250 .ao_fifo_depth = 2048,
251 .ao_range_table = &range_ni_E_ao_ext,
252 .ao_unipolar = 1,
253 .ao_speed = 10000,
254 .num_p0_dio_channels = 8,
255 .caldac = {dac8800, dac8043, ad8522},
256 .has_8255 = 0,
257 },
258 {
259 .device_id = 0x28c0,
260 .name = "pci-6014",
261 .n_adchan = 16,
262 .adbits = 16,
263 .ai_fifo_depth = 512,
264 .alwaysdither = 1,
265 .gainlkup = ai_gain_4,
266 .ai_speed = 5000,
267 .n_aochan = 2,
268 .aobits = 16,
269 .ao_fifo_depth = 0,
270 .ao_range_table = &range_bipolar10,
271 .ao_unipolar = 0,
272 .ao_speed = 100000,
273 .num_p0_dio_channels = 8,
274 .caldac = {ad8804_debug},
275 .has_8255 = 0,
276 },
277 {
278 .device_id = 0x11d0,
279 .name = "pxi-6030e",
280 .n_adchan = 16,
281 .adbits = 16,
282 .ai_fifo_depth = 512,
283 .alwaysdither = 1,
284 .gainlkup = ai_gain_14,
285 .ai_speed = 10000,
286 .n_aochan = 2,
287 .aobits = 16,
288 .ao_fifo_depth = 2048,
289 .ao_range_table = &range_ni_E_ao_ext,
290 .ao_unipolar = 1,
291 .ao_speed = 10000,
292 .num_p0_dio_channels = 8,
293 .caldac = {dac8800, dac8043, ad8522},
294 .has_8255 = 0,
295 },
296 {
297 .device_id = 0x1180,
298 .name = "pci-mio-16e-1", /* aka pci-6070e */
299 .n_adchan = 16,
300 .adbits = 12,
301 .ai_fifo_depth = 512,
302 .alwaysdither = 0,
303 .gainlkup = ai_gain_16,
304 .ai_speed = 800,
305 .n_aochan = 2,
306 .aobits = 12,
307 .ao_fifo_depth = 2048,
308 .ao_range_table = &range_ni_E_ao_ext,
309 .ao_unipolar = 1,
310 .ao_speed = 1000,
311 .num_p0_dio_channels = 8,
312 .caldac = {mb88341},
313 .has_8255 = 0,
314 },
315 {
316 .device_id = 0x1190,
317 .name = "pci-mio-16e-4", /* aka pci-6040e */
318 .n_adchan = 16,
319 .adbits = 12,
320 .ai_fifo_depth = 512,
321 .alwaysdither = 0,
322 .gainlkup = ai_gain_16,
323 /* Note: there have been reported problems with full speed
324 * on this board */
325 .ai_speed = 2000,
326 .n_aochan = 2,
327 .aobits = 12,
328 .ao_fifo_depth = 512,
329 .ao_range_table = &range_ni_E_ao_ext,
330 .ao_unipolar = 1,
331 .ao_speed = 1000,
332 .num_p0_dio_channels = 8,
333 .caldac = {ad8804_debug}, // doc says mb88341
334 .has_8255 = 0,
335 },
336 {
337 .device_id = 0x11c0,
338 .name = "pxi-6040e",
339 .n_adchan = 16,
340 .adbits = 12,
341 .ai_fifo_depth = 512,
342 .alwaysdither = 0,
343 .gainlkup = ai_gain_16,
344 .ai_speed = 2000,
345 .n_aochan = 2,
346 .aobits = 12,
347 .ao_fifo_depth = 512,
348 .ao_range_table = &range_ni_E_ao_ext,
349 .ao_unipolar = 1,
350 .ao_speed = 1000,
351 .num_p0_dio_channels = 8,
352 .caldac = {mb88341},
353 .has_8255 = 0,
354 },
355
356 {
357 .device_id = 0x1330,
358 .name = "pci-6031e",
359 .n_adchan = 64,
360 .adbits = 16,
361 .ai_fifo_depth = 512,
362 .alwaysdither = 1,
363 .gainlkup = ai_gain_14,
364 .ai_speed = 10000,
365 .n_aochan = 2,
366 .aobits = 16,
367 .ao_fifo_depth = 2048,
368 .ao_range_table = &range_ni_E_ao_ext,
369 .ao_unipolar = 1,
370 .ao_speed = 10000,
371 .num_p0_dio_channels = 8,
372 .caldac = {dac8800, dac8043, ad8522},
373 .has_8255 = 0,
374 },
375 {
376 .device_id = 0x1270,
377 .name = "pci-6032e",
378 .n_adchan = 16,
379 .adbits = 16,
380 .ai_fifo_depth = 512,
381 .alwaysdither = 1,
382 .gainlkup = ai_gain_14,
383 .ai_speed = 10000,
384 .n_aochan = 0,
385 .aobits = 0,
386 .ao_fifo_depth = 0,
387 .ao_unipolar = 0,
388 .num_p0_dio_channels = 8,
389 .caldac = {dac8800, dac8043, ad8522},
390 .has_8255 = 0,
391 },
392 {
393 .device_id = 0x1340,
394 .name = "pci-6033e",
395 .n_adchan = 64,
396 .adbits = 16,
397 .ai_fifo_depth = 512,
398 .alwaysdither = 1,
399 .gainlkup = ai_gain_14,
400 .ai_speed = 10000,
401 .n_aochan = 0,
402 .aobits = 0,
403 .ao_fifo_depth = 0,
404 .ao_unipolar = 0,
405 .num_p0_dio_channels = 8,
406 .caldac = {dac8800, dac8043, ad8522},
407 .has_8255 = 0,
408 },
409 {
410 .device_id = 0x1350,
411 .name = "pci-6071e",
412 .n_adchan = 64,
413 .adbits = 12,
414 .ai_fifo_depth = 512,
415 .alwaysdither = 1,
416 .gainlkup = ai_gain_16,
417 .ai_speed = 800,
418 .n_aochan = 2,
419 .aobits = 12,
420 .ao_fifo_depth = 2048,
421 .ao_range_table = &range_ni_E_ao_ext,
422 .ao_unipolar = 1,
423 .ao_speed = 1000,
424 .num_p0_dio_channels = 8,
425 .caldac = {ad8804_debug},
426 .has_8255 = 0,
427 },
428 {
429 .device_id = 0x2a60,
430 .name = "pci-6023e",
431 .n_adchan = 16,
432 .adbits = 12,
433 .ai_fifo_depth = 512,
434 .alwaysdither = 0,
435 .gainlkup = ai_gain_4,
436 .ai_speed = 5000,
437 .n_aochan = 0,
438 .aobits = 0,
439 .ao_unipolar = 0,
440 .num_p0_dio_channels = 8,
441 .caldac = {ad8804_debug}, /* manual is wrong */
442 .has_8255 = 0,
443 },
444 {
445 .device_id = 0x2a70,
446 .name = "pci-6024e",
447 .n_adchan = 16,
448 .adbits = 12,
449 .ai_fifo_depth = 512,
450 .alwaysdither = 0,
451 .gainlkup = ai_gain_4,
452 .ai_speed = 5000,
453 .n_aochan = 2,
454 .aobits = 12,
455 .ao_fifo_depth = 0,
456 .ao_range_table = &range_bipolar10,
457 .ao_unipolar = 0,
458 .ao_speed = 100000,
459 .num_p0_dio_channels = 8,
460 .caldac = {ad8804_debug}, /* manual is wrong */
461 .has_8255 = 0,
462 },
463 {
464 .device_id = 0x2a80,
465 .name = "pci-6025e",
466 .n_adchan = 16,
467 .adbits = 12,
468 .ai_fifo_depth = 512,
469 .alwaysdither = 0,
470 .gainlkup = ai_gain_4,
471 .ai_speed = 5000,
472 .n_aochan = 2,
473 .aobits = 12,
474 .ao_fifo_depth = 0,
475 .ao_range_table = &range_bipolar10,
476 .ao_unipolar = 0,
477 .ao_speed = 100000,
478 .num_p0_dio_channels = 8,
479 .caldac = {ad8804_debug}, /* manual is wrong */
480 .has_8255 = 1,
481 },
482 {
483 .device_id = 0x2ab0,
484 .name = "pxi-6025e",
485 .n_adchan = 16,
486 .adbits = 12,
487 .ai_fifo_depth = 512,
488 .alwaysdither = 0,
489 .gainlkup = ai_gain_4,
490 .ai_speed = 5000,
491 .n_aochan = 2,
492 .aobits = 12,
493 .ao_fifo_depth = 0,
494 .ao_range_table = &range_ni_E_ao_ext,
495 .ao_unipolar = 1,
496 .ao_speed = 100000,
497 .num_p0_dio_channels = 8,
498 .caldac = {ad8804_debug}, /* manual is wrong */
499 .has_8255 = 1,
500 },
501
502 {
503 .device_id = 0x2ca0,
504 .name = "pci-6034e",
505 .n_adchan = 16,
506 .adbits = 16,
507 .ai_fifo_depth = 512,
508 .alwaysdither = 1,
509 .gainlkup = ai_gain_4,
510 .ai_speed = 5000,
511 .n_aochan = 0,
512 .aobits = 0,
513 .ao_fifo_depth = 0,
514 .ao_unipolar = 0,
515 .num_p0_dio_channels = 8,
516 .caldac = {ad8804_debug},
517 .has_8255 = 0,
518 },
519 {
520 .device_id = 0x2c80,
521 .name = "pci-6035e",
522 .n_adchan = 16,
523 .adbits = 16,
524 .ai_fifo_depth = 512,
525 .alwaysdither = 1,
526 .gainlkup = ai_gain_4,
527 .ai_speed = 5000,
528 .n_aochan = 2,
529 .aobits = 12,
530 .ao_fifo_depth = 0,
531 .ao_range_table = &range_bipolar10,
532 .ao_unipolar = 0,
533 .ao_speed = 100000,
534 .num_p0_dio_channels = 8,
535 .caldac = {ad8804_debug},
536 .has_8255 = 0,
537 },
538 {
539 .device_id = 0x18b0,
540 .name = "pci-6052e",
541 .n_adchan = 16,
542 .adbits = 16,
543 .ai_fifo_depth = 512,
544 .alwaysdither = 1,
545 .gainlkup = ai_gain_16,
546 .ai_speed = 3000,
547 .n_aochan = 2,
548 .aobits = 16,
549 .ao_unipolar = 1,
550 .ao_fifo_depth = 2048,
551 .ao_range_table = &range_ni_E_ao_ext,
552 .ao_speed = 3000,
553 .num_p0_dio_channels = 8,
554 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
555 },
556 {.device_id = 0x14e0,
557 .name = "pci-6110",
558 .n_adchan = 4,
559 .adbits = 12,
560 .ai_fifo_depth = 8192,
561 .alwaysdither = 0,
562 .gainlkup = ai_gain_611x,
563 .ai_speed = 200,
564 .n_aochan = 2,
565 .aobits = 16,
566 .reg_type = ni_reg_611x,
567 .ao_range_table = &range_bipolar10,
568 .ao_unipolar = 0,
569 .ao_fifo_depth = 2048,
570 .ao_speed = 250,
571 .num_p0_dio_channels = 8,
572 .caldac = {ad8804, ad8804},
573 },
574 {
575 .device_id = 0x14f0,
576 .name = "pci-6111",
577 .n_adchan = 2,
578 .adbits = 12,
579 .ai_fifo_depth = 8192,
580 .alwaysdither = 0,
581 .gainlkup = ai_gain_611x,
582 .ai_speed = 200,
583 .n_aochan = 2,
584 .aobits = 16,
585 .reg_type = ni_reg_611x,
586 .ao_range_table = &range_bipolar10,
587 .ao_unipolar = 0,
588 .ao_fifo_depth = 2048,
589 .ao_speed = 250,
590 .num_p0_dio_channels = 8,
591 .caldac = {ad8804, ad8804},
592 },
593#if 0
594 /* The 6115 boards probably need their own driver */
595 {
596 .device_id = 0x2ed0,
597 .name = "pci-6115",
598 .n_adchan = 4,
599 .adbits = 12,
600 .ai_fifo_depth = 8192,
601 .alwaysdither = 0,
602 .gainlkup = ai_gain_611x,
603 .ai_speed = 100,
604 .n_aochan = 2,
605 .aobits = 16,
606 .ao_671x = 1,
607 .ao_unipolar = 0,
608 .ao_fifo_depth = 2048,
609 .ao_speed = 250,
610 .num_p0_dio_channels = 8,
611 .reg_611x = 1,
612 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
613 },
614#endif
615#if 0
616 {
617 .device_id = 0x0000,
618 .name = "pxi-6115",
619 .n_adchan = 4,
620 .adbits = 12,
621 .ai_fifo_depth = 8192,
622 .alwaysdither = 0,
623 .gainlkup = ai_gain_611x,
624 .ai_speed = 100,
625 .n_aochan = 2,
626 .aobits = 16,
627 .ao_671x = 1,
628 .ao_unipolar = 0,
629 .ao_fifo_depth = 2048,
630 .ao_speed = 250,
631 .reg_611x = 1,
632 .num_p0_dio_channels = 8,
633 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
634 },
635#endif
636 {
637 .device_id = 0x1880,
638 .name = "pci-6711",
639 .n_adchan = 0, /* no analog input */
640 .n_aochan = 4,
641 .aobits = 12,
642 .ao_unipolar = 0,
643 .ao_fifo_depth = 16384,
644 /* data sheet says 8192, but fifo really holds 16384 samples */
645 .ao_range_table = &range_bipolar10,
646 .ao_speed = 1000,
647 .num_p0_dio_channels = 8,
648 .reg_type = ni_reg_6711,
649 .caldac = {ad8804_debug},
650 },
651 {
652 .device_id = 0x2b90,
653 .name = "pxi-6711",
654 .n_adchan = 0, /* no analog input */
655 .n_aochan = 4,
656 .aobits = 12,
657 .ao_unipolar = 0,
658 .ao_fifo_depth = 16384,
659 .ao_range_table = &range_bipolar10,
660 .ao_speed = 1000,
661 .num_p0_dio_channels = 8,
662 .reg_type = ni_reg_6711,
663 .caldac = {ad8804_debug},
664 },
665 {
666 .device_id = 0x1870,
667 .name = "pci-6713",
668 .n_adchan = 0, /* no analog input */
669 .n_aochan = 8,
670 .aobits = 12,
671 .ao_unipolar = 0,
672 .ao_fifo_depth = 16384,
673 .ao_range_table = &range_bipolar10,
674 .ao_speed = 1000,
675 .num_p0_dio_channels = 8,
676 .reg_type = ni_reg_6713,
677 .caldac = {ad8804_debug, ad8804_debug},
678 },
679 {
680 .device_id = 0x2b80,
681 .name = "pxi-6713",
682 .n_adchan = 0, /* no analog input */
683 .n_aochan = 8,
684 .aobits = 12,
685 .ao_unipolar = 0,
686 .ao_fifo_depth = 16384,
687 .ao_range_table = &range_bipolar10,
688 .ao_speed = 1000,
689 .num_p0_dio_channels = 8,
690 .reg_type = ni_reg_6713,
691 .caldac = {ad8804_debug, ad8804_debug},
692 },
693 {
694 .device_id = 0x2430,
695 .name = "pci-6731",
696 .n_adchan = 0, /* no analog input */
697 .n_aochan = 4,
698 .aobits = 16,
699 .ao_unipolar = 0,
700 .ao_fifo_depth = 8192,
701 .ao_range_table = &range_bipolar10,
702 .ao_speed = 1000,
703 .num_p0_dio_channels = 8,
704 .reg_type = ni_reg_6711,
705 .caldac = {ad8804_debug},
706 },
707#if 0 /* need device ids */
708 {
709 .device_id = 0x0,
710 .name = "pxi-6731",
711 .n_adchan = 0, /* no analog input */
712 .n_aochan = 4,
713 .aobits = 16,
714 .ao_unipolar = 0,
715 .ao_fifo_depth = 8192,
716 .ao_range_table = &range_bipolar10,
717 .num_p0_dio_channels = 8,
718 .reg_type = ni_reg_6711,
719 .caldac = {ad8804_debug},
720 },
721#endif
722 {
723 .device_id = 0x2410,
724 .name = "pci-6733",
725 .n_adchan = 0, /* no analog input */
726 .n_aochan = 8,
727 .aobits = 16,
728 .ao_unipolar = 0,
729 .ao_fifo_depth = 16384,
730 .ao_range_table = &range_bipolar10,
731 .ao_speed = 1000,
732 .num_p0_dio_channels = 8,
733 .reg_type = ni_reg_6713,
734 .caldac = {ad8804_debug, ad8804_debug},
735 },
736 {
737 .device_id = 0x2420,
738 .name = "pxi-6733",
739 .n_adchan = 0, /* no analog input */
740 .n_aochan = 8,
741 .aobits = 16,
742 .ao_unipolar = 0,
743 .ao_fifo_depth = 16384,
744 .ao_range_table = &range_bipolar10,
745 .ao_speed = 1000,
746 .num_p0_dio_channels = 8,
747 .reg_type = ni_reg_6713,
748 .caldac = {ad8804_debug, ad8804_debug},
749 },
750 {
751 .device_id = 0x15b0,
752 .name = "pxi-6071e",
753 .n_adchan = 64,
754 .adbits = 12,
755 .ai_fifo_depth = 512,
756 .alwaysdither = 1,
757 .gainlkup = ai_gain_16,
758 .ai_speed = 800,
759 .n_aochan = 2,
760 .aobits = 12,
761 .ao_fifo_depth = 2048,
762 .ao_range_table = &range_ni_E_ao_ext,
763 .ao_unipolar = 1,
764 .ao_speed = 1000,
765 .num_p0_dio_channels = 8,
766 .caldac = {ad8804_debug},
767 .has_8255 = 0,
768 },
769 {
770 .device_id = 0x11b0,
771 .name = "pxi-6070e",
772 .n_adchan = 16,
773 .adbits = 12,
774 .ai_fifo_depth = 512,
775 .alwaysdither = 1,
776 .gainlkup = ai_gain_16,
777 .ai_speed = 800,
778 .n_aochan = 2,
779 .aobits = 12,
780 .ao_fifo_depth = 2048,
781 .ao_range_table = &range_ni_E_ao_ext,
782 .ao_unipolar = 1,
783 .ao_speed = 1000,
784 .num_p0_dio_channels = 8,
785 .caldac = {ad8804_debug},
786 .has_8255 = 0,
787 },
788 {
789 .device_id = 0x18c0,
790 .name = "pxi-6052e",
791 .n_adchan = 16,
792 .adbits = 16,
793 .ai_fifo_depth = 512,
794 .alwaysdither = 1,
795 .gainlkup = ai_gain_16,
796 .ai_speed = 3000,
797 .n_aochan = 2,
798 .aobits = 16,
799 .ao_unipolar = 1,
800 .ao_fifo_depth = 2048,
801 .ao_range_table = &range_ni_E_ao_ext,
802 .ao_speed = 3000,
803 .num_p0_dio_channels = 8,
804 .caldac = {mb88341, mb88341, ad8522},
805 },
806 {
807 .device_id = 0x1580,
808 .name = "pxi-6031e",
809 .n_adchan = 64,
810 .adbits = 16,
811 .ai_fifo_depth = 512,
812 .alwaysdither = 1,
813 .gainlkup = ai_gain_14,
814 .ai_speed = 10000,
815 .n_aochan = 2,
816 .aobits = 16,
817 .ao_fifo_depth = 2048,
818 .ao_range_table = &range_ni_E_ao_ext,
819 .ao_unipolar = 1,
820 .ao_speed = 10000,
821 .num_p0_dio_channels = 8,
822 .caldac = {dac8800, dac8043, ad8522},
823 },
824 {
825 .device_id = 0x2890,
826 .name = "pci-6036e",
827 .n_adchan = 16,
828 .adbits = 16,
829 .ai_fifo_depth = 512,
830 .alwaysdither = 1,
831 .gainlkup = ai_gain_4,
832 .ai_speed = 5000,
833 .n_aochan = 2,
834 .aobits = 16,
835 .ao_fifo_depth = 0,
836 .ao_range_table = &range_bipolar10,
837 .ao_unipolar = 0,
838 .ao_speed = 100000,
839 .num_p0_dio_channels = 8,
840 .caldac = {ad8804_debug},
841 .has_8255 = 0,
842 },
843 {
844 .device_id = 0x70b0,
845 .name = "pci-6220",
846 .n_adchan = 16,
847 .adbits = 16,
848 .ai_fifo_depth = 512,
849 //FIXME: guess
850 .gainlkup = ai_gain_622x,
851 .ai_speed = 4000,
852 .n_aochan = 0,
853 .aobits = 0,
854 .ao_fifo_depth = 0,
855 .num_p0_dio_channels = 8,
856 .reg_type = ni_reg_622x,
857 .ao_unipolar = 0,
858 .caldac = {caldac_none},
859 .has_8255 = 0,
860 },
861 {
862 .device_id = 0x70af,
863 .name = "pci-6221",
864 .n_adchan = 16,
865 .adbits = 16,
866 .ai_fifo_depth = 4095,
867 .gainlkup = ai_gain_622x,
868 .ai_speed = 4000,
869 .n_aochan = 2,
870 .aobits = 16,
871 .ao_fifo_depth = 8191,
872 .ao_range_table = &range_ni_M_622x_ao,
873 .reg_type = ni_reg_622x,
874 .ao_unipolar = 0,
875 .ao_speed = 1200,
876 .num_p0_dio_channels = 8,
877 .caldac = {caldac_none},
878 .has_8255 = 0,
879 },
880 {
881 .device_id = 0x71bc,
882 .name = "pci-6221_37pin",
883 .n_adchan = 16,
884 .adbits = 16,
885 .ai_fifo_depth = 4095,
886 .gainlkup = ai_gain_622x,
887 .ai_speed = 4000,
888 .n_aochan = 2,
889 .aobits = 16,
890 .ao_fifo_depth = 8191,
891 .ao_range_table = &range_ni_M_622x_ao,
892 .reg_type = ni_reg_622x,
893 .ao_unipolar = 0,
894 .ao_speed = 1200,
895 .num_p0_dio_channels = 8,
896 .caldac = {caldac_none},
897 .has_8255 = 0,
898 },
899 {
900 .device_id = 0x70f2,
901 .name = "pci-6224",
902 .n_adchan = 32,
903 .adbits = 16,
904 .ai_fifo_depth = 4095,
905 .gainlkup = ai_gain_622x,
906 .ai_speed = 4000,
907 .n_aochan = 0,
908 .aobits = 0,
909 .ao_fifo_depth = 0,
51e290fd
IA		 910 .reg_type = ni_reg_622x,
911 .ao_unipolar = 0,
912 .num_p0_dio_channels = 32,
913 .caldac = {caldac_none},
914 .has_8255 = 0,
915 },
916 {
917 .device_id = 0x70f3,
918 .name = "pxi-6224",
919 .n_adchan = 32,
920 .adbits = 16,
921 .ai_fifo_depth = 4095,
922 .gainlkup = ai_gain_622x,
923 .ai_speed = 4000,
924 .n_aochan = 0,
925 .aobits = 0,
926 .ao_fifo_depth = 0,
c4beb34e
DS		 927 .reg_type = ni_reg_622x,
928 .ao_unipolar = 0,
929 .num_p0_dio_channels = 32,
930 .caldac = {caldac_none},
931 .has_8255 = 0,
932 },
933 {
934 .device_id = 0x716c,
935 .name = "pci-6225",
936 .n_adchan = 80,
937 .adbits = 16,
938 .ai_fifo_depth = 4095,
939 .gainlkup = ai_gain_622x,
940 .ai_speed = 4000,
941 .n_aochan = 2,
942 .aobits = 16,
943 .ao_fifo_depth = 8191,
944 .ao_range_table = &range_ni_M_622x_ao,
945 .reg_type = ni_reg_622x,
946 .ao_unipolar = 0,
947 .ao_speed = 1200,
948 .num_p0_dio_channels = 32,
949 .caldac = {caldac_none},
950 .has_8255 = 0,
951 },
952 {
953 .device_id = 0x70aa,
954 .name = "pci-6229",
955 .n_adchan = 32,
956 .adbits = 16,
957 .ai_fifo_depth = 4095,
958 .gainlkup = ai_gain_622x,
959 .ai_speed = 4000,
960 .n_aochan = 4,
961 .aobits = 16,
962 .ao_fifo_depth = 8191,
963 .ao_range_table = &range_ni_M_622x_ao,
964 .reg_type = ni_reg_622x,
965 .ao_unipolar = 0,
966 .ao_speed = 1200,
967 .num_p0_dio_channels = 32,
968 .caldac = {caldac_none},
969 .has_8255 = 0,
970 },
971 {
972 .device_id = 0x70b4,
973 .name = "pci-6250",
974 .n_adchan = 16,
975 .adbits = 16,
976 .ai_fifo_depth = 4095,
977 .gainlkup = ai_gain_628x,
978 .ai_speed = 800,
979 .n_aochan = 0,
980 .aobits = 0,
981 .ao_fifo_depth = 0,
982 .reg_type = ni_reg_625x,
983 .ao_unipolar = 0,
984 .num_p0_dio_channels = 8,
985 .caldac = {caldac_none},
986 .has_8255 = 0,
987 },
988 {
989 .device_id = 0x70b8,
990 .name = "pci-6251",
991 .n_adchan = 16,
992 .adbits = 16,
993 .ai_fifo_depth = 4095,
994 .gainlkup = ai_gain_628x,
995 .ai_speed = 800,
996 .n_aochan = 2,
997 .aobits = 16,
998 .ao_fifo_depth = 8191,
999 .ao_range_table = &range_ni_M_625x_ao,
1000 .reg_type = ni_reg_625x,
1001 .ao_unipolar = 0,
1002 .ao_speed = 357,
1003 .num_p0_dio_channels = 8,
1004 .caldac = {caldac_none},
1005 .has_8255 = 0,
1006 },
1007 {
1008 .device_id = 0x717d,
1009 .name = "pcie-6251",
1010 .n_adchan = 16,
1011 .adbits = 16,
1012 .ai_fifo_depth = 4095,
1013 .gainlkup = ai_gain_628x,
1014 .ai_speed = 800,
1015 .n_aochan = 2,
1016 .aobits = 16,
1017 .ao_fifo_depth = 8191,
1018 .ao_range_table = &range_ni_M_625x_ao,
1019 .reg_type = ni_reg_625x,
1020 .ao_unipolar = 0,
1021 .ao_speed = 357,
1022 .num_p0_dio_channels = 8,
1023 .caldac = {caldac_none},
1024 .has_8255 = 0,
1025 },
1026 {
1027 .device_id = 0x70b7,
1028 .name = "pci-6254",
1029 .n_adchan = 32,
1030 .adbits = 16,
1031 .ai_fifo_depth = 4095,
1032 .gainlkup = ai_gain_628x,
1033 .ai_speed = 800,
1034 .n_aochan = 0,
1035 .aobits = 0,
1036 .ao_fifo_depth = 0,
1037 .reg_type = ni_reg_625x,
1038 .ao_unipolar = 0,
1039 .num_p0_dio_channels = 32,
1040 .caldac = {caldac_none},
1041 .has_8255 = 0,
1042 },
1043 {
1044 .device_id = 0x70ab,
1045 .name = "pci-6259",
1046 .n_adchan = 32,
1047 .adbits = 16,
1048 .ai_fifo_depth = 4095,
1049 .gainlkup = ai_gain_628x,
1050 .ai_speed = 800,
1051 .n_aochan = 4,
1052 .aobits = 16,
1053 .ao_fifo_depth = 8191,
1054 .ao_range_table = &range_ni_M_625x_ao,
1055 .reg_type = ni_reg_625x,
1056 .ao_unipolar = 0,
1057 .ao_speed = 357,
1058 .num_p0_dio_channels = 32,
1059 .caldac = {caldac_none},
1060 .has_8255 = 0,
1061 },
1062 {
1063 .device_id = 0x717f,
1064 .name = "pcie-6259",
1065 .n_adchan = 32,
1066 .adbits = 16,
1067 .ai_fifo_depth = 4095,
1068 .gainlkup = ai_gain_628x,
1069 .ai_speed = 800,
1070 .n_aochan = 4,
1071 .aobits = 16,
1072 .ao_fifo_depth = 8191,
1073 .ao_range_table = &range_ni_M_625x_ao,
1074 .reg_type = ni_reg_625x,
1075 .ao_unipolar = 0,
1076 .ao_speed = 357,
1077 .num_p0_dio_channels = 32,
1078 .caldac = {caldac_none},
1079 .has_8255 = 0,
1080 },
1081 {
1082 .device_id = 0x70b6,
1083 .name = "pci-6280",
1084 .n_adchan = 16,
1085 .adbits = 18,
1086 .ai_fifo_depth = 2047,
1087 .gainlkup = ai_gain_628x,
1088 .ai_speed = 1600,
1089 .n_aochan = 0,
1090 .aobits = 0,
1091 .ao_fifo_depth = 8191,
1092 .reg_type = ni_reg_628x,
1093 .ao_unipolar = 0,
1094 .num_p0_dio_channels = 8,
1095 .caldac = {caldac_none},
1096 .has_8255 = 0,
1097 },
1098 {
1099 .device_id = 0x70bd,
1100 .name = "pci-6281",
1101 .n_adchan = 16,
1102 .adbits = 18,
1103 .ai_fifo_depth = 2047,
1104 .gainlkup = ai_gain_628x,
1105 .ai_speed = 1600,
1106 .n_aochan = 2,
1107 .aobits = 16,
1108 .ao_fifo_depth = 8191,
1109 .ao_range_table = &range_ni_M_628x_ao,
1110 .reg_type = ni_reg_628x,
1111 .ao_unipolar = 1,
1112 .ao_speed = 357,
1113 .num_p0_dio_channels = 8,
1114 .caldac = {caldac_none},
1115 .has_8255 = 0,
1116 },
1117 {
1118 .device_id = 0x70bf,
1119 .name = "pxi-6281",
1120 .n_adchan = 16,
1121 .adbits = 18,
1122 .ai_fifo_depth = 2047,
1123 .gainlkup = ai_gain_628x,
1124 .ai_speed = 1600,
1125 .n_aochan = 2,
1126 .aobits = 16,
1127 .ao_fifo_depth = 8191,
1128 .ao_range_table = &range_ni_M_628x_ao,
1129 .reg_type = ni_reg_628x,
1130 .ao_unipolar = 1,
1131 .ao_speed = 357,
1132 .num_p0_dio_channels = 8,
1133 .caldac = {caldac_none},
1134 .has_8255 = 0,
1135 },
1136 {
1137 .device_id = 0x70bc,
1138 .name = "pci-6284",
1139 .n_adchan = 32,
1140 .adbits = 18,
1141 .ai_fifo_depth = 2047,
1142 .gainlkup = ai_gain_628x,
1143 .ai_speed = 1600,
1144 .n_aochan = 0,
1145 .aobits = 0,
1146 .ao_fifo_depth = 0,
1147 .reg_type = ni_reg_628x,
1148 .ao_unipolar = 0,
1149 .num_p0_dio_channels = 32,
1150 .caldac = {caldac_none},
1151 .has_8255 = 0,
1152 },
1153 {
1154 .device_id = 0x70ac,
1155 .name = "pci-6289",
1156 .n_adchan = 32,
1157 .adbits = 18,
1158 .ai_fifo_depth = 2047,
1159 .gainlkup = ai_gain_628x,
1160 .ai_speed = 1600,
1161 .n_aochan = 4,
1162 .aobits = 16,
1163 .ao_fifo_depth = 8191,
1164 .ao_range_table = &range_ni_M_628x_ao,
1165 .reg_type = ni_reg_628x,
1166 .ao_unipolar = 1,
1167 .ao_speed = 357,
1168 .num_p0_dio_channels = 32,
1169 .caldac = {caldac_none},
1170 .has_8255 = 0,
1171 },
1172 {
1173 .device_id = 0x70C0,
1174 .name = "pci-6143",
1175 .n_adchan = 8,
1176 .adbits = 16,
1177 .ai_fifo_depth = 1024,
1178 .alwaysdither = 0,
1179 .gainlkup = ai_gain_6143,
1180 .ai_speed = 4000,
1181 .n_aochan = 0,
1182 .aobits = 0,
1183 .reg_type = ni_reg_6143,
1184 .ao_unipolar = 0,
1185 .ao_fifo_depth = 0,
1186 .num_p0_dio_channels = 8,
1187 .caldac = {ad8804_debug, ad8804_debug},
1188 },
1189 {
1190 .device_id = 0x710D,
1191 .name = "pxi-6143",
1192 .n_adchan = 8,
1193 .adbits = 16,
1194 .ai_fifo_depth = 1024,
1195 .alwaysdither = 0,
1196 .gainlkup = ai_gain_6143,
1197 .ai_speed = 4000,
1198 .n_aochan = 0,
1199 .aobits = 0,
1200 .reg_type = ni_reg_6143,
1201 .ao_unipolar = 0,
1202 .ao_fifo_depth = 0,
1203 .num_p0_dio_channels = 8,
1204 .caldac = {ad8804_debug, ad8804_debug},
1205 },
1206};
1207
1208#define n_pcimio_boards ((sizeof(ni_boards)/sizeof(ni_boards[0])))
1209
0707bb04 1210static int pcimio_attach(struct comedi_device * dev, struct comedi_devconfig * it);
71b5f4f1 1211static int pcimio_detach(struct comedi_device * dev);
139dfbdf 1212static struct comedi_driver driver_pcimio = {
c4beb34e
DS		 1213 driver_name: DRV_NAME,
1214 module:THIS_MODULE,
1215 attach:pcimio_attach,
1216 detach:pcimio_detach,
1217};
1218
1219COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table)
1220
1221typedef struct {
1222NI_PRIVATE_COMMON} ni_private;
1223#define devpriv ((ni_private *)dev->private)
1224
1225/* How we access registers */
1226
1227#define ni_writel(a,b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1228#define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1229#define ni_writew(a,b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1230#define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1231#define ni_writeb(a,b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1232#define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1233
1234/* How we access STC registers */
1235
1236/* We automatically take advantage of STC registers that can be
1237 * read/written directly in the I/O space of the board. Most
1238 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1239 * The 611x devices map the write registers to iobase+addr*2, and
1240 * the read registers to iobase+(addr-1)*2. */
1241/* However, the 611x boards still aren't working, so I'm disabling
1242 * non-windowed STC access temporarily */
1243
71b5f4f1 1244static void e_series_win_out(struct comedi_device * dev, uint16_t data, int reg)
c4beb34e
DS		 1245{
1246 unsigned long flags;
1247
1248 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
1249 ni_writew(reg, Window_Address);
1250 ni_writew(data, Window_Data);
1251 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
1252}
1253
71b5f4f1 1254static uint16_t e_series_win_in(struct comedi_device * dev, int reg)
c4beb34e
DS		 1255{
1256 unsigned long flags;
1257 uint16_t ret;
1258
1259 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
1260 ni_writew(reg, Window_Address);
1261 ret = ni_readw(Window_Data);
1262 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
1263
1264 return ret;
1265}
1266
71b5f4f1 1267static void m_series_stc_writew(struct comedi_device * dev, uint16_t data, int reg)
c4beb34e
DS		 1268{
1269 unsigned offset;
1270 switch (reg) {
1271 case ADC_FIFO_Clear:
1272 offset = M_Offset_AI_FIFO_Clear;
1273 break;
1274 case AI_Command_1_Register:
1275 offset = M_Offset_AI_Command_1;
1276 break;
1277 case AI_Command_2_Register:
1278 offset = M_Offset_AI_Command_2;
1279 break;
1280 case AI_Mode_1_Register:
1281 offset = M_Offset_AI_Mode_1;
1282 break;
1283 case AI_Mode_2_Register:
1284 offset = M_Offset_AI_Mode_2;
1285 break;
1286 case AI_Mode_3_Register:
1287 offset = M_Offset_AI_Mode_3;
1288 break;
1289 case AI_Output_Control_Register:
1290 offset = M_Offset_AI_Output_Control;
1291 break;
1292 case AI_Personal_Register:
1293 offset = M_Offset_AI_Personal;
1294 break;
1295 case AI_SI2_Load_A_Register:
1296 // this is actually a 32 bit register on m series boards
1297 ni_writel(data, M_Offset_AI_SI2_Load_A);
1298 return;
1299 break;
1300 case AI_SI2_Load_B_Register:
1301 // this is actually a 32 bit register on m series boards
1302 ni_writel(data, M_Offset_AI_SI2_Load_B);
1303 return;
1304 break;
1305 case AI_START_STOP_Select_Register:
1306 offset = M_Offset_AI_START_STOP_Select;
1307 break;
1308 case AI_Trigger_Select_Register:
1309 offset = M_Offset_AI_Trigger_Select;
1310 break;
1311 case Analog_Trigger_Etc_Register:
1312 offset = M_Offset_Analog_Trigger_Etc;
1313 break;
1314 case AO_Command_1_Register:
1315 offset = M_Offset_AO_Command_1;
1316 break;
1317 case AO_Command_2_Register:
1318 offset = M_Offset_AO_Command_2;
1319 break;
1320 case AO_Mode_1_Register:
1321 offset = M_Offset_AO_Mode_1;
1322 break;
1323 case AO_Mode_2_Register:
1324 offset = M_Offset_AO_Mode_2;
1325 break;
1326 case AO_Mode_3_Register:
1327 offset = M_Offset_AO_Mode_3;
1328 break;
1329 case AO_Output_Control_Register:
1330 offset = M_Offset_AO_Output_Control;
1331 break;
1332 case AO_Personal_Register:
1333 offset = M_Offset_AO_Personal;
1334 break;
1335 case AO_Start_Select_Register:
1336 offset = M_Offset_AO_Start_Select;
1337 break;
1338 case AO_Trigger_Select_Register:
1339 offset = M_Offset_AO_Trigger_Select;
1340 break;
1341 case Clock_and_FOUT_Register:
1342 offset = M_Offset_Clock_and_FOUT;
1343 break;
1344 case Configuration_Memory_Clear:
1345 offset = M_Offset_Configuration_Memory_Clear;
1346 break;
1347 case DAC_FIFO_Clear:
1348 offset = M_Offset_AO_FIFO_Clear;
1349 break;
1350 case DIO_Control_Register:
1351 rt_printk
1352 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1353 __FUNCTION__, reg);
1354 return;
1355 break;
1356 case G_Autoincrement_Register(0):
1357 offset = M_Offset_G0_Autoincrement;
1358 break;
1359 case G_Autoincrement_Register(1):
1360 offset = M_Offset_G1_Autoincrement;
1361 break;
1362 case G_Command_Register(0):
1363 offset = M_Offset_G0_Command;
1364 break;
1365 case G_Command_Register(1):
1366 offset = M_Offset_G1_Command;
1367 break;
1368 case G_Input_Select_Register(0):
1369 offset = M_Offset_G0_Input_Select;
1370 break;
1371 case G_Input_Select_Register(1):
1372 offset = M_Offset_G1_Input_Select;
1373 break;
1374 case G_Mode_Register(0):
1375 offset = M_Offset_G0_Mode;
1376 break;
1377 case G_Mode_Register(1):
1378 offset = M_Offset_G1_Mode;
1379 break;
1380 case Interrupt_A_Ack_Register:
1381 offset = M_Offset_Interrupt_A_Ack;
1382 break;
1383 case Interrupt_A_Enable_Register:
1384 offset = M_Offset_Interrupt_A_Enable;
1385 break;
1386 case Interrupt_B_Ack_Register:
1387 offset = M_Offset_Interrupt_B_Ack;
1388 break;
1389 case Interrupt_B_Enable_Register:
1390 offset = M_Offset_Interrupt_B_Enable;
1391 break;
1392 case Interrupt_Control_Register:
1393 offset = M_Offset_Interrupt_Control;
1394 break;
1395 case IO_Bidirection_Pin_Register:
1396 offset = M_Offset_IO_Bidirection_Pin;
1397 break;
1398 case Joint_Reset_Register:
1399 offset = M_Offset_Joint_Reset;
1400 break;
1401 case RTSI_Trig_A_Output_Register:
1402 offset = M_Offset_RTSI_Trig_A_Output;
1403 break;
1404 case RTSI_Trig_B_Output_Register:
1405 offset = M_Offset_RTSI_Trig_B_Output;
1406 break;
1407 case RTSI_Trig_Direction_Register:
1408 offset = M_Offset_RTSI_Trig_Direction;
1409 break;
1410 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1411 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1412 default:
1413 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1414 __FUNCTION__, reg);
1415 BUG();
1416 return;
1417 break;
1418 }
1419 ni_writew(data, offset);
1420}
1421
71b5f4f1 1422static uint16_t m_series_stc_readw(struct comedi_device * dev, int reg)
c4beb34e
DS		 1423{
1424 unsigned offset;
1425 switch (reg) {
1426 case AI_Status_1_Register:
1427 offset = M_Offset_AI_Status_1;
1428 break;
1429 case AO_Status_1_Register:
1430 offset = M_Offset_AO_Status_1;
1431 break;
1432 case AO_Status_2_Register:
1433 offset = M_Offset_AO_Status_2;
1434 break;
1435 case DIO_Serial_Input_Register:
1436 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1437 break;
1438 case Joint_Status_1_Register:
1439 offset = M_Offset_Joint_Status_1;
1440 break;
1441 case Joint_Status_2_Register:
1442 offset = M_Offset_Joint_Status_2;
1443 break;
1444 case G_Status_Register:
1445 offset = M_Offset_G01_Status;
1446 break;
1447 default:
1448 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1449 __FUNCTION__, reg);
1450 BUG();
1451 return 0;
1452 break;
1453 }
1454 return ni_readw(offset);
1455}
1456
71b5f4f1 1457static void m_series_stc_writel(struct comedi_device * dev, uint32_t data, int reg)
c4beb34e
DS		 1458{
1459 unsigned offset;
1460 switch (reg) {
1461 case AI_SC_Load_A_Registers:
1462 offset = M_Offset_AI_SC_Load_A;
1463 break;
1464 case AI_SI_Load_A_Registers:
1465 offset = M_Offset_AI_SI_Load_A;
1466 break;
1467 case AO_BC_Load_A_Register:
1468 offset = M_Offset_AO_BC_Load_A;
1469 break;
1470 case AO_UC_Load_A_Register:
1471 offset = M_Offset_AO_UC_Load_A;
1472 break;
1473 case AO_UI_Load_A_Register:
1474 offset = M_Offset_AO_UI_Load_A;
1475 break;
1476 case G_Load_A_Register(0):
1477 offset = M_Offset_G0_Load_A;
1478 break;
1479 case G_Load_A_Register(1):
1480 offset = M_Offset_G1_Load_A;
1481 break;
1482 case G_Load_B_Register(0):
1483 offset = M_Offset_G0_Load_B;
1484 break;
1485 case G_Load_B_Register(1):
1486 offset = M_Offset_G1_Load_B;
1487 break;
1488 default:
1489 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1490 __FUNCTION__, reg);
1491 BUG();
1492 return;
1493 break;
1494 }
1495 ni_writel(data, offset);
1496}
1497
71b5f4f1 1498static uint32_t m_series_stc_readl(struct comedi_device * dev, int reg)
c4beb34e
DS		 1499{
1500 unsigned offset;
1501 switch (reg) {
1502 case G_HW_Save_Register(0):
1503 offset = M_Offset_G0_HW_Save;
1504 break;
1505 case G_HW_Save_Register(1):
1506 offset = M_Offset_G1_HW_Save;
1507 break;
1508 case G_Save_Register(0):
1509 offset = M_Offset_G0_Save;
1510 break;
1511 case G_Save_Register(1):
1512 offset = M_Offset_G1_Save;
1513 break;
1514 default:
1515 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1516 __FUNCTION__, reg);
1517 BUG();
1518 return 0;
1519 break;
1520 }
1521 return ni_readl(offset);
1522}
1523
1524#define interrupt_pin(a) 0
1525#define IRQ_POLARITY 1
1526
1527#define NI_E_IRQ_FLAGS IRQF_SHARED
1528
1529#include "ni_mio_common.c"
1530
71b5f4f1 1531static int pcimio_find_device(struct comedi_device * dev, int bus, int slot);
34c43922 1532static int pcimio_ai_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e 1533 unsigned long new_size);
34c43922 1534static int pcimio_ao_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e 1535 unsigned long new_size);
34c43922 1536static int pcimio_gpct0_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e 1537 unsigned long new_size);
34c43922 1538static int pcimio_gpct1_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e 1539 unsigned long new_size);
34c43922 1540static int pcimio_dio_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e
DS		 1541 unsigned long new_size);
1542
71b5f4f1 1543static void m_series_init_eeprom_buffer(struct comedi_device * dev)
c4beb34e
DS		 1544{
1545 static const int Start_Cal_EEPROM = 0x400;
1546 static const unsigned window_size = 10;
f8db88ef
FMH		 1547 static const int serial_number_eeprom_offset = 0x4;
1548 static const int serial_number_eeprom_length = 0x4;
c4beb34e
DS		 1549 unsigned old_iodwbsr_bits;
1550 unsigned old_iodwbsr1_bits;
1551 unsigned old_iodwcr1_bits;
1552 int i;
1553
1554 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1555 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1556 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1557 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1558 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1559 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
f8db88ef 1560 writel(0x1 | old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
c4beb34e
DS		 1561 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1562
f8db88ef
FMH		 1563 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1564 for (i = 0; i < serial_number_eeprom_length; ++i) {
1565 char *byte_ptr = (char*)&devpriv->serial_number + i;
1566 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1567 }
1568 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1569
c4beb34e
DS		 1570 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1571 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1572 }
1573
1574 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1575 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1576 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1577 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1578}
1579
71b5f4f1 1580static void init_6143(struct comedi_device * dev)
c4beb34e
DS		 1581{
1582 // Disable interrupts
1583 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1584
1585 // Initialise 6143 AI specific bits
1586 ni_writeb(0x00, Magic_6143); // Set G0,G1 DMA mode to E series version
1587 ni_writeb(0x80, PipelineDelay_6143); // Set EOCMode, ADCMode and pipelinedelay
1588 ni_writeb(0x00, EOC_Set_6143); // Set EOC Delay
1589
1590 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); // Set the FIFO half full level
1591
1592 // Strobe Relay disable bit
1593 devpriv->ai_calib_source_enabled = 0;
1594 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1595 Calibration_Channel_6143);
1596 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1597}
1598
1599/* cleans up allocated resources */
71b5f4f1 1600static int pcimio_detach(struct comedi_device * dev)
c4beb34e
DS		 1601{
1602 mio_common_detach(dev);
1603 if (dev->irq) {
1604 comedi_free_irq(dev->irq, dev);
1605 }
1606 if (dev->private) {
1607 mite_free_ring(devpriv->ai_mite_ring);
1608 mite_free_ring(devpriv->ao_mite_ring);
1609 mite_free_ring(devpriv->cdo_mite_ring);
1610 mite_free_ring(devpriv->gpct_mite_ring[0]);
1611 mite_free_ring(devpriv->gpct_mite_ring[1]);
1612 if (devpriv->mite)
1613 mite_unsetup(devpriv->mite);
1614 }
1615
1616 return 0;
1617}
1618
0707bb04 1619static int pcimio_attach(struct comedi_device * dev, struct comedi_devconfig * it)
c4beb34e
DS		 1620{
1621 int ret;
1622
1623 printk("comedi%d: ni_pcimio:", dev->minor);
1624
1625 ret = ni_alloc_private(dev);
1626 if (ret < 0)
1627 return ret;
1628
1629 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1630 if (ret < 0)
1631 return ret;
1632
1633 printk(" %s", boardtype.name);
1634 dev->board_name = boardtype.name;
1635
1636 if (boardtype.reg_type & ni_reg_m_series_mask) {
1637 devpriv->stc_writew = &m_series_stc_writew;
1638 devpriv->stc_readw = &m_series_stc_readw;
1639 devpriv->stc_writel = &m_series_stc_writel;
1640 devpriv->stc_readl = &m_series_stc_readl;
1641 } else {
1642 devpriv->stc_writew = &e_series_win_out;
1643 devpriv->stc_readw = &e_series_win_in;
1644 devpriv->stc_writel = &win_out2;
1645 devpriv->stc_readl = &win_in2;
1646 }
1647
1648 ret = mite_setup(devpriv->mite);
1649 if (ret < 0) {
1650 printk(" error setting up mite\n");
1651 return ret;
1652 }
1653 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1654 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1655 if (devpriv->ai_mite_ring == NULL)
1656 return -ENOMEM;
1657 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1658 if (devpriv->ao_mite_ring == NULL)
1659 return -ENOMEM;
1660 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1661 if (devpriv->cdo_mite_ring == NULL)
1662 return -ENOMEM;
1663 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1664 if (devpriv->gpct_mite_ring[0] == NULL)
1665 return -ENOMEM;
1666 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1667 if (devpriv->gpct_mite_ring[1] == NULL)
1668 return -ENOMEM;
1669
1670 if (boardtype.reg_type & ni_reg_m_series_mask)
1671 m_series_init_eeprom_buffer(dev);
1672 if (boardtype.reg_type == ni_reg_6143)
1673 init_6143(dev);
1674
1675 dev->irq = mite_irq(devpriv->mite);
1676
1677 if (dev->irq == 0) {
1678 printk(" unknown irq (bad)\n");
1679 } else {
1680 printk(" ( irq = %u )", dev->irq);
1681 if ((ret = comedi_request_irq(dev->irq, ni_E_interrupt,
1682 NI_E_IRQ_FLAGS, DRV_NAME,
1683 dev)) < 0) {
1684 printk(" irq not available\n");
1685 dev->irq = 0;
1686 }
1687 }
1688
1689 ret = ni_E_init(dev, it);
1690 if (ret < 0)
1691 return ret;
1692
1693 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1694 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1695 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1696 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1697 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1698
1699 return ret;
1700}
1701
71b5f4f1 1702static int pcimio_find_device(struct comedi_device * dev, int bus, int slot)
c4beb34e
DS		 1703{
1704 struct mite_struct *mite;
1705 int i;
1706
1707 for (mite = mite_devices; mite; mite = mite->next) {
1708 if (mite->used)
1709 continue;
1710 if (bus || slot) {
1711 if (bus != mite->pcidev->bus->number ||
1712 slot != PCI_SLOT(mite->pcidev->devfn))
1713 continue;
1714 }
1715
1716 for (i = 0; i < n_pcimio_boards; i++) {
1717 if (mite_device_id(mite) == ni_boards[i].device_id) {
1718 dev->board_ptr = ni_boards + i;
1719 devpriv->mite = mite;
1720
1721 return 0;
1722 }
1723 }
1724 }
1725 printk("no device found\n");
1726 mite_list_devices();
1727 return -EIO;
1728}
1729
34c43922 1730static int pcimio_ai_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e
DS		 1731 unsigned long new_size)
1732{
1733 int ret;
1734
1735 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1736 if (ret < 0)
1737 return ret;
1738
1739 return 0;
1740}
1741
34c43922 1742static int pcimio_ao_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e
DS		 1743 unsigned long new_size)
1744{
1745 int ret;
1746
1747 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1748 if (ret < 0)
1749 return ret;
1750
1751 return 0;
1752}
1753
34c43922 1754static int pcimio_gpct0_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e
DS		 1755 unsigned long new_size)
1756{
1757 int ret;
1758
1759 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1760 if (ret < 0)
1761 return ret;
1762
1763 return 0;
1764}
1765
34c43922 1766static int pcimio_gpct1_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e
DS		 1767 unsigned long new_size)
1768{
1769 int ret;
1770
1771 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1772 if (ret < 0)
1773 return ret;
1774
1775 return 0;
1776}
1777
34c43922 1778static int pcimio_dio_change(struct comedi_device * dev, struct comedi_subdevice * s,
c4beb34e
DS		 1779 unsigned long new_size)
1780{
1781 int ret;
1782
1783 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1784 if (ret < 0)
1785 return ret;
1786
1787 return 0;
1788}
kernel source for telekom puls (alcatel/mediatek)