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staging: comedi, remove interrupt.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_labpc.c
CommitLineData
124b13b2
FMH		 1/*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20************************************************************************
21*/
22/*
23Driver: ni_labpc
24Description: National Instruments Lab-PC (& compatibles)
25Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28Status: works
29
30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31and analog references will work, the available ranges/arefs will
32depend on how you have configured the jumpers on your board
33(see your owner's manual).
34
35Kernel-level ISA plug-and-play support for the lab-pc-1200
36boards has not
37yet been added to the driver, mainly due to the fact that
38I don't know the device id numbers. If you have one
39of these boards,
40please file a bug report at https://bugs.comedi.org/
41so I can get the necessary information from you.
42
43The 1200 series boards have onboard calibration dacs for correcting
44analog input/output offsets and gains. The proper settings for these
45caldacs are stored on the board's eeprom. To read the caldac values
46from the eeprom and store them into a file that can be then be used by
47comedilib, use the comedi_calibrate program.
48
49Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58The Lab-pc+ has quirky chanlist requirements
59when scanning multiple channels. Multiple channel scan
60sequence must start at highest channel, then decrement down to
61channel 0. The rest of the cards can scan down like lab-pc+ or scan
62up from channel zero. Chanlists consisting of all one channel
63are also legal, and allow you to pace conversions in bursts.
64
65*/
66
67/*
68
69NI manuals:
70341309a (labpc-1200 register manual)
71340914a (pci-1200)
72320502b (lab-pc+)
73
74*/
75
76#undef LABPC_DEBUG
f6b49620 77/* #define LABPC_DEBUG enable debugging messages */
124b13b2
FMH		 78
79#include "../comedidev.h"
80
81#include <linux/delay.h>
82#include <asm/dma.h>
83
84#include "8253.h"
85#include "8255.h"
86#include "mite.h"
87#include "comedi_fc.h"
88#include "ni_labpc.h"
89
90#define DRV_NAME "ni_labpc"
91
f6b49620
BP		 92#define LABPC_SIZE 32 /* size of io region used by board */
93#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */
124b13b2
FMH		 94
95/* Registers for the lab-pc+ */
96
f6b49620 97/* write-only registers */
124b13b2
FMH		 98#define COMMAND1_REG 0x0
99#define ADC_GAIN_MASK (0x7 << 4)
100#define ADC_CHAN_BITS(x) ((x) & 0x7)
f6b49620 101#define ADC_SCAN_EN_BIT 0x80 /* enables multi channel scans */
124b13b2 102#define COMMAND2_REG 0x1
f6b49620
BP		 103#define PRETRIG_BIT 0x1 /* enable pretriggering (used in conjunction with SWTRIG) */
104#define HWTRIG_BIT 0x2 /* enable paced conversions on external trigger */
105#define SWTRIG_BIT 0x4 /* enable paced conversions */
106#define CASCADE_BIT 0x8 /* use two cascaded counters for pacing */
124b13b2
FMH		 107#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
108#define COMMAND3_REG 0x2
f6b49620
BP		 109#define DMA_EN_BIT 0x1 /* enable dma transfers */
110#define DIO_INTR_EN_BIT 0x2 /* enable interrupts for 8255 */
111#define DMATC_INTR_EN_BIT 0x4 /* enable dma terminal count interrupt */
112#define TIMER_INTR_EN_BIT 0x8 /* enable timer interrupt */
113#define ERR_INTR_EN_BIT 0x10 /* enable error interrupt */
114#define ADC_FNE_INTR_EN_BIT 0x20 /* enable fifo not empty interrupt */
124b13b2
FMH		 115#define ADC_CONVERT_REG 0x3
116#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
117#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
118#define ADC_CLEAR_REG 0x8
119#define DMATC_CLEAR_REG 0xa
120#define TIMER_CLEAR_REG 0xc
f6b49620
BP		 121#define COMMAND6_REG 0xe /* 1200 boards only */
122#define ADC_COMMON_BIT 0x1 /* select ground or common-mode reference */
123#define ADC_UNIP_BIT 0x2 /* adc unipolar */
124#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) /* dac unipolar */
125#define ADC_FHF_INTR_EN_BIT 0x20 /* enable fifo half full interrupt */
126#define A1_INTR_EN_BIT 0x40 /* enable interrupt on end of hardware count */
127#define ADC_SCAN_UP_BIT 0x80 /* scan up from channel zero instead of down to zero */
124b13b2 128#define COMMAND4_REG 0xf
f6b49620
BP		 129#define INTERVAL_SCAN_EN_BIT 0x1 /* enables 'interval' scanning */
130#define EXT_SCAN_EN_BIT 0x2 /* enables external signal on counter b1 output to trigger scan */
131#define EXT_CONVERT_OUT_BIT 0x4 /* chooses direction (output or input) for EXTCONV* line */
132#define ADC_DIFF_BIT 0x8 /* chooses differential inputs for adc (in conjunction with board jumper) */
124b13b2 133#define EXT_CONVERT_DISABLE_BIT 0x10
f6b49620
BP		 134#define COMMAND5_REG 0x1c /* 1200 boards only, calibration stuff */
135#define EEPROM_WRITE_UNPROTECT_BIT 0x4 /* enable eeprom for write */
136#define DITHER_EN_BIT 0x8 /* enable dithering */
137#define CALDAC_LOAD_BIT 0x10 /* load calibration dac */
138#define SCLOCK_BIT 0x20 /* serial clock - rising edge writes, falling edge reads */
139#define SDATA_BIT 0x40 /* serial data bit for writing to eeprom or calibration dacs */
140#define EEPROM_EN_BIT 0x80 /* enable eeprom for read/write */
124b13b2
FMH		 141#define INTERVAL_COUNT_REG 0x1e
142#define INTERVAL_LOAD_REG 0x1f
143#define INTERVAL_LOAD_BITS 0x1
144
f6b49620 145/* read-only registers */
124b13b2 146#define STATUS1_REG 0x0
f6b49620
BP		 147#define DATA_AVAIL_BIT 0x1 /* data is available in fifo */
148#define OVERRUN_BIT 0x2 /* overrun has occurred */
149#define OVERFLOW_BIT 0x4 /* fifo overflow */
150#define TIMER_BIT 0x8 /* timer interrupt has occured */
151#define DMATC_BIT 0x10 /* dma terminal count has occured */
152#define EXT_TRIG_BIT 0x40 /* external trigger has occured */
153#define STATUS2_REG 0x1d /* 1200 boards only */
154#define EEPROM_OUT_BIT 0x1 /* programmable eeprom serial output */
155#define A1_TC_BIT 0x2 /* counter A1 terminal count */
156#define FNHF_BIT 0x4 /* fifo not half full */
124b13b2
FMH		 157#define ADC_FIFO_REG 0xa
158
159#define DIO_BASE_REG 0x10
160#define COUNTER_A_BASE_REG 0x14
161#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
f6b49620
BP		 162#define INIT_A0_BITS 0x14 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
163#define INIT_A1_BITS 0x70 /* put hardware conversion counter output in harmless state (a1 mode 0) */
124b13b2
FMH		 164#define COUNTER_B_BASE_REG 0x18
165
0707bb04 166static int labpc_attach(struct comedi_device * dev, struct comedi_devconfig * it);
34c43922 167static int labpc_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
70265d24 168static irqreturn_t labpc_interrupt(int irq, void *d);
71b5f4f1
BP		 169static int labpc_drain_fifo(struct comedi_device * dev);
170static void labpc_drain_dma(struct comedi_device * dev);
171static void handle_isa_dma(struct comedi_device * dev);
172static void labpc_drain_dregs(struct comedi_device * dev);
34c43922 173static int labpc_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
ea6d0d4c 174 struct comedi_cmd * cmd);
34c43922
BP		 175static int labpc_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
176static int labpc_ai_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 177 struct comedi_insn * insn, unsigned int * data);
34c43922 178static int labpc_ao_winsn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 179 struct comedi_insn * insn, unsigned int * data);
34c43922 180static int labpc_ao_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 181 struct comedi_insn * insn, unsigned int * data);
34c43922 182static int labpc_calib_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 183 struct comedi_insn * insn, unsigned int * data);
34c43922 184static int labpc_calib_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 185 struct comedi_insn * insn, unsigned int * data);
34c43922 186static int labpc_eeprom_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 187 struct comedi_insn * insn, unsigned int * data);
34c43922 188static int labpc_eeprom_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 189 struct comedi_insn * insn, unsigned int * data);
ea6d0d4c
BP		 190static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
191static void labpc_adc_timing(struct comedi_device * dev, struct comedi_cmd * cmd);
124b13b2 192#ifdef CONFIG_COMEDI_PCI
71b5f4f1 193static int labpc_find_device(struct comedi_device *dev, int bus, int slot);
124b13b2
FMH		 194#endif
195static int labpc_dio_mem_callback(int dir, int port, int data,
196 unsigned long arg);
71b5f4f1 197static void labpc_serial_out(struct comedi_device * dev, unsigned int value,
124b13b2 198 unsigned int num_bits);
71b5f4f1
BP		 199static unsigned int labpc_serial_in(struct comedi_device * dev);
200static unsigned int labpc_eeprom_read(struct comedi_device * dev,
124b13b2 201 unsigned int address);
71b5f4f1
BP		 202static unsigned int labpc_eeprom_read_status(struct comedi_device * dev);
203static unsigned int labpc_eeprom_write(struct comedi_device * dev,
124b13b2 204 unsigned int address, unsigned int value);
71b5f4f1 205static void write_caldac(struct comedi_device * dev, unsigned int channel,
124b13b2
FMH		 206 unsigned int value);
207
208enum scan_mode {
209 MODE_SINGLE_CHAN,
210 MODE_SINGLE_CHAN_INTERVAL,
211 MODE_MULT_CHAN_UP,
212 MODE_MULT_CHAN_DOWN,
213};
214
f6b49620 215/* analog input ranges */
124b13b2 216#define NUM_LABPC_PLUS_AI_RANGES 16
f6b49620 217/* indicates unipolar ranges */
124b13b2
FMH		 218static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
219 0,
220 0,
221 0,
222 0,
223 0,
224 0,
225 0,
226 0,
227 1,
228 1,
229 1,
230 1,
231 1,
232 1,
233 1,
234 1,
235};
236
f6b49620 237/* map range index to gain bits */
124b13b2
FMH		 238static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
239 0x00,
240 0x10,
241 0x20,
242 0x30,
243 0x40,
244 0x50,
245 0x60,
246 0x70,
247 0x00,
248 0x10,
249 0x20,
250 0x30,
251 0x40,
252 0x50,
253 0x60,
254 0x70,
255};
9ced1de6 256static const struct comedi_lrange range_labpc_plus_ai = {
124b13b2
FMH		 257 NUM_LABPC_PLUS_AI_RANGES,
258 {
259 BIP_RANGE(5),
260 BIP_RANGE(4),
261 BIP_RANGE(2.5),
262 BIP_RANGE(1),
263 BIP_RANGE(0.5),
264 BIP_RANGE(0.25),
265 BIP_RANGE(0.1),
266 BIP_RANGE(0.05),
267 UNI_RANGE(10),
268 UNI_RANGE(8),
269 UNI_RANGE(5),
270 UNI_RANGE(2),
271 UNI_RANGE(1),
272 UNI_RANGE(0.5),
273 UNI_RANGE(0.2),
274 UNI_RANGE(0.1),
275 }
276};
277
278#define NUM_LABPC_1200_AI_RANGES 14
f6b49620 279/* indicates unipolar ranges */
124b13b2
FMH		 280const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
281 0,
282 0,
283 0,
284 0,
285 0,
286 0,
287 0,
288 1,
289 1,
290 1,
291 1,
292 1,
293 1,
294 1,
295};
296
f6b49620 297/* map range index to gain bits */
124b13b2
FMH		 298const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
299 0x00,
300 0x20,
301 0x30,
302 0x40,
303 0x50,
304 0x60,
305 0x70,
306 0x00,
307 0x20,
308 0x30,
309 0x40,
310 0x50,
311 0x60,
312 0x70,
313};
9ced1de6 314const struct comedi_lrange range_labpc_1200_ai = {
124b13b2
FMH		 315 NUM_LABPC_1200_AI_RANGES,
316 {
317 BIP_RANGE(5),
318 BIP_RANGE(2.5),
319 BIP_RANGE(1),
320 BIP_RANGE(0.5),
321 BIP_RANGE(0.25),
322 BIP_RANGE(0.1),
323 BIP_RANGE(0.05),
324 UNI_RANGE(10),
325 UNI_RANGE(5),
326 UNI_RANGE(2),
327 UNI_RANGE(1),
328 UNI_RANGE(0.5),
329 UNI_RANGE(0.2),
330 UNI_RANGE(0.1),
331 }
332};
333
f6b49620 334/* analog output ranges */
124b13b2 335#define AO_RANGE_IS_UNIPOLAR 0x1
9ced1de6 336static const struct comedi_lrange range_labpc_ao = {
124b13b2
FMH		 337 2,
338 {
339 BIP_RANGE(5),
340 UNI_RANGE(10),
341 }
342};
343
344/* functions that do inb/outb and readb/writeb so we can use
345 * function pointers to decide which to use */
346static inline unsigned int labpc_inb(unsigned long address)
347{
348 return inb(address);
349}
350static inline void labpc_outb(unsigned int byte, unsigned long address)
351{
352 outb(byte, address);
353}
354static inline unsigned int labpc_readb(unsigned long address)
355{
356 return readb((void *)address);
357}
358static inline void labpc_writeb(unsigned int byte, unsigned long address)
359{
360 writeb(byte, (void *)address);
361}
362
9ad00740 363static const struct labpc_board_struct labpc_boards[] = {
124b13b2
FMH		 364 {
365 name: "lab-pc-1200",
366 ai_speed:10000,
367 bustype: isa_bustype,
368 register_layout:labpc_1200_layout,
369 has_ao: 1,
370 ai_range_table:&range_labpc_1200_ai,
371 ai_range_code:labpc_1200_ai_gain_bits,
372 ai_range_is_unipolar:labpc_1200_is_unipolar,
373 ai_scan_up:1,
374 memory_mapped_io:0,
375 },
376 {
377 name: "lab-pc-1200ai",
378 ai_speed:10000,
379 bustype: isa_bustype,
380 register_layout:labpc_1200_layout,
381 has_ao: 0,
382 ai_range_table:&range_labpc_1200_ai,
383 ai_range_code:labpc_1200_ai_gain_bits,
384 ai_range_is_unipolar:labpc_1200_is_unipolar,
385 ai_scan_up:1,
386 memory_mapped_io:0,
387 },
388 {
389 name: "lab-pc+",
390 ai_speed:12000,
391 bustype: isa_bustype,
392 register_layout:labpc_plus_layout,
393 has_ao: 1,
394 ai_range_table:&range_labpc_plus_ai,
395 ai_range_code:labpc_plus_ai_gain_bits,
396 ai_range_is_unipolar:labpc_plus_is_unipolar,
397 ai_scan_up:0,
398 memory_mapped_io:0,
399 },
400#ifdef CONFIG_COMEDI_PCI
401 {
402 name: "pci-1200",
403 device_id:0x161,
404 ai_speed:10000,
405 bustype: pci_bustype,
406 register_layout:labpc_1200_layout,
407 has_ao: 1,
408 ai_range_table:&range_labpc_1200_ai,
409 ai_range_code:labpc_1200_ai_gain_bits,
410 ai_range_is_unipolar:labpc_1200_is_unipolar,
411 ai_scan_up:1,
412 memory_mapped_io:1,
413 },
f6b49620 414 /* dummy entry so pci board works when comedi_config is passed driver name */
124b13b2
FMH		 415 {
416 .name = DRV_NAME,
417 .bustype = pci_bustype,
418 },
419#endif
420};
421
422/*
423 * Useful for shorthand access to the particular board structure
424 */
9ad00740 425#define thisboard ((struct labpc_board_struct *)dev->board_ptr)
124b13b2 426
f6b49620
BP		 427static const int dma_buffer_size = 0xff00; /* size in bytes of dma buffer */
428static const int sample_size = 2; /* 2 bytes per sample */
124b13b2 429
0a4eb4b6 430#define devpriv ((struct labpc_private *)dev->private)
124b13b2 431
139dfbdf 432static struct comedi_driver driver_labpc = {
124b13b2
FMH		 433 .driver_name = DRV_NAME,
434 .module = THIS_MODULE,
435 .attach = labpc_attach,
436 .detach = labpc_common_detach,
9ad00740 437 .num_names = sizeof(labpc_boards) / sizeof(struct labpc_board_struct),
124b13b2 438 .board_name = &labpc_boards[0].name,
9ad00740 439 .offset = sizeof(struct labpc_board_struct),
124b13b2
FMH		 440};
441
442#ifdef CONFIG_COMEDI_PCI
443static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
444 {PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
445 {0}
446};
447
448MODULE_DEVICE_TABLE(pci, labpc_pci_table);
449#endif /* CONFIG_COMEDI_PCI */
450
71b5f4f1 451static inline int labpc_counter_load(struct comedi_device * dev,
124b13b2
FMH		 452 unsigned long base_address, unsigned int counter_number,
453 unsigned int count, unsigned int mode)
454{
455 if (thisboard->memory_mapped_io)
456 return i8254_mm_load((void *)base_address, 0, counter_number,
457 count, mode);
458 else
459 return i8254_load(base_address, 0, counter_number, count, mode);
460}
461
71b5f4f1 462int labpc_common_attach(struct comedi_device * dev, unsigned long iobase,
124b13b2
FMH		 463 unsigned int irq, unsigned int dma_chan)
464{
34c43922 465 struct comedi_subdevice *s;
124b13b2
FMH		 466 int i;
467 unsigned long dma_flags, isr_flags;
468 short lsb, msb;
469
470 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name,
471 iobase);
472 if (irq) {
473 printk(", irq %u", irq);
474 }
475 if (dma_chan) {
476 printk(", dma %u", dma_chan);
477 }
478 printk("\n");
479
480 if (iobase == 0) {
481 printk("io base address is zero!\n");
482 return -EINVAL;
483 }
f6b49620 484 /* request io regions for isa boards */
124b13b2
FMH		 485 if (thisboard->bustype == isa_bustype) {
486 /* check if io addresses are available */
487 if (!request_region(iobase, LABPC_SIZE,
488 driver_labpc.driver_name)) {
489 printk("I/O port conflict\n");
490 return -EIO;
491 }
492 }
493 dev->iobase = iobase;
494
495 if (thisboard->memory_mapped_io) {
496 devpriv->read_byte = labpc_readb;
497 devpriv->write_byte = labpc_writeb;
498 } else {
499 devpriv->read_byte = labpc_inb;
500 devpriv->write_byte = labpc_outb;
501 }
f6b49620 502 /* initialize board's command registers */
124b13b2
FMH		 503 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
504 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
505 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
506 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
507 if (thisboard->register_layout == labpc_1200_layout) {
508 devpriv->write_byte(devpriv->command5_bits,
509 dev->iobase + COMMAND5_REG);
510 devpriv->write_byte(devpriv->command6_bits,
511 dev->iobase + COMMAND6_REG);
512 }
513
514 /* grab our IRQ */
515 if (irq) {
516 isr_flags = 0;
517 if (thisboard->bustype == pci_bustype)
518 isr_flags |= IRQF_SHARED;
519 if (comedi_request_irq(irq, labpc_interrupt, isr_flags,
520 driver_labpc.driver_name, dev)) {
521 printk("unable to allocate irq %u\n", irq);
522 return -EINVAL;
523 }
524 }
525 dev->irq = irq;
526
f6b49620 527 /* grab dma channel */
124b13b2
FMH		 528 if (dma_chan > 3) {
529 printk(" invalid dma channel %u\n", dma_chan);
530 return -EINVAL;
531 } else if (dma_chan) {
f6b49620 532 /* allocate dma buffer */
124b13b2
FMH		 533 devpriv->dma_buffer =
534 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
535 if (devpriv->dma_buffer == NULL) {
536 printk(" failed to allocate dma buffer\n");
537 return -ENOMEM;
538 }
539 if (request_dma(dma_chan, driver_labpc.driver_name)) {
540 printk(" failed to allocate dma channel %u\n",
541 dma_chan);
542 return -EINVAL;
543 }
544 devpriv->dma_chan = dma_chan;
545 dma_flags = claim_dma_lock();
546 disable_dma(devpriv->dma_chan);
547 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
548 release_dma_lock(dma_flags);
549 }
550
551 dev->board_name = thisboard->name;
552
553 if (alloc_subdevices(dev, 5) < 0)
554 return -ENOMEM;
555
556 /* analog input subdevice */
557 s = dev->subdevices + 0;
558 dev->read_subdev = s;
559 s->type = COMEDI_SUBD_AI;
560 s->subdev_flags =
561 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF |
562 SDF_CMD_READ;
563 s->n_chan = 8;
564 s->len_chanlist = 8;
f6b49620 565 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
124b13b2
FMH		 566 s->range_table = thisboard->ai_range_table;
567 s->do_cmd = labpc_ai_cmd;
568 s->do_cmdtest = labpc_ai_cmdtest;
569 s->insn_read = labpc_ai_rinsn;
570 s->cancel = labpc_cancel;
571
572 /* analog output */
573 s = dev->subdevices + 1;
574 if (thisboard->has_ao) {
575/* Could provide command support, except it only has a one sample
576 * hardware buffer for analog output and no underrun flag. */
577 s->type = COMEDI_SUBD_AO;
578 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
579 s->n_chan = NUM_AO_CHAN;
f6b49620 580 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
124b13b2
FMH		 581 s->range_table = &range_labpc_ao;
582 s->insn_read = labpc_ao_rinsn;
583 s->insn_write = labpc_ao_winsn;
584 /* initialize analog outputs to a known value */
585 for (i = 0; i < s->n_chan; i++) {
586 devpriv->ao_value[i] = s->maxdata / 2;
587 lsb = devpriv->ao_value[i] & 0xff;
588 msb = (devpriv->ao_value[i] >> 8) & 0xff;
589 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
590 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
591 }
592 } else {
593 s->type = COMEDI_SUBD_UNUSED;
594 }
595
596 /* 8255 dio */
597 s = dev->subdevices + 2;
f6b49620 598 /* if board uses io memory we have to give a custom callback function to the 8255 driver */
124b13b2
FMH		 599 if (thisboard->memory_mapped_io)
600 subdev_8255_init(dev, s, labpc_dio_mem_callback,
601 (unsigned long)(dev->iobase + DIO_BASE_REG));
602 else
603 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
604
f6b49620 605 /* calibration subdevices for boards that have one */
124b13b2
FMH		 606 s = dev->subdevices + 3;
607 if (thisboard->register_layout == labpc_1200_layout) {
608 s->type = COMEDI_SUBD_CALIB;
609 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
610 s->n_chan = 16;
611 s->maxdata = 0xff;
612 s->insn_read = labpc_calib_read_insn;
613 s->insn_write = labpc_calib_write_insn;
614
615 for (i = 0; i < s->n_chan; i++)
616 write_caldac(dev, i, s->maxdata / 2);
617 } else
618 s->type = COMEDI_SUBD_UNUSED;
619
620 /* EEPROM */
621 s = dev->subdevices + 4;
622 if (thisboard->register_layout == labpc_1200_layout) {
623 s->type = COMEDI_SUBD_MEMORY;
624 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
625 s->n_chan = EEPROM_SIZE;
626 s->maxdata = 0xff;
627 s->insn_read = labpc_eeprom_read_insn;
628 s->insn_write = labpc_eeprom_write_insn;
629
630 for (i = 0; i < EEPROM_SIZE; i++) {
631 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
632 }
633#ifdef LABPC_DEBUG
634 printk(" eeprom:");
635 for (i = 0; i < EEPROM_SIZE; i++) {
636 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
637 }
638 printk("\n");
639#endif
640 } else
641 s->type = COMEDI_SUBD_UNUSED;
642
643 return 0;
644}
645
0707bb04 646static int labpc_attach(struct comedi_device * dev, struct comedi_devconfig * it)
124b13b2
FMH		 647{
648 unsigned long iobase = 0;
649 unsigned int irq = 0;
650 unsigned int dma_chan = 0;
651#ifdef CONFIG_COMEDI_PCI
652 int retval;
653#endif
654
655 /* allocate and initialize dev->private */
0a4eb4b6 656 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
124b13b2
FMH		 657 return -ENOMEM;
658
f6b49620 659 /* get base address, irq etc. based on bustype */
124b13b2
FMH		 660 switch (thisboard->bustype) {
661 case isa_bustype:
662 iobase = it->options[0];
663 irq = it->options[1];
664 dma_chan = it->options[2];
665 break;
666 case pci_bustype:
667#ifdef CONFIG_COMEDI_PCI
668 retval = labpc_find_device(dev, it->options[0], it->options[1]);
669 if (retval < 0) {
670 return retval;
671 }
672 retval = mite_setup(devpriv->mite);
673 if (retval < 0)
674 return retval;
675 iobase = (unsigned long)devpriv->mite->daq_io_addr;
676 irq = mite_irq(devpriv->mite);
677#else
678 printk(" this driver has not been built with PCI support.\n");
679 return -EINVAL;
680#endif
681 break;
682 case pcmcia_bustype:
683 printk(" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
684 return -EINVAL;
685 break;
686 default:
687 printk("bug! couldn't determine board type\n");
688 return -EINVAL;
689 break;
690 }
691
692 return labpc_common_attach(dev, iobase, irq, dma_chan);
693}
694
f6b49620 695/* adapted from ni_pcimio for finding mite based boards (pc-1200) */
124b13b2 696#ifdef CONFIG_COMEDI_PCI
71b5f4f1 697static int labpc_find_device(struct comedi_device *dev, int bus, int slot)
124b13b2
FMH		 698{
699 struct mite_struct *mite;
700 int i;
701 for (mite = mite_devices; mite; mite = mite->next) {
702 if (mite->used)
703 continue;
f6b49620 704 /* if bus/slot are specified then make sure we have the right bus/slot */
124b13b2
FMH		 705 if (bus || slot) {
706 if (bus != mite->pcidev->bus->number
707 || slot != PCI_SLOT(mite->pcidev->devfn))
708 continue;
709 }
710 for (i = 0; i < driver_labpc.num_names; i++) {
711 if (labpc_boards[i].bustype != pci_bustype)
712 continue;
713 if (mite_device_id(mite) == labpc_boards[i].device_id) {
714 devpriv->mite = mite;
f6b49620 715 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */
124b13b2
FMH		 716 dev->board_ptr = &labpc_boards[i];
717 return 0;
718 }
719 }
720 }
721 printk("no device found\n");
722 mite_list_devices();
723 return -EIO;
724}
725#endif
726
71b5f4f1 727int labpc_common_detach(struct comedi_device * dev)
124b13b2
FMH		 728{
729 printk("comedi%d: ni_labpc: detach\n", dev->minor);
730
731 if (dev->subdevices)
732 subdev_8255_cleanup(dev, dev->subdevices + 2);
733
734 /* only free stuff if it has been allocated by _attach */
735 if (devpriv->dma_buffer)
736 kfree(devpriv->dma_buffer);
737 if (devpriv->dma_chan)
738 free_dma(devpriv->dma_chan);
739 if (dev->irq)
740 comedi_free_irq(dev->irq, dev);
741 if (thisboard->bustype == isa_bustype && dev->iobase)
742 release_region(dev->iobase, LABPC_SIZE);
743#ifdef CONFIG_COMEDI_PCI
744 if (devpriv->mite)
745 mite_unsetup(devpriv->mite);
746#endif
747
748 return 0;
749};
750
71b5f4f1 751static void labpc_clear_adc_fifo(const struct comedi_device * dev)
124b13b2
FMH		 752{
753 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
754 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
755 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
756}
757
34c43922 758static int labpc_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
124b13b2
FMH		 759{
760 unsigned long flags;
761
762 comedi_spin_lock_irqsave(&dev->spinlock, flags);
763 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
764 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
765 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
766
767 devpriv->command3_bits = 0;
768 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
769
770 return 0;
771}
772
ea6d0d4c 773static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd * cmd)
124b13b2
FMH		 774{
775 if (cmd->chanlist_len == 1)
776 return MODE_SINGLE_CHAN;
777
778 /* chanlist may be NULL during cmdtest. */
779 if (cmd->chanlist == NULL)
780 return MODE_MULT_CHAN_UP;
781
782 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
783 return MODE_SINGLE_CHAN_INTERVAL;
784
785 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
786 return MODE_MULT_CHAN_UP;
787
788 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
789 return MODE_MULT_CHAN_DOWN;
790
791 rt_printk("ni_labpc: bug! this should never happen\n");
792
793 return 0;
794}
795
71b5f4f1 796static int labpc_ai_chanlist_invalid(const struct comedi_device * dev,
ea6d0d4c 797 const struct comedi_cmd * cmd)
124b13b2
FMH		 798{
799 int mode, channel, range, aref, i;
800
801 if (cmd->chanlist == NULL)
802 return 0;
803
804 mode = labpc_ai_scan_mode(cmd);
805
806 if (mode == MODE_SINGLE_CHAN)
807 return 0;
808
809 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
810 if (cmd->chanlist_len > 0xff) {
811 comedi_error(dev,
812 "ni_labpc: chanlist too long for single channel interval mode\n");
813 return 1;
814 }
815 }
816
817 channel = CR_CHAN(cmd->chanlist[0]);
818 range = CR_RANGE(cmd->chanlist[0]);
819 aref = CR_AREF(cmd->chanlist[0]);
820
821 for (i = 0; i < cmd->chanlist_len; i++) {
822
823 switch (mode) {
824 case MODE_SINGLE_CHAN_INTERVAL:
825 if (CR_CHAN(cmd->chanlist[i]) != channel) {
826 comedi_error(dev,
827 "channel scanning order specified in chanlist is not supported by hardware.\n");
828 return 1;
829 }
830 break;
831 case MODE_MULT_CHAN_UP:
832 if (CR_CHAN(cmd->chanlist[i]) != i) {
833 comedi_error(dev,
834 "channel scanning order specified in chanlist is not supported by hardware.\n");
835 return 1;
836 }
837 break;
838 case MODE_MULT_CHAN_DOWN:
839 if (CR_CHAN(cmd->chanlist[i]) !=
840 cmd->chanlist_len - i - 1) {
841 comedi_error(dev,
842 "channel scanning order specified in chanlist is not supported by hardware.\n");
843 return 1;
844 }
845 break;
846 default:
847 rt_printk("ni_labpc: bug! in chanlist check\n");
848 return 1;
849 break;
850 }
851
852 if (CR_RANGE(cmd->chanlist[i]) != range) {
853 comedi_error(dev,
854 "entries in chanlist must all have the same range\n");
855 return 1;
856 }
857
858 if (CR_AREF(cmd->chanlist[i]) != aref) {
859 comedi_error(dev,
860 "entries in chanlist must all have the same reference\n");
861 return 1;
862 }
863 }
864
865 return 0;
866}
867
ea6d0d4c 868static int labpc_use_continuous_mode(const struct comedi_cmd * cmd)
124b13b2
FMH		 869{
870 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
871 return 1;
872
873 if (cmd->scan_begin_src == TRIG_FOLLOW)
874 return 1;
875
876 return 0;
877}
878
ea6d0d4c 879static unsigned int labpc_ai_convert_period(const struct comedi_cmd * cmd)
124b13b2
FMH		 880{
881 if (cmd->convert_src != TRIG_TIMER)
882 return 0;
883
884 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
885 cmd->scan_begin_src == TRIG_TIMER)
886 return cmd->scan_begin_arg;
887
888 return cmd->convert_arg;
889}
890
ea6d0d4c 891static void labpc_set_ai_convert_period(struct comedi_cmd * cmd, unsigned int ns)
124b13b2
FMH		 892{
893 if (cmd->convert_src != TRIG_TIMER)
894 return;
895
896 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
897 cmd->scan_begin_src == TRIG_TIMER) {
898 cmd->scan_begin_arg = ns;
899 if (cmd->convert_arg > cmd->scan_begin_arg)
900 cmd->convert_arg = cmd->scan_begin_arg;
901 } else
902 cmd->convert_arg = ns;
903}
904
ea6d0d4c 905static unsigned int labpc_ai_scan_period(const struct comedi_cmd * cmd)
124b13b2
FMH		 906{
907 if (cmd->scan_begin_src != TRIG_TIMER)
908 return 0;
909
910 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
911 cmd->convert_src == TRIG_TIMER)
912 return 0;
913
914 return cmd->scan_begin_arg;
915}
916
ea6d0d4c 917static void labpc_set_ai_scan_period(struct comedi_cmd * cmd, unsigned int ns)
124b13b2
FMH		 918{
919 if (cmd->scan_begin_src != TRIG_TIMER)
920 return;
921
922 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
923 cmd->convert_src == TRIG_TIMER)
924 return;
925
926 cmd->scan_begin_arg = ns;
927}
928
34c43922 929static int labpc_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
ea6d0d4c 930 struct comedi_cmd * cmd)
124b13b2
FMH		 931{
932 int err = 0;
933 int tmp, tmp2;
934 int stop_mask;
935
936 /* step 1: make sure trigger sources are trivially valid */
937
938 tmp = cmd->start_src;
939 cmd->start_src &= TRIG_NOW | TRIG_EXT;
940 if (!cmd->start_src || tmp != cmd->start_src)
941 err++;
942
943 tmp = cmd->scan_begin_src;
944 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
945 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
946 err++;
947
948 tmp = cmd->convert_src;
949 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
950 if (!cmd->convert_src || tmp != cmd->convert_src)
951 err++;
952
953 tmp = cmd->scan_end_src;
954 cmd->scan_end_src &= TRIG_COUNT;
955 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
956 err++;
957
958 tmp = cmd->stop_src;
959 stop_mask = TRIG_COUNT | TRIG_NONE;
960 if (thisboard->register_layout == labpc_1200_layout)
961 stop_mask |= TRIG_EXT;
962 cmd->stop_src &= stop_mask;
963 if (!cmd->stop_src || tmp != cmd->stop_src)
964 err++;
965
966 if (err)
967 return 1;
968
969 /* step 2: make sure trigger sources are unique and mutually compatible */
970
971 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
972 err++;
973 if (cmd->scan_begin_src != TRIG_TIMER &&
974 cmd->scan_begin_src != TRIG_FOLLOW &&
975 cmd->scan_begin_src != TRIG_EXT)
976 err++;
977 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
978 err++;
979 if (cmd->stop_src != TRIG_COUNT &&
980 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
981 err++;
982
f6b49620 983 /* can't have external stop and start triggers at once */
124b13b2
FMH		 984 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
985 err++;
986
987 if (err)
988 return 2;
989
990 /* step 3: make sure arguments are trivially compatible */
991
992 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
993 cmd->start_arg = 0;
994 err++;
995 }
996
997 if (!cmd->chanlist_len) {
998 err++;
999 }
1000 if (cmd->scan_end_arg != cmd->chanlist_len) {
1001 cmd->scan_end_arg = cmd->chanlist_len;
1002 err++;
1003 }
1004
1005 if (cmd->convert_src == TRIG_TIMER) {
1006 if (cmd->convert_arg < thisboard->ai_speed) {
1007 cmd->convert_arg = thisboard->ai_speed;
1008 err++;
1009 }
1010 }
f6b49620 1011 /* make sure scan timing is not too fast */
124b13b2
FMH		 1012 if (cmd->scan_begin_src == TRIG_TIMER) {
1013 if (cmd->convert_src == TRIG_TIMER &&
1014 cmd->scan_begin_arg <
1015 cmd->convert_arg * cmd->chanlist_len) {
1016 cmd->scan_begin_arg =
1017 cmd->convert_arg * cmd->chanlist_len;
1018 err++;
1019 }
1020 if (cmd->scan_begin_arg <
1021 thisboard->ai_speed * cmd->chanlist_len) {
1022 cmd->scan_begin_arg =
1023 thisboard->ai_speed * cmd->chanlist_len;
1024 err++;
1025 }
1026 }
f6b49620 1027 /* stop source */
124b13b2
FMH		 1028 switch (cmd->stop_src) {
1029 case TRIG_COUNT:
1030 if (!cmd->stop_arg) {
1031 cmd->stop_arg = 1;
1032 err++;
1033 }
1034 break;
1035 case TRIG_NONE:
1036 if (cmd->stop_arg != 0) {
1037 cmd->stop_arg = 0;
1038 err++;
1039 }
1040 break;
f6b49620 1041 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */
124b13b2
FMH		 1042 default:
1043 break;
1044 }
1045
1046 if (err)
1047 return 3;
1048
1049 /* step 4: fix up any arguments */
1050
1051 tmp = cmd->convert_arg;
1052 tmp2 = cmd->scan_begin_arg;
1053 labpc_adc_timing(dev, cmd);
1054 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1055 err++;
1056
1057 if (err)
1058 return 4;
1059
1060 if (labpc_ai_chanlist_invalid(dev, cmd))
1061 return 5;
1062
1063 return 0;
1064}
1065
34c43922 1066static int labpc_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
124b13b2
FMH		 1067{
1068 int channel, range, aref;
1069 unsigned long irq_flags;
1070 int ret;
d163679c 1071 struct comedi_async *async = s->async;
ea6d0d4c 1072 struct comedi_cmd *cmd = &async->cmd;
124b13b2
FMH		 1073 enum transfer_type xfer;
1074 unsigned long flags;
1075
1076 if (!dev->irq) {
1077 comedi_error(dev, "no irq assigned, cannot perform command");
1078 return -1;
1079 }
1080
1081 range = CR_RANGE(cmd->chanlist[0]);
1082 aref = CR_AREF(cmd->chanlist[0]);
1083
f6b49620 1084 /* make sure board is disabled before setting up aquisition */
124b13b2
FMH		 1085 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1086 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1087 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1088 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1089
1090 devpriv->command3_bits = 0;
1091 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1092
f6b49620 1093 /* initialize software conversion count */
124b13b2
FMH		 1094 if (cmd->stop_src == TRIG_COUNT) {
1095 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1096 }
f6b49620 1097 /* setup hardware conversion counter */
124b13b2 1098 if (cmd->stop_src == TRIG_EXT) {
f6b49620 1099 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */
124b13b2
FMH		 1100 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1101 1, 3, 0);
1102 if (ret < 0) {
1103 comedi_error(dev, "error loading counter a1");
1104 return -1;
1105 }
f6b49620 1106 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */
124b13b2
FMH		 1107 devpriv->write_byte(INIT_A1_BITS,
1108 dev->iobase + COUNTER_A_CONTROL_REG);
1109
f6b49620
BP		 1110 /* figure out what method we will use to transfer data */
1111 if (devpriv->dma_chan && /* need a dma channel allocated */
1112 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */
124b13b2 1113 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
f6b49620 1114 /* only available on the isa boards */
124b13b2
FMH		 1115 thisboard->bustype == isa_bustype) {
1116 xfer = isa_dma_transfer;
f6b49620
BP		 1117 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */
1118 /* wake-end-of-scan should interrupt on fifo not empty */
124b13b2 1119 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
f6b49620 1120 /* make sure we are taking more than just a few points */
124b13b2
FMH		 1121 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1122 xfer = fifo_half_full_transfer;
1123 } else
1124 xfer = fifo_not_empty_transfer;
1125 devpriv->current_transfer = xfer;
1126
f6b49620 1127 /* setup command6 register for 1200 boards */
124b13b2 1128 if (thisboard->register_layout == labpc_1200_layout) {
f6b49620 1129 /* reference inputs to ground or common? */
124b13b2
FMH		 1130 if (aref != AREF_GROUND)
1131 devpriv->command6_bits |= ADC_COMMON_BIT;
1132 else
1133 devpriv->command6_bits &= ~ADC_COMMON_BIT;
f6b49620 1134 /* bipolar or unipolar range? */
124b13b2
FMH		 1135 if (thisboard->ai_range_is_unipolar[range])
1136 devpriv->command6_bits |= ADC_UNIP_BIT;
1137 else
1138 devpriv->command6_bits &= ~ADC_UNIP_BIT;
f6b49620 1139 /* interrupt on fifo half full? */
124b13b2
FMH		 1140 if (xfer == fifo_half_full_transfer)
1141 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1142 else
1143 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
f6b49620 1144 /* enable interrupt on counter a1 terminal count? */
124b13b2
FMH		 1145 if (cmd->stop_src == TRIG_EXT)
1146 devpriv->command6_bits |= A1_INTR_EN_BIT;
1147 else
1148 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
f6b49620 1149 /* are we scanning up or down through channels? */
124b13b2
FMH		 1150 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1151 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1152 else
1153 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
f6b49620 1154 /* write to register */
124b13b2
FMH		 1155 devpriv->write_byte(devpriv->command6_bits,
1156 dev->iobase + COMMAND6_REG);
1157 }
1158
1159 /* setup channel list, etc (command1 register) */
1160 devpriv->command1_bits = 0;
1161 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1162 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1163 else
1164 channel = CR_CHAN(cmd->chanlist[0]);
f6b49620 1165 /* munge channel bits for differential / scan disabled mode */
124b13b2
FMH		 1166 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1167 channel *= 2;
1168 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1169 devpriv->command1_bits |= thisboard->ai_range_code[range];
1170 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
f6b49620 1171 /* manual says to set scan enable bit on second pass */
124b13b2
FMH		 1172 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1173 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1174 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1175 /* need a brief delay before enabling scan, or scan list will get screwed when you switch
1176 * between scan up to scan down mode - dunno why */
1177 comedi_udelay(1);
1178 devpriv->write_byte(devpriv->command1_bits,
1179 dev->iobase + COMMAND1_REG);
1180 }
f6b49620 1181 /* setup any external triggering/pacing (command4 register) */
124b13b2
FMH		 1182 devpriv->command4_bits = 0;
1183 if (cmd->convert_src != TRIG_EXT)
1184 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1185 /* XXX should discard first scan when using interval scanning
1186 * since manual says it is not synced with scan clock */
1187 if (labpc_use_continuous_mode(cmd) == 0) {
1188 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1189 if (cmd->scan_begin_src == TRIG_EXT)
1190 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1191 }
f6b49620 1192 /* single-ended/differential */
124b13b2
FMH		 1193 if (aref == AREF_DIFF)
1194 devpriv->command4_bits |= ADC_DIFF_BIT;
1195 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1196
1197 devpriv->write_byte(cmd->chanlist_len,
1198 dev->iobase + INTERVAL_COUNT_REG);
f6b49620 1199 /* load count */
124b13b2
FMH		 1200 devpriv->write_byte(INTERVAL_LOAD_BITS,
1201 dev->iobase + INTERVAL_LOAD_REG);
1202
1203 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
f6b49620 1204 /* set up pacing */
124b13b2 1205 labpc_adc_timing(dev, cmd);
f6b49620 1206 /* load counter b0 in mode 3 */
124b13b2
FMH		 1207 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1208 0, devpriv->divisor_b0, 3);
1209 if (ret < 0) {
1210 comedi_error(dev, "error loading counter b0");
1211 return -1;
1212 }
1213 }
f6b49620 1214 /* set up conversion pacing */
124b13b2 1215 if (labpc_ai_convert_period(cmd)) {
f6b49620 1216 /* load counter a0 in mode 2 */
124b13b2
FMH		 1217 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1218 0, devpriv->divisor_a0, 2);
1219 if (ret < 0) {
1220 comedi_error(dev, "error loading counter a0");
1221 return -1;
1222 }
1223 } else
1224 devpriv->write_byte(INIT_A0_BITS,
1225 dev->iobase + COUNTER_A_CONTROL_REG);
1226
f6b49620 1227 /* set up scan pacing */
124b13b2 1228 if (labpc_ai_scan_period(cmd)) {
f6b49620 1229 /* load counter b1 in mode 2 */
124b13b2
FMH		 1230 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1231 1, devpriv->divisor_b1, 2);
1232 if (ret < 0) {
1233 comedi_error(dev, "error loading counter b1");
1234 return -1;
1235 }
1236 }
1237
1238 labpc_clear_adc_fifo(dev);
1239
f6b49620 1240 /* set up dma transfer */
124b13b2
FMH		 1241 if (xfer == isa_dma_transfer) {
1242 irq_flags = claim_dma_lock();
1243 disable_dma(devpriv->dma_chan);
1244 /* clear flip-flop to make sure 2-byte registers for
1245 * count and address get set correctly */
1246 clear_dma_ff(devpriv->dma_chan);
1247 set_dma_addr(devpriv->dma_chan,
1248 virt_to_bus(devpriv->dma_buffer));
f6b49620 1249 /* set appropriate size of transfer */
124b13b2
FMH		 1250 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1251 if (cmd->stop_src == TRIG_COUNT &&
1252 devpriv->count * sample_size <
1253 devpriv->dma_transfer_size) {
1254 devpriv->dma_transfer_size =
1255 devpriv->count * sample_size;
1256 }
1257 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1258 enable_dma(devpriv->dma_chan);
1259 release_dma_lock(irq_flags);
f6b49620 1260 /* enable board's dma */
124b13b2
FMH		 1261 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1262 } else
1263 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1264
f6b49620 1265 /* enable error interrupts */
124b13b2 1266 devpriv->command3_bits |= ERR_INTR_EN_BIT;
f6b49620 1267 /* enable fifo not empty interrupt? */
124b13b2
FMH		 1268 if (xfer == fifo_not_empty_transfer)
1269 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1270 else
1271 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1272 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1273
f6b49620 1274 /* startup aquisition */
124b13b2 1275
f6b49620
BP		 1276 /* command2 reg */
1277 /* use 2 cascaded counters for pacing */
124b13b2
FMH		 1278 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1279 devpriv->command2_bits |= CASCADE_BIT;
1280 switch (cmd->start_src) {
1281 case TRIG_EXT:
1282 devpriv->command2_bits |= HWTRIG_BIT;
1283 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1284 break;
1285 case TRIG_NOW:
1286 devpriv->command2_bits |= SWTRIG_BIT;
1287 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1288 break;
1289 default:
1290 comedi_error(dev, "bug with start_src");
1291 return -1;
1292 break;
1293 }
1294 switch (cmd->stop_src) {
1295 case TRIG_EXT:
1296 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1297 break;
1298 case TRIG_COUNT:
1299 case TRIG_NONE:
1300 break;
1301 default:
1302 comedi_error(dev, "bug with stop_src");
1303 return -1;
1304 }
1305 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1306 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1307
1308 return 0;
1309}
1310
1311/* interrupt service routine */
70265d24 1312static irqreturn_t labpc_interrupt(int irq, void *d)
124b13b2 1313{
71b5f4f1 1314 struct comedi_device *dev = d;
34c43922 1315 struct comedi_subdevice *s = dev->read_subdev;
d163679c 1316 struct comedi_async *async;
ea6d0d4c 1317 struct comedi_cmd *cmd;
124b13b2
FMH		 1318
1319 if (dev->attached == 0) {
1320 comedi_error(dev, "premature interrupt");
1321 return IRQ_HANDLED;
1322 }
1323
1324 async = s->async;
1325 cmd = &async->cmd;
1326 async->events = 0;
1327
f6b49620 1328 /* read board status */
124b13b2
FMH		 1329 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1330 if (thisboard->register_layout == labpc_1200_layout)
1331 devpriv->status2_bits =
1332 devpriv->read_byte(dev->iobase + STATUS2_REG);
1333
1334 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1335 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1336 && (devpriv->status2_bits & A1_TC_BIT) == 0
1337 && (devpriv->status2_bits & FNHF_BIT)) {
1338 return IRQ_NONE;
1339 }
1340
1341 if (devpriv->status1_bits & OVERRUN_BIT) {
f6b49620 1342 /* clear error interrupt */
124b13b2
FMH		 1343 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1344 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1345 comedi_event(dev, s);
1346 comedi_error(dev, "overrun");
1347 return IRQ_HANDLED;
1348 }
1349
1350 if (devpriv->current_transfer == isa_dma_transfer) {
f6b49620 1351 /* if a dma terminal count of external stop trigger has occurred */
124b13b2
FMH		 1352 if (devpriv->status1_bits & DMATC_BIT ||
1353 (thisboard->register_layout == labpc_1200_layout
1354 && devpriv->status2_bits & A1_TC_BIT)) {
1355 handle_isa_dma(dev);
1356 }
1357 } else
1358 labpc_drain_fifo(dev);
1359
1360 if (devpriv->status1_bits & TIMER_BIT) {
1361 comedi_error(dev, "handled timer interrupt?");
f6b49620 1362 /* clear it */
124b13b2
FMH		 1363 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1364 }
1365
1366 if (devpriv->status1_bits & OVERFLOW_BIT) {
f6b49620 1367 /* clear error interrupt */
124b13b2
FMH		 1368 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1369 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1370 comedi_event(dev, s);
1371 comedi_error(dev, "overflow");
1372 return IRQ_HANDLED;
1373 }
f6b49620 1374 /* handle external stop trigger */
124b13b2
FMH		 1375 if (cmd->stop_src == TRIG_EXT) {
1376 if (devpriv->status2_bits & A1_TC_BIT) {
1377 labpc_drain_dregs(dev);
1378 labpc_cancel(dev, s);
1379 async->events |= COMEDI_CB_EOA;
1380 }
1381 }
1382
1383 /* TRIG_COUNT end of acquisition */
1384 if (cmd->stop_src == TRIG_COUNT) {
1385 if (devpriv->count == 0) {
1386 labpc_cancel(dev, s);
1387 async->events |= COMEDI_CB_EOA;
1388 }
1389 }
1390
1391 comedi_event(dev, s);
1392 return IRQ_HANDLED;
1393}
1394
f6b49620 1395/* read all available samples from ai fifo */
71b5f4f1 1396static int labpc_drain_fifo(struct comedi_device * dev)
124b13b2
FMH		 1397{
1398 unsigned int lsb, msb;
790c5541 1399 short data;
d163679c 1400 struct comedi_async *async = dev->read_subdev->async;
124b13b2
FMH		 1401 const int timeout = 10000;
1402 unsigned int i;
1403
1404 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1405
1406 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1407 i++) {
f6b49620 1408 /* quit if we have all the data we want */
124b13b2
FMH		 1409 if (async->cmd.stop_src == TRIG_COUNT) {
1410 if (devpriv->count == 0)
1411 break;
1412 devpriv->count--;
1413 }
1414 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1415 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1416 data = (msb << 8) | lsb;
1417 cfc_write_to_buffer(dev->read_subdev, data);
1418 devpriv->status1_bits =
1419 devpriv->read_byte(dev->iobase + STATUS1_REG);
1420 }
1421 if (i == timeout) {
1422 comedi_error(dev, "ai timeout, fifo never empties");
1423 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1424 return -1;
1425 }
1426
1427 return 0;
1428}
1429
71b5f4f1 1430static void labpc_drain_dma(struct comedi_device * dev)
124b13b2 1431{
34c43922 1432 struct comedi_subdevice *s = dev->read_subdev;
d163679c 1433 struct comedi_async *async = s->async;
124b13b2
FMH		 1434 int status;
1435 unsigned long flags;
1436 unsigned int max_points, num_points, residue, leftover;
1437 int i;
1438
1439 status = devpriv->status1_bits;
1440
1441 flags = claim_dma_lock();
1442 disable_dma(devpriv->dma_chan);
1443 /* clear flip-flop to make sure 2-byte registers for
1444 * count and address get set correctly */
1445 clear_dma_ff(devpriv->dma_chan);
1446
f6b49620 1447 /* figure out how many points to read */
124b13b2
FMH		 1448 max_points = devpriv->dma_transfer_size / sample_size;
1449 /* residue is the number of points left to be done on the dma
1450 * transfer. It should always be zero at this point unless
1451 * the stop_src is set to external triggering.
1452 */
1453 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1454 num_points = max_points - residue;
1455 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1456 num_points = devpriv->count;
1457
f6b49620 1458 /* figure out how many points will be stored next time */
124b13b2
FMH		 1459 leftover = 0;
1460 if (async->cmd.stop_src != TRIG_COUNT) {
1461 leftover = devpriv->dma_transfer_size / sample_size;
1462 } else if (devpriv->count > num_points) {
1463 leftover = devpriv->count - num_points;
1464 if (leftover > max_points)
1465 leftover = max_points;
1466 }
1467
1468 /* write data to comedi buffer */
1469 for (i = 0; i < num_points; i++) {
1470 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1471 }
1472 if (async->cmd.stop_src == TRIG_COUNT)
1473 devpriv->count -= num_points;
1474
f6b49620 1475 /* set address and count for next transfer */
124b13b2
FMH		 1476 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1477 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1478 release_dma_lock(flags);
1479
1480 async->events |= COMEDI_CB_BLOCK;
1481}
1482
71b5f4f1 1483static void handle_isa_dma(struct comedi_device * dev)
124b13b2
FMH		 1484{
1485 labpc_drain_dma(dev);
1486
1487 enable_dma(devpriv->dma_chan);
1488
f6b49620 1489 /* clear dma tc interrupt */
124b13b2
FMH		 1490 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1491}
1492
1493/* makes sure all data aquired by board is transfered to comedi (used
1494 * when aquisition is terminated by stop_src == TRIG_EXT). */
71b5f4f1 1495static void labpc_drain_dregs(struct comedi_device * dev)
124b13b2
FMH		 1496{
1497 if (devpriv->current_transfer == isa_dma_transfer)
1498 labpc_drain_dma(dev);
1499
1500 labpc_drain_fifo(dev);
1501}
1502
34c43922 1503static int labpc_ai_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1504 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1505{
1506 int i, n;
1507 int chan, range;
1508 int lsb, msb;
1509 int timeout = 1000;
1510 unsigned long flags;
1511
f6b49620 1512 /* disable timed conversions */
124b13b2
FMH		 1513 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1514 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1515 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1516 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1517
f6b49620 1518 /* disable interrupt generation and dma */
124b13b2
FMH		 1519 devpriv->command3_bits = 0;
1520 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1521
1522 /* set gain and channel */
1523 devpriv->command1_bits = 0;
1524 chan = CR_CHAN(insn->chanspec);
1525 range = CR_RANGE(insn->chanspec);
1526 devpriv->command1_bits |= thisboard->ai_range_code[range];
f6b49620 1527 /* munge channel bits for differential/scan disabled mode */
124b13b2
FMH		 1528 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1529 chan *= 2;
1530 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1531 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1532
f6b49620 1533 /* setup command6 register for 1200 boards */
124b13b2 1534 if (thisboard->register_layout == labpc_1200_layout) {
f6b49620 1535 /* reference inputs to ground or common? */
124b13b2
FMH		 1536 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1537 devpriv->command6_bits |= ADC_COMMON_BIT;
1538 else
1539 devpriv->command6_bits &= ~ADC_COMMON_BIT;
f6b49620 1540 /* bipolar or unipolar range? */
124b13b2
FMH		 1541 if (thisboard->ai_range_is_unipolar[range])
1542 devpriv->command6_bits |= ADC_UNIP_BIT;
1543 else
1544 devpriv->command6_bits &= ~ADC_UNIP_BIT;
f6b49620 1545 /* don't interrupt on fifo half full */
124b13b2 1546 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
f6b49620 1547 /* don't enable interrupt on counter a1 terminal count? */
124b13b2 1548 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
f6b49620 1549 /* write to register */
124b13b2
FMH		 1550 devpriv->write_byte(devpriv->command6_bits,
1551 dev->iobase + COMMAND6_REG);
1552 }
f6b49620 1553 /* setup command4 register */
124b13b2
FMH		 1554 devpriv->command4_bits = 0;
1555 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
f6b49620 1556 /* single-ended/differential */
124b13b2
FMH		 1557 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1558 devpriv->command4_bits |= ADC_DIFF_BIT;
1559 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1560
f6b49620 1561 /* initialize pacer counter output to make sure it doesn't cause any problems */
124b13b2
FMH		 1562 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1563
1564 labpc_clear_adc_fifo(dev);
1565
1566 for (n = 0; n < insn->n; n++) {
1567 /* trigger conversion */
1568 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1569
1570 for (i = 0; i < timeout; i++) {
1571 if (devpriv->read_byte(dev->iobase +
1572 STATUS1_REG) & DATA_AVAIL_BIT)
1573 break;
1574 comedi_udelay(1);
1575 }
1576 if (i == timeout) {
1577 comedi_error(dev, "timeout");
1578 return -ETIME;
1579 }
1580 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1581 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1582 data[n] = (msb << 8) | lsb;
1583 }
1584
1585 return n;
1586}
1587
f6b49620 1588/* analog output insn */
34c43922 1589static int labpc_ao_winsn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1590 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1591{
1592 int channel, range;
1593 unsigned long flags;
1594 int lsb, msb;
1595
1596 channel = CR_CHAN(insn->chanspec);
1597
f6b49620 1598 /* turn off pacing of analog output channel */
124b13b2
FMH		 1599 /* note: hardware bug in daqcard-1200 means pacing cannot
1600 * be independently enabled/disabled for its the two channels */
1601 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1602 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1603 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1604 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1605
f6b49620 1606 /* set range */
124b13b2
FMH		 1607 if (thisboard->register_layout == labpc_1200_layout) {
1608 range = CR_RANGE(insn->chanspec);
1609 if (range & AO_RANGE_IS_UNIPOLAR)
1610 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1611 else
1612 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
f6b49620 1613 /* write to register */
124b13b2
FMH		 1614 devpriv->write_byte(devpriv->command6_bits,
1615 dev->iobase + COMMAND6_REG);
1616 }
f6b49620 1617 /* send data */
124b13b2
FMH		 1618 lsb = data[0] & 0xff;
1619 msb = (data[0] >> 8) & 0xff;
1620 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1621 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1622
f6b49620 1623 /* remember value for readback */
124b13b2
FMH		 1624 devpriv->ao_value[channel] = data[0];
1625
1626 return 1;
1627}
1628
f6b49620 1629/* analog output readback insn */
34c43922 1630static int labpc_ao_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1631 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1632{
1633 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1634
1635 return 1;
1636}
1637
34c43922 1638static int labpc_calib_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1639 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1640{
1641 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1642
1643 return 1;
1644}
1645
34c43922 1646static int labpc_calib_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1647 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1648{
1649 int channel = CR_CHAN(insn->chanspec);
1650
1651 write_caldac(dev, channel, data[0]);
1652 return 1;
1653}
1654
34c43922 1655static int labpc_eeprom_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1656 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1657{
1658 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1659
1660 return 1;
1661}
1662
34c43922 1663static int labpc_eeprom_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 1664 struct comedi_insn * insn, unsigned int * data)
124b13b2
FMH		 1665{
1666 int channel = CR_CHAN(insn->chanspec);
1667 int ret;
1668
f6b49620 1669 /* only allow writes to user area of eeprom */
124b13b2
FMH		 1670 if (channel < 16 || channel > 127) {
1671 printk("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
1672 return -EINVAL;
1673 }
1674
1675 ret = labpc_eeprom_write(dev, channel, data[0]);
1676 if (ret < 0)
1677 return ret;
1678
1679 return 1;
1680}
1681
f6b49620 1682/* utility function that suggests a dma transfer size in bytes */
ea6d0d4c 1683static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
124b13b2
FMH		 1684{
1685 unsigned int size;
1686 unsigned int freq;
1687
1688 if (cmd.convert_src == TRIG_TIMER)
1689 freq = 1000000000 / cmd.convert_arg;
f6b49620 1690 /* return some default value */
124b13b2
FMH		 1691 else
1692 freq = 0xffffffff;
1693
f6b49620 1694 /* make buffer fill in no more than 1/3 second */
124b13b2
FMH		 1695 size = (freq / 3) * sample_size;
1696
f6b49620 1697 /* set a minimum and maximum size allowed */
124b13b2
FMH		 1698 if (size > dma_buffer_size)
1699 size = dma_buffer_size - dma_buffer_size % sample_size;
1700 else if (size < sample_size)
1701 size = sample_size;
1702
1703 return size;
1704}
1705
f6b49620 1706/* figures out what counter values to use based on command */
ea6d0d4c 1707static void labpc_adc_timing(struct comedi_device * dev, struct comedi_cmd * cmd)
124b13b2 1708{
f6b49620
BP		 1709 const int max_counter_value = 0x10000; /* max value for 16 bit counter in mode 2 */
1710 const int min_counter_value = 2; /* min value for 16 bit counter in mode 2 */
124b13b2
FMH		 1711 unsigned int base_period;
1712
f6b49620 1713 /* if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */
124b13b2 1714 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
f6b49620 1715 /* pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */
124b13b2
FMH		 1716 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1717 (LABPC_TIMER_BASE * max_counter_value) + 1;
1718 if (devpriv->divisor_b0 < min_counter_value)
1719 devpriv->divisor_b0 = min_counter_value;
1720 if (devpriv->divisor_b0 > max_counter_value)
1721 devpriv->divisor_b0 = max_counter_value;
1722
1723 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1724
f6b49620 1725 /* set a0 for conversion frequency and b1 for scan frequency */
124b13b2
FMH		 1726 switch (cmd->flags & TRIG_ROUND_MASK) {
1727 default:
1728 case TRIG_ROUND_NEAREST:
1729 devpriv->divisor_a0 =
1730 (labpc_ai_convert_period(cmd) +
1731 (base_period / 2)) / base_period;
1732 devpriv->divisor_b1 =
1733 (labpc_ai_scan_period(cmd) +
1734 (base_period / 2)) / base_period;
1735 break;
1736 case TRIG_ROUND_UP:
1737 devpriv->divisor_a0 =
1738 (labpc_ai_convert_period(cmd) + (base_period -
1739 1)) / base_period;
1740 devpriv->divisor_b1 =
1741 (labpc_ai_scan_period(cmd) + (base_period -
1742 1)) / base_period;
1743 break;
1744 case TRIG_ROUND_DOWN:
1745 devpriv->divisor_a0 =
1746 labpc_ai_convert_period(cmd) / base_period;
1747 devpriv->divisor_b1 =
1748 labpc_ai_scan_period(cmd) / base_period;
1749 break;
1750 }
f6b49620 1751 /* make sure a0 and b1 values are acceptable */
124b13b2
FMH		 1752 if (devpriv->divisor_a0 < min_counter_value)
1753 devpriv->divisor_a0 = min_counter_value;
1754 if (devpriv->divisor_a0 > max_counter_value)
1755 devpriv->divisor_a0 = max_counter_value;
1756 if (devpriv->divisor_b1 < min_counter_value)
1757 devpriv->divisor_b1 = min_counter_value;
1758 if (devpriv->divisor_b1 > max_counter_value)
1759 devpriv->divisor_b1 = max_counter_value;
f6b49620 1760 /* write corrected timings to command */
124b13b2
FMH		 1761 labpc_set_ai_convert_period(cmd,
1762 base_period * devpriv->divisor_a0);
1763 labpc_set_ai_scan_period(cmd,
1764 base_period * devpriv->divisor_b1);
f6b49620 1765 /* if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */
124b13b2
FMH		 1766 } else if (labpc_ai_scan_period(cmd)) {
1767 unsigned int scan_period;
1768
1769 scan_period = labpc_ai_scan_period(cmd);
1770 /* calculate cascaded counter values that give desired scan timing */
1771 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1772 &(devpriv->divisor_b1), &(devpriv->divisor_b0),
1773 &scan_period, cmd->flags & TRIG_ROUND_MASK);
1774 labpc_set_ai_scan_period(cmd, scan_period);
1775 } else if (labpc_ai_convert_period(cmd)) {
1776 unsigned int convert_period;
1777
1778 convert_period = labpc_ai_convert_period(cmd);
1779 /* calculate cascaded counter values that give desired conversion timing */
1780 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1781 &(devpriv->divisor_a0), &(devpriv->divisor_b0),
1782 &convert_period, cmd->flags & TRIG_ROUND_MASK);
1783 labpc_set_ai_convert_period(cmd, convert_period);
1784 }
1785}
1786
1787static int labpc_dio_mem_callback(int dir, int port, int data,
1788 unsigned long iobase)
1789{
1790 if (dir) {
1791 writeb(data, (void *)(iobase + port));
1792 return 0;
1793 } else {
1794 return readb((void *)(iobase + port));
1795 }
1796}
1797
f6b49620 1798/* lowlevel write to eeprom/dac */
71b5f4f1 1799static void labpc_serial_out(struct comedi_device * dev, unsigned int value,
124b13b2
FMH		 1800 unsigned int value_width)
1801{
1802 int i;
1803
1804 for (i = 1; i <= value_width; i++) {
f6b49620 1805 /* clear serial clock */
124b13b2 1806 devpriv->command5_bits &= ~SCLOCK_BIT;
f6b49620 1807 /* send bits most significant bit first */
124b13b2
FMH		 1808 if (value & (1 << (value_width - i)))
1809 devpriv->command5_bits |= SDATA_BIT;
1810 else
1811 devpriv->command5_bits &= ~SDATA_BIT;
1812 comedi_udelay(1);
1813 devpriv->write_byte(devpriv->command5_bits,
1814 dev->iobase + COMMAND5_REG);
f6b49620 1815 /* set clock to load bit */
124b13b2
FMH		 1816 devpriv->command5_bits |= SCLOCK_BIT;
1817 comedi_udelay(1);
1818 devpriv->write_byte(devpriv->command5_bits,
1819 dev->iobase + COMMAND5_REG);
1820 }
1821}
1822
f6b49620 1823/* lowlevel read from eeprom */
71b5f4f1 1824static unsigned int labpc_serial_in(struct comedi_device * dev)
124b13b2
FMH		 1825{
1826 unsigned int value = 0;
1827 int i;
f6b49620 1828 const int value_width = 8; /* number of bits wide values are */
124b13b2
FMH		 1829
1830 for (i = 1; i <= value_width; i++) {
f6b49620 1831 /* set serial clock */
124b13b2
FMH		 1832 devpriv->command5_bits |= SCLOCK_BIT;
1833 comedi_udelay(1);
1834 devpriv->write_byte(devpriv->command5_bits,
1835 dev->iobase + COMMAND5_REG);
f6b49620 1836 /* clear clock bit */
124b13b2
FMH		 1837 devpriv->command5_bits &= ~SCLOCK_BIT;
1838 comedi_udelay(1);
1839 devpriv->write_byte(devpriv->command5_bits,
1840 dev->iobase + COMMAND5_REG);
f6b49620 1841 /* read bits most significant bit first */
124b13b2
FMH		 1842 comedi_udelay(1);
1843 devpriv->status2_bits =
1844 devpriv->read_byte(dev->iobase + STATUS2_REG);
1845 if (devpriv->status2_bits & EEPROM_OUT_BIT) {
1846 value |= 1 << (value_width - i);
1847 }
1848 }
1849
1850 return value;
1851}
1852
71b5f4f1 1853static unsigned int labpc_eeprom_read(struct comedi_device * dev, unsigned int address)
124b13b2
FMH		 1854{
1855 unsigned int value;
f6b49620
BP		 1856 const int read_instruction = 0x3; /* bits to tell eeprom to expect a read */
1857 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2 1858
f6b49620 1859 /* enable read/write to eeprom */
124b13b2
FMH		 1860 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1861 comedi_udelay(1);
1862 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1863 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1864 comedi_udelay(1);
1865 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1866
f6b49620 1867 /* send read instruction */
124b13b2 1868 labpc_serial_out(dev, read_instruction, write_length);
f6b49620 1869 /* send 8 bit address to read from */
124b13b2 1870 labpc_serial_out(dev, address, write_length);
f6b49620 1871 /* read result */
124b13b2
FMH		 1872 value = labpc_serial_in(dev);
1873
f6b49620 1874 /* disable read/write to eeprom */
124b13b2
FMH		 1875 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1876 comedi_udelay(1);
1877 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1878
1879 return value;
1880}
1881
71b5f4f1 1882static unsigned int labpc_eeprom_write(struct comedi_device * dev,
124b13b2
FMH		 1883 unsigned int address, unsigned int value)
1884{
1885 const int write_enable_instruction = 0x6;
1886 const int write_instruction = 0x2;
f6b49620 1887 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2
FMH		 1888 const int write_in_progress_bit = 0x1;
1889 const int timeout = 10000;
1890 int i;
1891
f6b49620 1892 /* make sure there isn't already a write in progress */
124b13b2
FMH		 1893 for (i = 0; i < timeout; i++) {
1894 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1895 0)
1896 break;
1897 }
1898 if (i == timeout) {
1899 comedi_error(dev, "eeprom write timed out");
1900 return -ETIME;
1901 }
f6b49620 1902 /* update software copy of eeprom */
124b13b2
FMH		 1903 devpriv->eeprom_data[address] = value;
1904
f6b49620 1905 /* enable read/write to eeprom */
124b13b2
FMH		 1906 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1907 comedi_udelay(1);
1908 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1909 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1910 comedi_udelay(1);
1911 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1912
f6b49620 1913 /* send write_enable instruction */
124b13b2
FMH		 1914 labpc_serial_out(dev, write_enable_instruction, write_length);
1915 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1916 comedi_udelay(1);
1917 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1918
f6b49620 1919 /* send write instruction */
124b13b2
FMH		 1920 devpriv->command5_bits |= EEPROM_EN_BIT;
1921 comedi_udelay(1);
1922 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1923 labpc_serial_out(dev, write_instruction, write_length);
f6b49620 1924 /* send 8 bit address to write to */
124b13b2 1925 labpc_serial_out(dev, address, write_length);
f6b49620 1926 /* write value */
124b13b2
FMH		 1927 labpc_serial_out(dev, value, write_length);
1928 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1929 comedi_udelay(1);
1930 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1931
f6b49620 1932 /* disable read/write to eeprom */
124b13b2
FMH		 1933 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1934 comedi_udelay(1);
1935 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1936
1937 return 0;
1938}
1939
71b5f4f1 1940static unsigned int labpc_eeprom_read_status(struct comedi_device * dev)
124b13b2
FMH		 1941{
1942 unsigned int value;
1943 const int read_status_instruction = 0x5;
f6b49620 1944 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2 1945
f6b49620 1946 /* enable read/write to eeprom */
124b13b2
FMH		 1947 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1948 comedi_udelay(1);
1949 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1950 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1951 comedi_udelay(1);
1952 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1953
f6b49620 1954 /* send read status instruction */
124b13b2 1955 labpc_serial_out(dev, read_status_instruction, write_length);
f6b49620 1956 /* read result */
124b13b2
FMH		 1957 value = labpc_serial_in(dev);
1958
f6b49620 1959 /* disable read/write to eeprom */
124b13b2
FMH		 1960 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1961 comedi_udelay(1);
1962 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1963
1964 return value;
1965}
1966
f6b49620 1967/* writes to 8 bit calibration dacs */
71b5f4f1 1968static void write_caldac(struct comedi_device * dev, unsigned int channel,
124b13b2
FMH		 1969 unsigned int value)
1970{
1971 if (value == devpriv->caldac[channel])
1972 return;
1973 devpriv->caldac[channel] = value;
1974
f6b49620 1975 /* clear caldac load bit and make sure we don't write to eeprom */
124b13b2
FMH		 1976 devpriv->command5_bits &=
1977 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1978 comedi_udelay(1);
1979 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1980
f6b49620 1981 /* write 4 bit channel */
124b13b2 1982 labpc_serial_out(dev, channel, 4);
f6b49620 1983 /* write 8 bit caldac value */
124b13b2
FMH		 1984 labpc_serial_out(dev, value, 8);
1985
f6b49620 1986 /* set and clear caldac bit to load caldac value */
124b13b2
FMH		 1987 devpriv->command5_bits |= CALDAC_LOAD_BIT;
1988 comedi_udelay(1);
1989 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1990 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
1991 comedi_udelay(1);
1992 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1993}
1994
1995#ifdef CONFIG_COMEDI_PCI
1996COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table);
1997#else
1998COMEDI_INITCLEANUP(driver_labpc);
1999#endif
2000
2001EXPORT_SYMBOL_GPL(labpc_common_attach);
2002EXPORT_SYMBOL_GPL(labpc_common_detach);
2003EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
2004EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
2005EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
kernel source for telekom puls (alcatel/mediatek)