Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_at_ao.c
CommitLineData
6a9d800f
DS
1/*
2 comedi/drivers/ni_at_ao.c
3 Driver for NI AT-AO-6/10 boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000,2002 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22*/
23/*
24Driver: ni_at_ao
25Description: National Instruments AT-AO-6/10
26Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
27Status: should work
28Author: ds
29Updated: Sun Dec 26 12:26:28 EST 2004
30
31Configuration options:
32 [0] - I/O port base address
33 [1] - IRQ (unused)
34 [2] - DMA (unused)
d1a04408
AR
35 [3] - analog output range, set by jumpers on hardware (0 for -10 to 10V
36 bipolar, 1 for 0V to 10V unipolar)
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DS
37
38*/
39/*
40 * Register-level programming information can be found in NI
41 * document 320379.pdf.
42 */
43
44#include "../comedidev.h"
45
46#include <linux/ioport.h>
47
48/* board egisters */
49/* registers with _2_ are accessed when GRP2WR is set in CFG1 */
50
51#define ATAO_SIZE 0x20
52
53#define ATAO_2_DMATCCLR 0x00 /* W 16 */
54#define ATAO_DIN 0x00 /* R 16 */
55#define ATAO_DOUT 0x00 /* W 16 */
56
57#define ATAO_CFG2 0x02 /* W 16 */
58#define CALLD1 0x8000
59#define CALLD0 0x4000
60#define FFRTEN 0x2000
61#define DAC2S8 0x1000
62#define DAC2S6 0x0800
63#define DAC2S4 0x0400
64#define DAC2S2 0x0200
65#define DAC2S0 0x0100
66#define LDAC8 0x0080
67#define LDAC6 0x0040
68#define LDAC4 0x0020
69#define LDAC2 0x0010
70#define LDAC0 0x0008
71#define PROMEN 0x0004
72#define SCLK 0x0002
73#define SDATA 0x0001
74
75#define ATAO_2_INT1CLR 0x02 /* W 16 */
76
77#define ATAO_CFG3 0x04 /* W 16 */
78#define DMAMODE 0x0040
79#define CLKOUT 0x0020
80#define RCLKEN 0x0010
81#define DOUTEN2 0x0008
82#define DOUTEN1 0x0004
83#define EN2_5V 0x0002
84#define SCANEN 0x0001
85
86#define ATAO_2_INT2CLR 0x04 /* W 16 */
87
88#define ATAO_82C53_BASE 0x06 /* RW 8 */
89
90#define ATAO_82C53_CNTR1 0x06 /* RW 8 */
91#define ATAO_82C53_CNTR2 0x07 /* RW 8 */
92#define ATAO_82C53_CNTR3 0x08 /* RW 8 */
93#define ATAO_82C53_CNTRCMD 0x09 /* W 8 */
94#define CNTRSEL1 0x80
95#define CNTRSEL0 0x40
96#define RWSEL1 0x20
97#define RWSEL0 0x10
98#define MODESEL2 0x08
99#define MODESEL1 0x04
100#define MODESEL0 0x02
101#define BCDSEL 0x01
102 /* read-back command */
103#define COUNT 0x20
104#define STATUS 0x10
105#define CNTR3 0x08
106#define CNTR2 0x04
107#define CNTR1 0x02
108 /* status */
109#define OUT 0x80
110#define _NULL 0x40
111#define RW1 0x20
112#define RW0 0x10
113#define MODE2 0x08
114#define MODE1 0x04
115#define MODE0 0x02
116#define BCD 0x01
117
118#define ATAO_2_RTSISHFT 0x06 /* W 8 */
119#define RSI 0x01
120
121#define ATAO_2_RTSISTRB 0x07 /* W 8 */
122
123#define ATAO_CFG1 0x0a /* W 16 */
124#define EXTINT2EN 0x8000
125#define EXTINT1EN 0x4000
126#define CNTINT2EN 0x2000
127#define CNTINT1EN 0x1000
128#define TCINTEN 0x0800
129#define CNT1SRC 0x0400
130#define CNT2SRC 0x0200
131#define FIFOEN 0x0100
132#define GRP2WR 0x0080
133#define EXTUPDEN 0x0040
134#define DMARQ 0x0020
135#define DMAEN 0x0010
136#define CH_mask 0x000f
137#define ATAO_STATUS 0x0a /* R 16 */
138#define FH 0x0040
139#define FE 0x0020
140#define FF 0x0010
141#define INT2 0x0008
142#define INT1 0x0004
143#define TCINT 0x0002
144#define PROMOUT 0x0001
145
146#define ATAO_FIFO_WRITE 0x0c /* W 16 */
147#define ATAO_FIFO_CLEAR 0x0c /* R 16 */
148#define ATAO_DACn(x) (0x0c + 2*(x)) /* W */
149
150/*
151 * Board descriptions for two imaginary boards. Describing the
152 * boards in this way is optional, and completely driver-dependent.
153 * Some drivers use arrays such as this, other do not.
154 */
01983c39 155struct atao_board {
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156 const char *name;
157 int n_ao_chans;
01983c39
BP
158};
159
160static const struct atao_board atao_boards[] = {
6a9d800f 161 {
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162 .name = "ai-ao-6",
163 .n_ao_chans = 6,
164 },
6a9d800f 165 {
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166 .name = "ai-ao-10",
167 .n_ao_chans = 10,
168 },
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169};
170
01983c39 171#define thisboard ((struct atao_board *)dev->board_ptr)
6a9d800f 172
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173struct atao_private {
174
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175 unsigned short cfg1;
176 unsigned short cfg2;
177 unsigned short cfg3;
178
179 /* Used for AO readback */
790c5541 180 unsigned int ao_readback[10];
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181};
182
183#define devpriv ((struct atao_private *)dev->private)
6a9d800f 184
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185static int atao_attach(struct comedi_device *dev, struct comedi_devconfig *it);
186static int atao_detach(struct comedi_device *dev);
139dfbdf 187static struct comedi_driver driver_atao = {
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BP
188 .driver_name = "ni_at_ao",
189 .module = THIS_MODULE,
190 .attach = atao_attach,
191 .detach = atao_detach,
192 .board_name = &atao_boards[0].name,
193 .offset = sizeof(struct atao_board),
8629efa4 194 .num_names = ARRAY_SIZE(atao_boards),
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195};
196
7114a280
AT
197static int __init driver_atao_init_module(void)
198{
199 return comedi_driver_register(&driver_atao);
200}
201
202static void __exit driver_atao_cleanup_module(void)
203{
204 comedi_driver_unregister(&driver_atao);
205}
206
207module_init(driver_atao_init_module);
208module_exit(driver_atao_cleanup_module);
6a9d800f 209
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BP
210static void atao_reset(struct comedi_device *dev);
211
212static int atao_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 213 struct comedi_insn *insn, unsigned int *data);
da91b269 214static int atao_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
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MT
215 struct comedi_insn *insn, unsigned int *data);
216static int atao_dio_insn_bits(struct comedi_device *dev,
217 struct comedi_subdevice *s,
218 struct comedi_insn *insn, unsigned int *data);
219static int atao_dio_insn_config(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222static int atao_calib_insn_read(struct comedi_device *dev,
223 struct comedi_subdevice *s,
224 struct comedi_insn *insn, unsigned int *data);
225static int atao_calib_insn_write(struct comedi_device *dev,
226 struct comedi_subdevice *s,
227 struct comedi_insn *insn, unsigned int *data);
da91b269
BP
228
229static int atao_attach(struct comedi_device *dev, struct comedi_devconfig *it)
6a9d800f 230{
34c43922 231 struct comedi_subdevice *s;
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232 unsigned long iobase;
233 int ao_unipolar;
234
235 iobase = it->options[0];
236 if (iobase == 0)
237 iobase = 0x1c0;
238 ao_unipolar = it->options[3];
239
a2936e0d 240 printk(KERN_INFO "comedi%d: ni_at_ao: 0x%04lx", dev->minor, iobase);
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241
242 if (!request_region(iobase, ATAO_SIZE, "ni_at_ao")) {
243 printk(" I/O port conflict\n");
244 return -EIO;
245 }
246 dev->iobase = iobase;
247
2696fb57 248 /* dev->board_ptr = atao_probe(dev); */
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249
250 dev->board_name = thisboard->name;
251
75b80739 252 if (alloc_private(dev, sizeof(struct atao_private)) < 0)
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253 return -ENOMEM;
254
255 if (alloc_subdevices(dev, 4) < 0)
256 return -ENOMEM;
257
258 s = dev->subdevices + 0;
259 /* analog output subdevice */
260 s->type = COMEDI_SUBD_AO;
261 s->subdev_flags = SDF_WRITABLE;
262 s->n_chan = thisboard->n_ao_chans;
263 s->maxdata = (1 << 12) - 1;
264 if (ao_unipolar)
265 s->range_table = &range_unipolar10;
266 else
267 s->range_table = &range_bipolar10;
268 s->insn_write = &atao_ao_winsn;
269 s->insn_read = &atao_ao_rinsn;
270
271 s = dev->subdevices + 1;
272 /* digital i/o subdevice */
273 s->type = COMEDI_SUBD_DIO;
274 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
275 s->n_chan = 8;
276 s->maxdata = 1;
277 s->range_table = &range_digital;
278 s->insn_bits = atao_dio_insn_bits;
279 s->insn_config = atao_dio_insn_config;
280
281 s = dev->subdevices + 2;
282 /* caldac subdevice */
283 s->type = COMEDI_SUBD_CALIB;
284 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
285 s->n_chan = 21;
286 s->maxdata = 0xff;
287 s->insn_read = atao_calib_insn_read;
288 s->insn_write = atao_calib_insn_write;
289
290 s = dev->subdevices + 3;
291 /* eeprom subdevice */
2696fb57 292 /* s->type=COMEDI_SUBD_EEPROM; */
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293 s->type = COMEDI_SUBD_UNUSED;
294
295 atao_reset(dev);
296
a2936e0d 297 printk(KERN_INFO "\n");
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298
299 return 0;
300}
301
da91b269 302static int atao_detach(struct comedi_device *dev)
6a9d800f 303{
a2936e0d 304 printk(KERN_INFO "comedi%d: atao: remove\n", dev->minor);
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DS
305
306 if (dev->iobase)
307 release_region(dev->iobase, ATAO_SIZE);
308
309 return 0;
310}
311
da91b269 312static void atao_reset(struct comedi_device *dev)
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DS
313{
314 /* This is the reset sequence described in the manual */
315
316 devpriv->cfg1 = 0;
317 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
318
319 outb(RWSEL0 | MODESEL2, dev->iobase + ATAO_82C53_CNTRCMD);
320 outb(0x03, dev->iobase + ATAO_82C53_CNTR1);
321 outb(CNTRSEL0 | RWSEL0 | MODESEL2, dev->iobase + ATAO_82C53_CNTRCMD);
322
323 devpriv->cfg2 = 0;
324 outw(devpriv->cfg2, dev->iobase + ATAO_CFG2);
325
326 devpriv->cfg3 = 0;
327 outw(devpriv->cfg3, dev->iobase + ATAO_CFG3);
328
329 inw(dev->iobase + ATAO_FIFO_CLEAR);
330
331 devpriv->cfg1 |= GRP2WR;
332 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
333
334 outw(0, dev->iobase + ATAO_2_INT1CLR);
335 outw(0, dev->iobase + ATAO_2_INT2CLR);
336 outw(0, dev->iobase + ATAO_2_DMATCCLR);
337
338 devpriv->cfg1 &= ~GRP2WR;
339 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
340}
341
da91b269 342static int atao_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 343 struct comedi_insn *insn, unsigned int *data)
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DS
344{
345 int i;
346 int chan = CR_CHAN(insn->chanspec);
347 short bits;
348
349 for (i = 0; i < insn->n; i++) {
350 bits = data[i] - 0x800;
351 if (chan == 0) {
352 devpriv->cfg1 |= GRP2WR;
353 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
354 }
355 outw(bits, dev->iobase + ATAO_DACn(chan));
356 if (chan == 0) {
357 devpriv->cfg1 &= ~GRP2WR;
358 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
359 }
360 devpriv->ao_readback[chan] = data[i];
361 }
362
363 return i;
364}
365
da91b269 366static int atao_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 367 struct comedi_insn *insn, unsigned int *data)
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DS
368{
369 int i;
370 int chan = CR_CHAN(insn->chanspec);
371
372 for (i = 0; i < insn->n; i++)
373 data[i] = devpriv->ao_readback[chan];
374
375 return i;
376}
377
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MT
378static int atao_dio_insn_bits(struct comedi_device *dev,
379 struct comedi_subdevice *s,
380 struct comedi_insn *insn, unsigned int *data)
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DS
381{
382 if (insn->n != 2)
383 return -EINVAL;
384
385 if (data[0]) {
386 s->state &= ~data[0];
387 s->state |= data[0] & data[1];
388 outw(s->state, dev->iobase + ATAO_DOUT);
389 }
390
391 data[1] = inw(dev->iobase + ATAO_DIN);
392
393 return 2;
394}
395
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MT
396static int atao_dio_insn_config(struct comedi_device *dev,
397 struct comedi_subdevice *s,
398 struct comedi_insn *insn, unsigned int *data)
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DS
399{
400 int chan = CR_CHAN(insn->chanspec);
401 unsigned int mask, bit;
402
403 /* The input or output configuration of each digital line is
404 * configured by a special insn_config instruction. chanspec
405 * contains the channel to be changed, and data[0] contains the
406 * value COMEDI_INPUT or COMEDI_OUTPUT. */
407
408 mask = (chan < 4) ? 0x0f : 0xf0;
409 bit = (chan < 4) ? DOUTEN1 : DOUTEN2;
410
411 switch (data[0]) {
412 case INSN_CONFIG_DIO_OUTPUT:
413 s->io_bits |= mask;
414 devpriv->cfg3 |= bit;
415 break;
416 case INSN_CONFIG_DIO_INPUT:
417 s->io_bits &= ~mask;
418 devpriv->cfg3 &= ~bit;
419 break;
420 case INSN_CONFIG_DIO_QUERY:
421 data[1] =
0a85b6f0 422 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
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DS
423 return insn->n;
424 break;
425 default:
426 return -EINVAL;
427 break;
428 }
429
430 outw(devpriv->cfg3, dev->iobase + ATAO_CFG3);
431
432 return 1;
433}
434
435/*
436 * Figure 2-1 in the manual shows 3 chips labeled DAC8800, which
437 * are 8-channel 8-bit DACs. These are most likely the calibration
438 * DACs. It is not explicitly stated in the manual how to access
439 * the caldacs, but we can guess.
440 */
0a85b6f0
MT
441static int atao_calib_insn_read(struct comedi_device *dev,
442 struct comedi_subdevice *s,
443 struct comedi_insn *insn, unsigned int *data)
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DS
444{
445 int i;
d1a04408 446 for (i = 0; i < insn->n; i++)
6a9d800f 447 data[i] = 0; /* XXX */
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DS
448 return insn->n;
449}
450
0a85b6f0
MT
451static int atao_calib_insn_write(struct comedi_device *dev,
452 struct comedi_subdevice *s,
453 struct comedi_insn *insn, unsigned int *data)
6a9d800f
DS
454{
455 unsigned int bitstring, bit;
456 unsigned int chan = CR_CHAN(insn->chanspec);
457
458 bitstring = ((chan & 0x7) << 8) | (data[insn->n - 1] & 0xff);
459
460 for (bit = 1 << (11 - 1); bit; bit >>= 1) {
461 outw(devpriv->cfg2 | ((bit & bitstring) ? SDATA : 0),
0a85b6f0 462 dev->iobase + ATAO_CFG2);
6a9d800f 463 outw(devpriv->cfg2 | SCLK | ((bit & bitstring) ? SDATA : 0),
0a85b6f0 464 dev->iobase + ATAO_CFG2);
6a9d800f
DS
465 }
466 /* strobe the appropriate caldac */
467 outw(devpriv->cfg2 | (((chan >> 3) + 1) << 14),
0a85b6f0 468 dev->iobase + ATAO_CFG2);
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DS
469 outw(devpriv->cfg2, dev->iobase + ATAO_CFG2);
470
471 return insn->n;
472}
90f703d3
AT
473
474MODULE_AUTHOR("Comedi http://www.comedi.org");
475MODULE_DESCRIPTION("Comedi low-level driver");
476MODULE_LICENSE("GPL");