Commit | Line | Data |
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01b0a258 FMH |
1 | /* |
2 | comedi/drivers/ni_at_a2150.c | |
3 | Driver for National Instruments AT-A2150 boards | |
4 | Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net> | |
5 | ||
6 | COMEDI - Linux Control and Measurement Device Interface | |
7 | Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | ||
23 | ************************************************************************ | |
24 | */ | |
25 | /* | |
26 | Driver: ni_at_a2150 | |
27 | Description: National Instruments AT-A2150 | |
28 | Author: Frank Mori Hess | |
29 | Status: works | |
30 | Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s) | |
31 | ||
32 | If you want to ac couple the board's inputs, use AREF_OTHER. | |
33 | ||
34 | Configuration options: | |
35 | [0] - I/O port base address | |
36 | [1] - IRQ (optional, required for timed conversions) | |
37 | [2] - DMA (optional, required for timed conversions) | |
38 | ||
39 | */ | |
40 | /* | |
41 | Yet another driver for obsolete hardware brought to you by Frank Hess. | |
42 | Testing and debugging help provided by Dave Andruczyk. | |
43 | ||
44 | This driver supports the boards: | |
45 | ||
46 | AT-A2150C | |
47 | AT-A2150S | |
48 | ||
49 | The only difference is their master clock frequencies. | |
50 | ||
51 | Options: | |
52 | [0] - base io address | |
53 | [1] - irq | |
54 | [2] - dma channel | |
55 | ||
56 | References (from ftp://ftp.natinst.com/support/manuals): | |
57 | ||
58 | 320360.pdf AT-A2150 User Manual | |
59 | ||
60 | TODO: | |
61 | ||
62 | analog level triggering | |
63 | TRIG_WAKE_EOS | |
64 | ||
65 | */ | |
66 | ||
25436dc9 | 67 | #include <linux/interrupt.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
01b0a258 FMH |
69 | #include "../comedidev.h" |
70 | ||
71 | #include <linux/ioport.h> | |
845d131e | 72 | #include <linux/io.h> |
01b0a258 FMH |
73 | #include <asm/dma.h> |
74 | ||
75 | #include "8253.h" | |
76 | #include "comedi_fc.h" | |
77 | ||
78 | #define A2150_SIZE 28 | |
30c687c1 | 79 | #define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */ |
01b0a258 | 80 | |
30c687c1 BP |
81 | /* #define A2150_DEBUG enable debugging code */ |
82 | #undef A2150_DEBUG /* disable debugging code */ | |
01b0a258 FMH |
83 | |
84 | /* Registers and bits */ | |
85 | #define CONFIG_REG 0x0 | |
86 | #define CHANNEL_BITS(x) ((x) & 0x7) | |
87 | #define CHANNEL_MASK 0x7 | |
88 | #define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3) | |
89 | #define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5) | |
90 | #define CLOCK_MASK (0xf << 3) | |
30c687c1 BP |
91 | #define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */ |
92 | #define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */ | |
93 | #define AC0_BIT 0x200 /* ac couple channels 0,1 */ | |
94 | #define AC1_BIT 0x400 /* ac couple channels 2,3 */ | |
95 | #define APD_BIT 0x800 /* analog power down */ | |
96 | #define DPD_BIT 0x1000 /* digital power down */ | |
97 | #define TRIGGER_REG 0x2 /* trigger config register */ | |
01b0a258 FMH |
98 | #define POST_TRIGGER_BITS 0x2 |
99 | #define DELAY_TRIGGER_BITS 0x3 | |
30c687c1 BP |
100 | #define HW_TRIG_EN 0x10 /* enable hardware trigger */ |
101 | #define FIFO_START_REG 0x6 /* software start aquistion trigger */ | |
102 | #define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */ | |
103 | #define FIFO_DATA_REG 0xa /* read data */ | |
104 | #define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */ | |
105 | #define STATUS_REG 0x12 /* read only */ | |
106 | #define FNE_BIT 0x1 /* fifo not empty */ | |
107 | #define OVFL_BIT 0x8 /* fifo overflow */ | |
25985edc | 108 | #define EDAQ_BIT 0x10 /* end of acquisition interrupt */ |
30c687c1 | 109 | #define DCAL_BIT 0x20 /* offset calibration in progress */ |
25985edc LDM |
110 | #define INTR_BIT 0x40 /* interrupt has occurred */ |
111 | #define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */ | |
01b0a258 | 112 | #define ID_BITS(x) (((x) >> 8) & 0x3) |
30c687c1 BP |
113 | #define IRQ_DMA_CNTRL_REG 0x12 /* write only */ |
114 | #define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */ | |
115 | #define DMA_EN_BIT 0x8 /* enables dma */ | |
116 | #define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */ | |
117 | #define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */ | |
118 | #define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */ | |
119 | #define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */ | |
120 | #define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */ | |
01b0a258 FMH |
121 | #define I8253_BASE_REG 0x14 |
122 | #define I8253_MODE_REG 0x17 | |
30c687c1 | 123 | #define HW_COUNT_DISABLE 0x30 /* disable hardware counting of conversions */ |
01b0a258 | 124 | |
92b635c5 | 125 | struct a2150_board { |
01b0a258 | 126 | const char *name; |
30c687c1 BP |
127 | int clock[4]; /* master clock periods, in nanoseconds */ |
128 | int num_clocks; /* number of available master clock speeds */ | |
129 | int ai_speed; /* maximum conversion rate in nanoseconds */ | |
92b635c5 | 130 | }; |
01b0a258 | 131 | |
30c687c1 | 132 | /* analog input range */ |
9ced1de6 | 133 | static const struct comedi_lrange range_a2150 = { |
01b0a258 FMH |
134 | 1, |
135 | { | |
0a85b6f0 MT |
136 | RANGE(-2.828, 2.828), |
137 | } | |
01b0a258 FMH |
138 | }; |
139 | ||
30c687c1 | 140 | /* enum must match board indices */ |
01b0a258 | 141 | enum { a2150_c, a2150_s }; |
92b635c5 | 142 | static const struct a2150_board a2150_boards[] = { |
01b0a258 | 143 | { |
0a85b6f0 MT |
144 | .name = "at-a2150c", |
145 | .clock = {31250, 22676, 20833, 19531}, | |
146 | .num_clocks = 4, | |
147 | .ai_speed = 19531, | |
148 | }, | |
01b0a258 | 149 | { |
0a85b6f0 MT |
150 | .name = "at-a2150s", |
151 | .clock = {62500, 50000, 41667, 0}, | |
152 | .num_clocks = 3, | |
153 | .ai_speed = 41667, | |
154 | }, | |
01b0a258 FMH |
155 | }; |
156 | ||
157 | /* | |
158 | * Useful for shorthand access to the particular board structure | |
159 | */ | |
92b635c5 | 160 | #define thisboard ((const struct a2150_board *)dev->board_ptr) |
01b0a258 | 161 | |
3cc3872b BP |
162 | struct a2150_private { |
163 | ||
01b0a258 | 164 | volatile unsigned int count; /* number of data points left to be taken */ |
30c687c1 BP |
165 | unsigned int dma; /* dma channel */ |
166 | s16 *dma_buffer; /* dma buffer */ | |
167 | unsigned int dma_transfer_size; /* size in bytes of dma transfers */ | |
168 | int irq_dma_bits; /* irq/dma register bits */ | |
169 | int config_bits; /* config register bits */ | |
3cc3872b BP |
170 | }; |
171 | ||
3cc3872b | 172 | #define devpriv ((struct a2150_private *)dev->private) |
01b0a258 | 173 | |
da91b269 | 174 | static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s); |
01b0a258 | 175 | |
814900c9 | 176 | static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, |
0a85b6f0 | 177 | int flags); |
0a85b6f0 MT |
178 | static int a2150_set_chanlist(struct comedi_device *dev, |
179 | unsigned int start_channel, | |
180 | unsigned int num_channels); | |
01b0a258 FMH |
181 | #ifdef A2150_DEBUG |
182 | ||
da91b269 | 183 | static void ni_dump_regs(struct comedi_device *dev) |
01b0a258 | 184 | { |
5f74ea14 GKH |
185 | printk("config bits 0x%x\n", devpriv->config_bits); |
186 | printk("irq dma bits 0x%x\n", devpriv->irq_dma_bits); | |
187 | printk("status bits 0x%x\n", inw(dev->iobase + STATUS_REG)); | |
01b0a258 FMH |
188 | } |
189 | ||
190 | #endif | |
191 | ||
192 | /* interrupt service routine */ | |
70265d24 | 193 | static irqreturn_t a2150_interrupt(int irq, void *d) |
01b0a258 FMH |
194 | { |
195 | int i; | |
196 | int status; | |
197 | unsigned long flags; | |
71b5f4f1 | 198 | struct comedi_device *dev = d; |
34c43922 | 199 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 200 | struct comedi_async *async; |
ea6d0d4c | 201 | struct comedi_cmd *cmd; |
01b0a258 | 202 | unsigned int max_points, num_points, residue, leftover; |
790c5541 | 203 | short dpnt; |
01b0a258 FMH |
204 | static const int sample_size = sizeof(devpriv->dma_buffer[0]); |
205 | ||
206 | if (dev->attached == 0) { | |
207 | comedi_error(dev, "premature interrupt"); | |
208 | return IRQ_HANDLED; | |
209 | } | |
30c687c1 | 210 | /* initialize async here to make sure s is not NULL */ |
01b0a258 FMH |
211 | async = s->async; |
212 | async->events = 0; | |
213 | cmd = &async->cmd; | |
214 | ||
215 | status = inw(dev->iobase + STATUS_REG); | |
216 | ||
217 | if ((status & INTR_BIT) == 0) { | |
218 | comedi_error(dev, "spurious interrupt"); | |
219 | return IRQ_NONE; | |
220 | } | |
221 | ||
222 | if (status & OVFL_BIT) { | |
223 | comedi_error(dev, "fifo overflow"); | |
224 | a2150_cancel(dev, s); | |
225 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
226 | } | |
227 | ||
228 | if ((status & DMA_TC_BIT) == 0) { | |
229 | comedi_error(dev, "caught non-dma interrupt? Aborting."); | |
230 | a2150_cancel(dev, s); | |
231 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
232 | comedi_event(dev, s); | |
233 | return IRQ_HANDLED; | |
234 | } | |
235 | ||
236 | flags = claim_dma_lock(); | |
237 | disable_dma(devpriv->dma); | |
238 | /* clear flip-flop to make sure 2-byte registers for | |
239 | * count and address get set correctly */ | |
240 | clear_dma_ff(devpriv->dma); | |
241 | ||
30c687c1 | 242 | /* figure out how many points to read */ |
01b0a258 FMH |
243 | max_points = devpriv->dma_transfer_size / sample_size; |
244 | /* residue is the number of points left to be done on the dma | |
245 | * transfer. It should always be zero at this point unless | |
246 | * the stop_src is set to external triggering. | |
247 | */ | |
248 | residue = get_dma_residue(devpriv->dma) / sample_size; | |
249 | num_points = max_points - residue; | |
250 | if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT) | |
251 | num_points = devpriv->count; | |
252 | ||
30c687c1 | 253 | /* figure out how many points will be stored next time */ |
01b0a258 FMH |
254 | leftover = 0; |
255 | if (cmd->stop_src == TRIG_NONE) { | |
256 | leftover = devpriv->dma_transfer_size / sample_size; | |
257 | } else if (devpriv->count > max_points) { | |
258 | leftover = devpriv->count - max_points; | |
259 | if (leftover > max_points) | |
260 | leftover = max_points; | |
261 | } | |
262 | /* there should only be a residue if collection was stopped by having | |
263 | * the stop_src set to an external trigger, in which case there | |
264 | * will be no more data | |
265 | */ | |
266 | if (residue) | |
267 | leftover = 0; | |
268 | ||
269 | for (i = 0; i < num_points; i++) { | |
270 | /* write data point to comedi buffer */ | |
271 | dpnt = devpriv->dma_buffer[i]; | |
30c687c1 | 272 | /* convert from 2's complement to unsigned coding */ |
01b0a258 FMH |
273 | dpnt ^= 0x8000; |
274 | cfc_write_to_buffer(s, dpnt); | |
275 | if (cmd->stop_src == TRIG_COUNT) { | |
276 | if (--devpriv->count == 0) { /* end of acquisition */ | |
277 | a2150_cancel(dev, s); | |
278 | async->events |= COMEDI_CB_EOA; | |
279 | break; | |
280 | } | |
281 | } | |
282 | } | |
30c687c1 | 283 | /* re-enable dma */ |
01b0a258 FMH |
284 | if (leftover) { |
285 | set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer)); | |
286 | set_dma_count(devpriv->dma, leftover * sample_size); | |
287 | enable_dma(devpriv->dma); | |
288 | } | |
289 | release_dma_lock(flags); | |
290 | ||
291 | async->events |= COMEDI_CB_BLOCK; | |
292 | ||
293 | comedi_event(dev, s); | |
294 | ||
295 | /* clear interrupt */ | |
296 | outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); | |
297 | ||
298 | return IRQ_HANDLED; | |
299 | } | |
300 | ||
da91b269 | 301 | static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
01b0a258 | 302 | { |
30c687c1 | 303 | /* disable dma on card */ |
01b0a258 FMH |
304 | devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; |
305 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
306 | ||
30c687c1 | 307 | /* disable computer's dma */ |
01b0a258 FMH |
308 | disable_dma(devpriv->dma); |
309 | ||
30c687c1 | 310 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
311 | outw(0, dev->iobase + FIFO_RESET_REG); |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
0a85b6f0 MT |
316 | static int a2150_ai_cmdtest(struct comedi_device *dev, |
317 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
01b0a258 FMH |
318 | { |
319 | int err = 0; | |
320 | int tmp; | |
321 | int startChan; | |
322 | int i; | |
323 | ||
324 | /* step 1: make sure trigger sources are trivially valid */ | |
325 | ||
326 | tmp = cmd->start_src; | |
327 | cmd->start_src &= TRIG_NOW | TRIG_EXT; | |
328 | if (!cmd->start_src || tmp != cmd->start_src) | |
329 | err++; | |
330 | ||
331 | tmp = cmd->scan_begin_src; | |
332 | cmd->scan_begin_src &= TRIG_TIMER; | |
333 | if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) | |
334 | err++; | |
335 | ||
336 | tmp = cmd->convert_src; | |
337 | cmd->convert_src &= TRIG_NOW; | |
338 | if (!cmd->convert_src || tmp != cmd->convert_src) | |
339 | err++; | |
340 | ||
341 | tmp = cmd->scan_end_src; | |
342 | cmd->scan_end_src &= TRIG_COUNT; | |
343 | if (!cmd->scan_end_src || tmp != cmd->scan_end_src) | |
344 | err++; | |
345 | ||
346 | tmp = cmd->stop_src; | |
347 | cmd->stop_src &= TRIG_COUNT | TRIG_NONE; | |
348 | if (!cmd->stop_src || tmp != cmd->stop_src) | |
349 | err++; | |
350 | ||
351 | if (err) | |
352 | return 1; | |
353 | ||
949fd38c RKM |
354 | /* |
355 | * step 2: make sure trigger sources are unique and mutually | |
356 | * compatible | |
357 | */ | |
01b0a258 FMH |
358 | |
359 | if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) | |
360 | err++; | |
361 | if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) | |
362 | err++; | |
363 | ||
364 | if (err) | |
365 | return 2; | |
366 | ||
367 | /* step 3: make sure arguments are trivially compatible */ | |
368 | ||
369 | if (cmd->start_arg != 0) { | |
370 | cmd->start_arg = 0; | |
371 | err++; | |
372 | } | |
373 | if (cmd->convert_src == TRIG_TIMER) { | |
374 | if (cmd->convert_arg < thisboard->ai_speed) { | |
375 | cmd->convert_arg = thisboard->ai_speed; | |
376 | err++; | |
377 | } | |
378 | } | |
379 | if (!cmd->chanlist_len) { | |
380 | cmd->chanlist_len = 1; | |
381 | err++; | |
382 | } | |
383 | if (cmd->scan_end_arg != cmd->chanlist_len) { | |
384 | cmd->scan_end_arg = cmd->chanlist_len; | |
385 | err++; | |
386 | } | |
387 | if (cmd->stop_src == TRIG_COUNT) { | |
388 | if (!cmd->stop_arg) { | |
389 | cmd->stop_arg = 1; | |
390 | err++; | |
391 | } | |
392 | } else { /* TRIG_NONE */ | |
393 | if (cmd->stop_arg != 0) { | |
394 | cmd->stop_arg = 0; | |
395 | err++; | |
396 | } | |
397 | } | |
398 | ||
399 | if (err) | |
400 | return 3; | |
401 | ||
402 | /* step 4: fix up any arguments */ | |
403 | ||
404 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
405 | tmp = cmd->scan_begin_arg; | |
406 | a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags); | |
407 | if (tmp != cmd->scan_begin_arg) | |
408 | err++; | |
409 | } | |
410 | ||
411 | if (err) | |
412 | return 4; | |
413 | ||
30c687c1 | 414 | /* check channel/gain list against card's limitations */ |
01b0a258 FMH |
415 | if (cmd->chanlist) { |
416 | startChan = CR_CHAN(cmd->chanlist[0]); | |
417 | for (i = 1; i < cmd->chanlist_len; i++) { | |
418 | if (CR_CHAN(cmd->chanlist[i]) != (startChan + i)) { | |
419 | comedi_error(dev, | |
0a85b6f0 | 420 | "entries in chanlist must be consecutive channels, counting upwards\n"); |
01b0a258 FMH |
421 | err++; |
422 | } | |
423 | } | |
424 | if (cmd->chanlist_len == 2 && CR_CHAN(cmd->chanlist[0]) == 1) { | |
425 | comedi_error(dev, | |
0a85b6f0 | 426 | "length 2 chanlist must be channels 0,1 or channels 2,3"); |
01b0a258 FMH |
427 | err++; |
428 | } | |
429 | if (cmd->chanlist_len == 3) { | |
430 | comedi_error(dev, | |
0a85b6f0 | 431 | "chanlist must have 1,2 or 4 channels"); |
01b0a258 FMH |
432 | err++; |
433 | } | |
434 | if (CR_AREF(cmd->chanlist[0]) != CR_AREF(cmd->chanlist[1]) || | |
0a85b6f0 | 435 | CR_AREF(cmd->chanlist[2]) != CR_AREF(cmd->chanlist[3])) { |
01b0a258 | 436 | comedi_error(dev, |
0a85b6f0 | 437 | "channels 0/1 and 2/3 must have the same analog reference"); |
01b0a258 FMH |
438 | err++; |
439 | } | |
440 | } | |
441 | ||
442 | if (err) | |
443 | return 5; | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
da91b269 | 448 | static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
01b0a258 | 449 | { |
d163679c | 450 | struct comedi_async *async = s->async; |
ea6d0d4c | 451 | struct comedi_cmd *cmd = &async->cmd; |
01b0a258 FMH |
452 | unsigned long lock_flags; |
453 | unsigned int old_config_bits = devpriv->config_bits; | |
454 | unsigned int trigger_bits; | |
455 | ||
456 | if (!dev->irq || !devpriv->dma) { | |
457 | comedi_error(dev, | |
0a85b6f0 | 458 | " irq and dma required, cannot do hardware conversions"); |
01b0a258 FMH |
459 | return -1; |
460 | } | |
461 | if (cmd->flags & TRIG_RT) { | |
462 | comedi_error(dev, | |
0a85b6f0 | 463 | " dma incompatible with hard real-time interrupt (TRIG_RT), aborting"); |
01b0a258 FMH |
464 | return -1; |
465 | } | |
30c687c1 | 466 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
467 | outw(0, dev->iobase + FIFO_RESET_REG); |
468 | ||
469 | /* setup chanlist */ | |
470 | if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]), | |
0a85b6f0 | 471 | cmd->chanlist_len) < 0) |
01b0a258 FMH |
472 | return -1; |
473 | ||
30c687c1 | 474 | /* setup ac/dc coupling */ |
01b0a258 FMH |
475 | if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER) |
476 | devpriv->config_bits |= AC0_BIT; | |
477 | else | |
478 | devpriv->config_bits &= ~AC0_BIT; | |
479 | if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER) | |
480 | devpriv->config_bits |= AC1_BIT; | |
481 | else | |
482 | devpriv->config_bits &= ~AC1_BIT; | |
483 | ||
30c687c1 | 484 | /* setup timing */ |
01b0a258 FMH |
485 | a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags); |
486 | ||
30c687c1 | 487 | /* send timing, channel, config bits */ |
01b0a258 FMH |
488 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
489 | ||
30c687c1 | 490 | /* initialize number of samples remaining */ |
01b0a258 FMH |
491 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
492 | ||
30c687c1 | 493 | /* enable computer's dma */ |
01b0a258 FMH |
494 | lock_flags = claim_dma_lock(); |
495 | disable_dma(devpriv->dma); | |
496 | /* clear flip-flop to make sure 2-byte registers for | |
497 | * count and address get set correctly */ | |
498 | clear_dma_ff(devpriv->dma); | |
499 | set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer)); | |
30c687c1 | 500 | /* set size of transfer to fill in 1/3 second */ |
01b0a258 FMH |
501 | #define ONE_THIRD_SECOND 333333333 |
502 | devpriv->dma_transfer_size = | |
0a85b6f0 MT |
503 | sizeof(devpriv->dma_buffer[0]) * cmd->chanlist_len * |
504 | ONE_THIRD_SECOND / cmd->scan_begin_arg; | |
01b0a258 FMH |
505 | if (devpriv->dma_transfer_size > A2150_DMA_BUFFER_SIZE) |
506 | devpriv->dma_transfer_size = A2150_DMA_BUFFER_SIZE; | |
507 | if (devpriv->dma_transfer_size < sizeof(devpriv->dma_buffer[0])) | |
508 | devpriv->dma_transfer_size = sizeof(devpriv->dma_buffer[0]); | |
509 | devpriv->dma_transfer_size -= | |
0a85b6f0 | 510 | devpriv->dma_transfer_size % sizeof(devpriv->dma_buffer[0]); |
01b0a258 FMH |
511 | set_dma_count(devpriv->dma, devpriv->dma_transfer_size); |
512 | enable_dma(devpriv->dma); | |
513 | release_dma_lock(lock_flags); | |
514 | ||
515 | /* clear dma interrupt before enabling it, to try and get rid of that | |
516 | * one spurious interrupt that has been happening */ | |
517 | outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); | |
518 | ||
30c687c1 | 519 | /* enable dma on card */ |
01b0a258 FMH |
520 | devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT; |
521 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
522 | ||
30c687c1 | 523 | /* may need to wait 72 sampling periods if timing was changed */ |
01b0a258 FMH |
524 | i8254_load(dev->iobase + I8253_BASE_REG, 0, 2, 72, 0); |
525 | ||
30c687c1 | 526 | /* setup start triggering */ |
01b0a258 | 527 | trigger_bits = 0; |
30c687c1 | 528 | /* decide if we need to wait 72 periods for valid data */ |
01b0a258 | 529 | if (cmd->start_src == TRIG_NOW && |
0a85b6f0 MT |
530 | (old_config_bits & CLOCK_MASK) != |
531 | (devpriv->config_bits & CLOCK_MASK)) { | |
30c687c1 | 532 | /* set trigger source to delay trigger */ |
01b0a258 FMH |
533 | trigger_bits |= DELAY_TRIGGER_BITS; |
534 | } else { | |
30c687c1 | 535 | /* otherwise no delay */ |
01b0a258 FMH |
536 | trigger_bits |= POST_TRIGGER_BITS; |
537 | } | |
30c687c1 | 538 | /* enable external hardware trigger */ |
01b0a258 FMH |
539 | if (cmd->start_src == TRIG_EXT) { |
540 | trigger_bits |= HW_TRIG_EN; | |
541 | } else if (cmd->start_src == TRIG_OTHER) { | |
30c687c1 | 542 | /* XXX add support for level/slope start trigger using TRIG_OTHER */ |
01b0a258 FMH |
543 | comedi_error(dev, "you shouldn't see this?"); |
544 | } | |
30c687c1 | 545 | /* send trigger config bits */ |
01b0a258 FMH |
546 | outw(trigger_bits, dev->iobase + TRIGGER_REG); |
547 | ||
25985edc | 548 | /* start acquisition for soft trigger */ |
a96b98f2 | 549 | if (cmd->start_src == TRIG_NOW) |
01b0a258 | 550 | outw(0, dev->iobase + FIFO_START_REG); |
01b0a258 FMH |
551 | #ifdef A2150_DEBUG |
552 | ni_dump_regs(dev); | |
553 | #endif | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
da91b269 | 558 | static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 559 | struct comedi_insn *insn, unsigned int *data) |
01b0a258 FMH |
560 | { |
561 | unsigned int i, n; | |
562 | static const int timeout = 100000; | |
563 | static const int filter_delay = 36; | |
564 | ||
30c687c1 | 565 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
566 | outw(0, dev->iobase + FIFO_RESET_REG); |
567 | ||
568 | /* setup chanlist */ | |
569 | if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0) | |
570 | return -1; | |
571 | ||
30c687c1 | 572 | /* set dc coupling */ |
01b0a258 FMH |
573 | devpriv->config_bits &= ~AC0_BIT; |
574 | devpriv->config_bits &= ~AC1_BIT; | |
575 | ||
30c687c1 | 576 | /* send timing, channel, config bits */ |
01b0a258 FMH |
577 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
578 | ||
30c687c1 | 579 | /* disable dma on card */ |
01b0a258 FMH |
580 | devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; |
581 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
582 | ||
30c687c1 | 583 | /* setup start triggering */ |
01b0a258 FMH |
584 | outw(0, dev->iobase + TRIGGER_REG); |
585 | ||
25985edc | 586 | /* start acquisition for soft trigger */ |
01b0a258 FMH |
587 | outw(0, dev->iobase + FIFO_START_REG); |
588 | ||
949fd38c RKM |
589 | /* |
590 | * there is a 35.6 sample delay for data to get through the | |
591 | * antialias filter | |
592 | */ | |
01b0a258 FMH |
593 | for (n = 0; n < filter_delay; n++) { |
594 | for (i = 0; i < timeout; i++) { | |
595 | if (inw(dev->iobase + STATUS_REG) & FNE_BIT) | |
596 | break; | |
5f74ea14 | 597 | udelay(1); |
01b0a258 FMH |
598 | } |
599 | if (i == timeout) { | |
600 | comedi_error(dev, "timeout"); | |
601 | return -ETIME; | |
602 | } | |
603 | inw(dev->iobase + FIFO_DATA_REG); | |
604 | } | |
605 | ||
30c687c1 | 606 | /* read data */ |
01b0a258 FMH |
607 | for (n = 0; n < insn->n; n++) { |
608 | for (i = 0; i < timeout; i++) { | |
609 | if (inw(dev->iobase + STATUS_REG) & FNE_BIT) | |
610 | break; | |
5f74ea14 | 611 | udelay(1); |
01b0a258 FMH |
612 | } |
613 | if (i == timeout) { | |
614 | comedi_error(dev, "timeout"); | |
615 | return -ETIME; | |
616 | } | |
617 | #ifdef A2150_DEBUG | |
618 | ni_dump_regs(dev); | |
619 | #endif | |
620 | data[n] = inw(dev->iobase + FIFO_DATA_REG); | |
621 | #ifdef A2150_DEBUG | |
5f74ea14 | 622 | printk(" data is %i\n", data[n]); |
01b0a258 FMH |
623 | #endif |
624 | data[n] ^= 0x8000; | |
625 | } | |
626 | ||
30c687c1 | 627 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
628 | outw(0, dev->iobase + FIFO_RESET_REG); |
629 | ||
630 | return n; | |
631 | } | |
632 | ||
949fd38c RKM |
633 | /* |
634 | * sets bits in devpriv->clock_bits to nearest approximation of requested | |
635 | * period, adjusts requested period to actual timing. | |
636 | */ | |
da91b269 | 637 | static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, |
0a85b6f0 | 638 | int flags) |
01b0a258 FMH |
639 | { |
640 | int lub, glb, temp; | |
641 | int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index; | |
642 | int i, j; | |
643 | ||
30c687c1 | 644 | /* initialize greatest lower and least upper bounds */ |
01b0a258 FMH |
645 | lub_divisor_shift = 3; |
646 | lub_index = 0; | |
647 | lub = thisboard->clock[lub_index] * (1 << lub_divisor_shift); | |
648 | glb_divisor_shift = 0; | |
649 | glb_index = thisboard->num_clocks - 1; | |
650 | glb = thisboard->clock[glb_index] * (1 << glb_divisor_shift); | |
651 | ||
30c687c1 | 652 | /* make sure period is in available range */ |
01b0a258 FMH |
653 | if (*period < glb) |
654 | *period = glb; | |
655 | if (*period > lub) | |
656 | *period = lub; | |
657 | ||
30c687c1 | 658 | /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ |
01b0a258 | 659 | for (i = 0; i < 4; i++) { |
30c687c1 | 660 | /* there are a maximum of 4 master clocks */ |
01b0a258 | 661 | for (j = 0; j < thisboard->num_clocks; j++) { |
30c687c1 | 662 | /* temp is the period in nanosec we are evaluating */ |
01b0a258 | 663 | temp = thisboard->clock[j] * (1 << i); |
30c687c1 | 664 | /* if it is the best match yet */ |
01b0a258 FMH |
665 | if (temp < lub && temp >= *period) { |
666 | lub_divisor_shift = i; | |
667 | lub_index = j; | |
668 | lub = temp; | |
669 | } | |
670 | if (temp > glb && temp <= *period) { | |
671 | glb_divisor_shift = i; | |
672 | glb_index = j; | |
673 | glb = temp; | |
674 | } | |
675 | } | |
676 | } | |
677 | flags &= TRIG_ROUND_MASK; | |
678 | switch (flags) { | |
679 | case TRIG_ROUND_NEAREST: | |
680 | default: | |
30c687c1 | 681 | /* if least upper bound is better approximation */ |
a96b98f2 | 682 | if (lub - *period < *period - glb) |
01b0a258 | 683 | *period = lub; |
a96b98f2 | 684 | else |
01b0a258 | 685 | *period = glb; |
01b0a258 FMH |
686 | break; |
687 | case TRIG_ROUND_UP: | |
688 | *period = lub; | |
689 | break; | |
690 | case TRIG_ROUND_DOWN: | |
691 | *period = glb; | |
692 | break; | |
693 | } | |
694 | ||
30c687c1 | 695 | /* set clock bits for config register appropriately */ |
01b0a258 FMH |
696 | devpriv->config_bits &= ~CLOCK_MASK; |
697 | if (*period == lub) { | |
698 | devpriv->config_bits |= | |
0a85b6f0 MT |
699 | CLOCK_SELECT_BITS(lub_index) | |
700 | CLOCK_DIVISOR_BITS(lub_divisor_shift); | |
01b0a258 FMH |
701 | } else { |
702 | devpriv->config_bits |= | |
0a85b6f0 MT |
703 | CLOCK_SELECT_BITS(glb_index) | |
704 | CLOCK_DIVISOR_BITS(glb_divisor_shift); | |
01b0a258 FMH |
705 | } |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
0a85b6f0 MT |
710 | static int a2150_set_chanlist(struct comedi_device *dev, |
711 | unsigned int start_channel, | |
712 | unsigned int num_channels) | |
01b0a258 FMH |
713 | { |
714 | if (start_channel + num_channels > 4) | |
715 | return -1; | |
716 | ||
717 | devpriv->config_bits &= ~CHANNEL_MASK; | |
718 | ||
719 | switch (num_channels) { | |
720 | case 1: | |
721 | devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel); | |
722 | break; | |
723 | case 2: | |
724 | if (start_channel == 0) { | |
725 | devpriv->config_bits |= CHANNEL_BITS(0x2); | |
726 | } else if (start_channel == 2) { | |
727 | devpriv->config_bits |= CHANNEL_BITS(0x3); | |
728 | } else { | |
729 | return -1; | |
730 | } | |
731 | break; | |
732 | case 4: | |
733 | devpriv->config_bits |= CHANNEL_BITS(0x1); | |
734 | break; | |
735 | default: | |
736 | return -1; | |
737 | break; | |
738 | } | |
739 | ||
740 | return 0; | |
741 | } | |
90f703d3 | 742 | |
fe14fa2b HS |
743 | /* probes board type, returns offset */ |
744 | static int a2150_probe(struct comedi_device *dev) | |
745 | { | |
746 | int status = inw(dev->iobase + STATUS_REG); | |
747 | return ID_BITS(status); | |
748 | } | |
749 | ||
750 | static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) | |
751 | { | |
752 | struct comedi_subdevice *s; | |
753 | unsigned long iobase = it->options[0]; | |
754 | unsigned int irq = it->options[1]; | |
755 | unsigned int dma = it->options[2]; | |
756 | static const int timeout = 2000; | |
757 | int i; | |
8b6c5694 | 758 | int ret; |
fe14fa2b HS |
759 | |
760 | printk("comedi%d: %s: io 0x%lx", dev->minor, dev->driver->driver_name, | |
761 | iobase); | |
762 | if (irq) { | |
763 | printk(", irq %u", irq); | |
764 | } else { | |
765 | printk(", no irq"); | |
766 | } | |
767 | if (dma) { | |
768 | printk(", dma %u", dma); | |
769 | } else { | |
770 | printk(", no dma"); | |
771 | } | |
772 | printk("\n"); | |
773 | ||
774 | /* allocate and initialize dev->private */ | |
775 | if (alloc_private(dev, sizeof(struct a2150_private)) < 0) | |
776 | return -ENOMEM; | |
777 | ||
778 | if (iobase == 0) { | |
779 | printk(" io base address required\n"); | |
780 | return -EINVAL; | |
781 | } | |
782 | ||
783 | /* check if io addresses are available */ | |
784 | if (!request_region(iobase, A2150_SIZE, dev->driver->driver_name)) { | |
785 | printk(" I/O port conflict\n"); | |
786 | return -EIO; | |
787 | } | |
788 | dev->iobase = iobase; | |
789 | ||
790 | /* grab our IRQ */ | |
791 | if (irq) { | |
792 | /* check that irq is supported */ | |
793 | if (irq < 3 || irq == 8 || irq == 13 || irq > 15) { | |
794 | printk(" invalid irq line %u\n", irq); | |
795 | return -EINVAL; | |
796 | } | |
797 | if (request_irq(irq, a2150_interrupt, 0, | |
798 | dev->driver->driver_name, dev)) { | |
799 | printk("unable to allocate irq %u\n", irq); | |
800 | return -EINVAL; | |
801 | } | |
802 | devpriv->irq_dma_bits |= IRQ_LVL_BITS(irq); | |
803 | dev->irq = irq; | |
804 | } | |
805 | /* initialize dma */ | |
806 | if (dma) { | |
807 | if (dma == 4 || dma > 7) { | |
808 | printk(" invalid dma channel %u\n", dma); | |
809 | return -EINVAL; | |
810 | } | |
811 | if (request_dma(dma, dev->driver->driver_name)) { | |
812 | printk(" failed to allocate dma channel %u\n", dma); | |
813 | return -EINVAL; | |
814 | } | |
815 | devpriv->dma = dma; | |
816 | devpriv->dma_buffer = | |
817 | kmalloc(A2150_DMA_BUFFER_SIZE, GFP_KERNEL | GFP_DMA); | |
818 | if (devpriv->dma_buffer == NULL) | |
819 | return -ENOMEM; | |
820 | ||
821 | disable_dma(dma); | |
822 | set_dma_mode(dma, DMA_MODE_READ); | |
823 | ||
824 | devpriv->irq_dma_bits |= DMA_CHAN_BITS(dma); | |
825 | } | |
826 | ||
827 | dev->board_ptr = a2150_boards + a2150_probe(dev); | |
828 | dev->board_name = thisboard->name; | |
829 | ||
8b6c5694 HS |
830 | ret = comedi_alloc_subdevices(dev, 1); |
831 | if (ret) | |
832 | return ret; | |
fe14fa2b HS |
833 | |
834 | /* analog input subdevice */ | |
835 | s = dev->subdevices + 0; | |
836 | dev->read_subdev = s; | |
837 | s->type = COMEDI_SUBD_AI; | |
838 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER | SDF_CMD_READ; | |
839 | s->n_chan = 4; | |
840 | s->len_chanlist = 4; | |
841 | s->maxdata = 0xffff; | |
842 | s->range_table = &range_a2150; | |
843 | s->do_cmd = a2150_ai_cmd; | |
844 | s->do_cmdtest = a2150_ai_cmdtest; | |
845 | s->insn_read = a2150_ai_rinsn; | |
846 | s->cancel = a2150_cancel; | |
847 | ||
848 | /* need to do this for software counting of completed conversions, to | |
849 | * prevent hardware count from stopping acquisition */ | |
850 | outw(HW_COUNT_DISABLE, dev->iobase + I8253_MODE_REG); | |
851 | ||
852 | /* set card's irq and dma levels */ | |
853 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
854 | ||
855 | /* reset and sync adc clock circuitry */ | |
856 | outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG); | |
857 | outw_p(DPD_BIT, dev->iobase + CONFIG_REG); | |
858 | /* initialize configuration register */ | |
859 | devpriv->config_bits = 0; | |
860 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); | |
861 | /* wait until offset calibration is done, then enable analog inputs */ | |
862 | for (i = 0; i < timeout; i++) { | |
863 | if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0) | |
864 | break; | |
865 | udelay(1000); | |
866 | } | |
867 | if (i == timeout) { | |
868 | printk | |
869 | (" timed out waiting for offset calibration to complete\n"); | |
870 | return -ETIME; | |
871 | } | |
872 | devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT; | |
873 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); | |
874 | ||
875 | return 0; | |
876 | }; | |
877 | ||
484ecc95 | 878 | static void a2150_detach(struct comedi_device *dev) |
fe14fa2b | 879 | { |
fe14fa2b | 880 | if (dev->iobase) { |
fe14fa2b HS |
881 | outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG); |
882 | release_region(dev->iobase, A2150_SIZE); | |
883 | } | |
fe14fa2b HS |
884 | if (dev->irq) |
885 | free_irq(dev->irq, dev); | |
886 | if (devpriv) { | |
887 | if (devpriv->dma) | |
888 | free_dma(devpriv->dma); | |
889 | kfree(devpriv->dma_buffer); | |
890 | } | |
fe14fa2b HS |
891 | }; |
892 | ||
893 | static struct comedi_driver ni_at_a2150_driver = { | |
894 | .driver_name = "ni_at_a2150", | |
895 | .module = THIS_MODULE, | |
896 | .attach = a2150_attach, | |
897 | .detach = a2150_detach, | |
898 | }; | |
899 | module_comedi_driver(ni_at_a2150_driver); | |
900 | ||
90f703d3 AT |
901 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
902 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
903 | MODULE_LICENSE("GPL"); |