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staging: comedi: pcmuio: fix possible NULL deref on detach
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_at_a2150.c
CommitLineData
01b0a258
FMH		 1/*
2 comedi/drivers/ni_at_a2150.c
3 Driver for National Instruments AT-A2150 boards
4 Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 COMEDI - Linux Control and Measurement Device Interface
7 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23************************************************************************
24*/
25/*
26Driver: ni_at_a2150
27Description: National Instruments AT-A2150
28Author: Frank Mori Hess
29Status: works
30Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s)
31
32If you want to ac couple the board's inputs, use AREF_OTHER.
33
34Configuration options:
35 [0] - I/O port base address
36 [1] - IRQ (optional, required for timed conversions)
37 [2] - DMA (optional, required for timed conversions)
38
39*/
40/*
41Yet another driver for obsolete hardware brought to you by Frank Hess.
42Testing and debugging help provided by Dave Andruczyk.
43
44This driver supports the boards:
45
46AT-A2150C
47AT-A2150S
48
49The only difference is their master clock frequencies.
50
51Options:
52 [0] - base io address
53 [1] - irq
54 [2] - dma channel
55
56References (from ftp://ftp.natinst.com/support/manuals):
57
58 320360.pdf AT-A2150 User Manual
59
60TODO:
61
62analog level triggering
63TRIG_WAKE_EOS
64
65*/
66
25436dc9 67#include <linux/interrupt.h>
5a0e3ad6 68#include <linux/slab.h>
01b0a258
FMH		 69#include "../comedidev.h"
70
71#include <linux/ioport.h>
845d131e 72#include <linux/io.h>
01b0a258
FMH		 73#include <asm/dma.h>
74
75#include "8253.h"
76#include "comedi_fc.h"
77
78#define A2150_SIZE 28
30c687c1 79#define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */
01b0a258 80
30c687c1
BP		 81/* #define A2150_DEBUG enable debugging code */
82#undef A2150_DEBUG /* disable debugging code */
01b0a258
FMH		 83
84/* Registers and bits */
85#define CONFIG_REG 0x0
86#define CHANNEL_BITS(x) ((x) & 0x7)
87#define CHANNEL_MASK 0x7
88#define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3)
89#define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5)
90#define CLOCK_MASK (0xf << 3)
30c687c1
BP		 91#define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */
92#define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */
93#define AC0_BIT 0x200 /* ac couple channels 0,1 */
94#define AC1_BIT 0x400 /* ac couple channels 2,3 */
95#define APD_BIT 0x800 /* analog power down */
96#define DPD_BIT 0x1000 /* digital power down */
97#define TRIGGER_REG 0x2 /* trigger config register */
01b0a258
FMH		 98#define POST_TRIGGER_BITS 0x2
99#define DELAY_TRIGGER_BITS 0x3
30c687c1
BP		 100#define HW_TRIG_EN 0x10 /* enable hardware trigger */
101#define FIFO_START_REG 0x6 /* software start aquistion trigger */
102#define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */
103#define FIFO_DATA_REG 0xa /* read data */
104#define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */
105#define STATUS_REG 0x12 /* read only */
106#define FNE_BIT 0x1 /* fifo not empty */
107#define OVFL_BIT 0x8 /* fifo overflow */
25985edc 108#define EDAQ_BIT 0x10 /* end of acquisition interrupt */
30c687c1 109#define DCAL_BIT 0x20 /* offset calibration in progress */
25985edc
LDM		 110#define INTR_BIT 0x40 /* interrupt has occurred */
111#define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */
01b0a258 112#define ID_BITS(x) (((x) >> 8) & 0x3)
30c687c1
BP		 113#define IRQ_DMA_CNTRL_REG 0x12 /* write only */
114#define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */
115#define DMA_EN_BIT 0x8 /* enables dma */
116#define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */
117#define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */
118#define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */
119#define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */
120#define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */
01b0a258
FMH		 121#define I8253_BASE_REG 0x14
122#define I8253_MODE_REG 0x17
30c687c1 123#define HW_COUNT_DISABLE 0x30 /* disable hardware counting of conversions */
01b0a258 124
92b635c5 125struct a2150_board {
01b0a258 126 const char *name;
30c687c1
BP		 127 int clock[4]; /* master clock periods, in nanoseconds */
128 int num_clocks; /* number of available master clock speeds */
129 int ai_speed; /* maximum conversion rate in nanoseconds */
92b635c5 130};
01b0a258 131
30c687c1 132/* analog input range */
9ced1de6 133static const struct comedi_lrange range_a2150 = {
01b0a258
FMH		 134 1,
135 {
0a85b6f0
MT		 136 RANGE(-2.828, 2.828),
137 }
01b0a258
FMH		 138};
139
30c687c1 140/* enum must match board indices */
01b0a258 141enum { a2150_c, a2150_s };
92b635c5 142static const struct a2150_board a2150_boards[] = {
01b0a258 143 {
0a85b6f0
MT		 144 .name = "at-a2150c",
145 .clock = {31250, 22676, 20833, 19531},
146 .num_clocks = 4,
147 .ai_speed = 19531,
148 },
01b0a258 149 {
0a85b6f0
MT		 150 .name = "at-a2150s",
151 .clock = {62500, 50000, 41667, 0},
152 .num_clocks = 3,
153 .ai_speed = 41667,
154 },
01b0a258
FMH		 155};
156
3cc3872b
BP		 157struct a2150_private {
158
01b0a258 159 volatile unsigned int count; /* number of data points left to be taken */
30c687c1
BP		 160 unsigned int dma; /* dma channel */
161 s16 *dma_buffer; /* dma buffer */
162 unsigned int dma_transfer_size; /* size in bytes of dma transfers */
163 int irq_dma_bits; /* irq/dma register bits */
164 int config_bits; /* config register bits */
3cc3872b
BP		 165};
166
da91b269 167static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
01b0a258 168
814900c9 169static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
0a85b6f0 170 int flags);
0a85b6f0
MT		 171static int a2150_set_chanlist(struct comedi_device *dev,
172 unsigned int start_channel,
173 unsigned int num_channels);
01b0a258
FMH		 174#ifdef A2150_DEBUG
175
da91b269 176static void ni_dump_regs(struct comedi_device *dev)
01b0a258 177{
9a1a6cf8
HS		 178 struct a2150_private *devpriv = dev->private;
179
5f74ea14
GKH		 180 printk("config bits 0x%x\n", devpriv->config_bits);
181 printk("irq dma bits 0x%x\n", devpriv->irq_dma_bits);
182 printk("status bits 0x%x\n", inw(dev->iobase + STATUS_REG));
01b0a258
FMH		 183}
184
185#endif
186
187/* interrupt service routine */
70265d24 188static irqreturn_t a2150_interrupt(int irq, void *d)
01b0a258
FMH		 189{
190 int i;
191 int status;
192 unsigned long flags;
71b5f4f1 193 struct comedi_device *dev = d;
9a1a6cf8 194 struct a2150_private *devpriv = dev->private;
34c43922 195 struct comedi_subdevice *s = dev->read_subdev;
d163679c 196 struct comedi_async *async;
ea6d0d4c 197 struct comedi_cmd *cmd;
01b0a258 198 unsigned int max_points, num_points, residue, leftover;
790c5541 199 short dpnt;
01b0a258
FMH		 200 static const int sample_size = sizeof(devpriv->dma_buffer[0]);
201
a7401cdd 202 if (!dev->attached) {
01b0a258
FMH		 203 comedi_error(dev, "premature interrupt");
204 return IRQ_HANDLED;
205 }
30c687c1 206 /* initialize async here to make sure s is not NULL */
01b0a258
FMH		 207 async = s->async;
208 async->events = 0;
209 cmd = &async->cmd;
210
211 status = inw(dev->iobase + STATUS_REG);
212
213 if ((status & INTR_BIT) == 0) {
214 comedi_error(dev, "spurious interrupt");
215 return IRQ_NONE;
216 }
217
218 if (status & OVFL_BIT) {
219 comedi_error(dev, "fifo overflow");
220 a2150_cancel(dev, s);
221 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
222 }
223
224 if ((status & DMA_TC_BIT) == 0) {
225 comedi_error(dev, "caught non-dma interrupt? Aborting.");
226 a2150_cancel(dev, s);
227 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
228 comedi_event(dev, s);
229 return IRQ_HANDLED;
230 }
231
232 flags = claim_dma_lock();
233 disable_dma(devpriv->dma);
234 /* clear flip-flop to make sure 2-byte registers for
235 * count and address get set correctly */
236 clear_dma_ff(devpriv->dma);
237
30c687c1 238 /* figure out how many points to read */
01b0a258
FMH		 239 max_points = devpriv->dma_transfer_size / sample_size;
240 /* residue is the number of points left to be done on the dma
241 * transfer. It should always be zero at this point unless
242 * the stop_src is set to external triggering.
243 */
244 residue = get_dma_residue(devpriv->dma) / sample_size;
245 num_points = max_points - residue;
246 if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT)
247 num_points = devpriv->count;
248
30c687c1 249 /* figure out how many points will be stored next time */
01b0a258
FMH		 250 leftover = 0;
251 if (cmd->stop_src == TRIG_NONE) {
252 leftover = devpriv->dma_transfer_size / sample_size;
253 } else if (devpriv->count > max_points) {
254 leftover = devpriv->count - max_points;
255 if (leftover > max_points)
256 leftover = max_points;
257 }
258 /* there should only be a residue if collection was stopped by having
259 * the stop_src set to an external trigger, in which case there
260 * will be no more data
261 */
262 if (residue)
263 leftover = 0;
264
265 for (i = 0; i < num_points; i++) {
266 /* write data point to comedi buffer */
267 dpnt = devpriv->dma_buffer[i];
30c687c1 268 /* convert from 2's complement to unsigned coding */
01b0a258
FMH		 269 dpnt ^= 0x8000;
270 cfc_write_to_buffer(s, dpnt);
271 if (cmd->stop_src == TRIG_COUNT) {
272 if (--devpriv->count == 0) { /* end of acquisition */
273 a2150_cancel(dev, s);
274 async->events |= COMEDI_CB_EOA;
275 break;
276 }
277 }
278 }
30c687c1 279 /* re-enable dma */
01b0a258
FMH		 280 if (leftover) {
281 set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer));
282 set_dma_count(devpriv->dma, leftover * sample_size);
283 enable_dma(devpriv->dma);
284 }
285 release_dma_lock(flags);
286
287 async->events |= COMEDI_CB_BLOCK;
288
289 comedi_event(dev, s);
290
291 /* clear interrupt */
292 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
293
294 return IRQ_HANDLED;
295}
296
da91b269 297static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
01b0a258 298{
9a1a6cf8
HS		 299 struct a2150_private *devpriv = dev->private;
300
30c687c1 301 /* disable dma on card */
01b0a258
FMH		 302 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
303 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
304
30c687c1 305 /* disable computer's dma */
01b0a258
FMH		 306 disable_dma(devpriv->dma);
307
30c687c1 308 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 309 outw(0, dev->iobase + FIFO_RESET_REG);
310
311 return 0;
312}
313
0a85b6f0
MT		 314static int a2150_ai_cmdtest(struct comedi_device *dev,
315 struct comedi_subdevice *s, struct comedi_cmd *cmd)
01b0a258 316{
e8e1560a 317 const struct a2150_board *thisboard = comedi_board(dev);
01b0a258
FMH		 318 int err = 0;
319 int tmp;
320 int startChan;
321 int i;
322
27020ffe 323 /* Step 1 : check if triggers are trivially valid */
01b0a258 324
27020ffe
HS		 325 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
326 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER);
327 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
328 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
329 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
01b0a258
FMH		 330
331 if (err)
332 return 1;
333
27020ffe 334 /* Step 2a : make sure trigger sources are unique */
01b0a258 335
27020ffe
HS		 336 err |= cfc_check_trigger_is_unique(cmd->start_src);
337 err |= cfc_check_trigger_is_unique(cmd->stop_src);
338
339 /* Step 2b : and mutually compatible */
01b0a258
FMH		 340
341 if (err)
342 return 2;
343
dd254844 344 /* Step 3: check if arguments are trivially valid */
01b0a258 345
dd254844
HS		 346 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
347
348 if (cmd->convert_src == TRIG_TIMER)
349 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
350 thisboard->ai_speed);
351
352 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
353 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
354
355 if (cmd->stop_src == TRIG_COUNT)
356 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
357 else /* TRIG_NONE */
358 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
01b0a258
FMH		 359
360 if (err)
361 return 3;
362
363 /* step 4: fix up any arguments */
364
365 if (cmd->scan_begin_src == TRIG_TIMER) {
366 tmp = cmd->scan_begin_arg;
367 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
368 if (tmp != cmd->scan_begin_arg)
369 err++;
370 }
371
372 if (err)
373 return 4;
374
30c687c1 375 /* check channel/gain list against card's limitations */
01b0a258
FMH		 376 if (cmd->chanlist) {
377 startChan = CR_CHAN(cmd->chanlist[0]);
378 for (i = 1; i < cmd->chanlist_len; i++) {
379 if (CR_CHAN(cmd->chanlist[i]) != (startChan + i)) {
380 comedi_error(dev,
0a85b6f0 381 "entries in chanlist must be consecutive channels, counting upwards\n");
01b0a258
FMH		 382 err++;
383 }
384 }
385 if (cmd->chanlist_len == 2 && CR_CHAN(cmd->chanlist[0]) == 1) {
386 comedi_error(dev,
0a85b6f0 387 "length 2 chanlist must be channels 0,1 or channels 2,3");
01b0a258
FMH		 388 err++;
389 }
390 if (cmd->chanlist_len == 3) {
391 comedi_error(dev,
0a85b6f0 392 "chanlist must have 1,2 or 4 channels");
01b0a258
FMH		 393 err++;
394 }
395 if (CR_AREF(cmd->chanlist[0]) != CR_AREF(cmd->chanlist[1]) ||
0a85b6f0 396 CR_AREF(cmd->chanlist[2]) != CR_AREF(cmd->chanlist[3])) {
01b0a258 397 comedi_error(dev,
0a85b6f0 398 "channels 0/1 and 2/3 must have the same analog reference");
01b0a258
FMH		 399 err++;
400 }
401 }
402
403 if (err)
404 return 5;
405
406 return 0;
407}
408
da91b269 409static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
01b0a258 410{
9a1a6cf8 411 struct a2150_private *devpriv = dev->private;
d163679c 412 struct comedi_async *async = s->async;
ea6d0d4c 413 struct comedi_cmd *cmd = &async->cmd;
01b0a258
FMH		 414 unsigned long lock_flags;
415 unsigned int old_config_bits = devpriv->config_bits;
416 unsigned int trigger_bits;
417
418 if (!dev->irq || !devpriv->dma) {
419 comedi_error(dev,
0a85b6f0 420 " irq and dma required, cannot do hardware conversions");
01b0a258
FMH		 421 return -1;
422 }
423 if (cmd->flags & TRIG_RT) {
424 comedi_error(dev,
0a85b6f0 425 " dma incompatible with hard real-time interrupt (TRIG_RT), aborting");
01b0a258
FMH		 426 return -1;
427 }
30c687c1 428 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 429 outw(0, dev->iobase + FIFO_RESET_REG);
430
431 /* setup chanlist */
432 if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]),
0a85b6f0 433 cmd->chanlist_len) < 0)
01b0a258
FMH		 434 return -1;
435
30c687c1 436 /* setup ac/dc coupling */
01b0a258
FMH		 437 if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER)
438 devpriv->config_bits |= AC0_BIT;
439 else
440 devpriv->config_bits &= ~AC0_BIT;
441 if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER)
442 devpriv->config_bits |= AC1_BIT;
443 else
444 devpriv->config_bits &= ~AC1_BIT;
445
30c687c1 446 /* setup timing */
01b0a258
FMH		 447 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
448
30c687c1 449 /* send timing, channel, config bits */
01b0a258
FMH		 450 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
451
30c687c1 452 /* initialize number of samples remaining */
01b0a258
FMH		 453 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
454
30c687c1 455 /* enable computer's dma */
01b0a258
FMH		 456 lock_flags = claim_dma_lock();
457 disable_dma(devpriv->dma);
458 /* clear flip-flop to make sure 2-byte registers for
459 * count and address get set correctly */
460 clear_dma_ff(devpriv->dma);
461 set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer));
30c687c1 462 /* set size of transfer to fill in 1/3 second */
01b0a258
FMH		 463#define ONE_THIRD_SECOND 333333333
464 devpriv->dma_transfer_size =
0a85b6f0
MT		 465 sizeof(devpriv->dma_buffer[0]) * cmd->chanlist_len *
466 ONE_THIRD_SECOND / cmd->scan_begin_arg;
01b0a258
FMH		 467 if (devpriv->dma_transfer_size > A2150_DMA_BUFFER_SIZE)
468 devpriv->dma_transfer_size = A2150_DMA_BUFFER_SIZE;
469 if (devpriv->dma_transfer_size < sizeof(devpriv->dma_buffer[0]))
470 devpriv->dma_transfer_size = sizeof(devpriv->dma_buffer[0]);
471 devpriv->dma_transfer_size -=
0a85b6f0 472 devpriv->dma_transfer_size % sizeof(devpriv->dma_buffer[0]);
01b0a258
FMH		 473 set_dma_count(devpriv->dma, devpriv->dma_transfer_size);
474 enable_dma(devpriv->dma);
475 release_dma_lock(lock_flags);
476
477 /* clear dma interrupt before enabling it, to try and get rid of that
478 * one spurious interrupt that has been happening */
479 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
480
30c687c1 481 /* enable dma on card */
01b0a258
FMH		 482 devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT;
483 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
484
30c687c1 485 /* may need to wait 72 sampling periods if timing was changed */
01b0a258
FMH		 486 i8254_load(dev->iobase + I8253_BASE_REG, 0, 2, 72, 0);
487
30c687c1 488 /* setup start triggering */
01b0a258 489 trigger_bits = 0;
30c687c1 490 /* decide if we need to wait 72 periods for valid data */
01b0a258 491 if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT		 492 (old_config_bits & CLOCK_MASK) !=
493 (devpriv->config_bits & CLOCK_MASK)) {
30c687c1 494 /* set trigger source to delay trigger */
01b0a258
FMH		 495 trigger_bits |= DELAY_TRIGGER_BITS;
496 } else {
30c687c1 497 /* otherwise no delay */
01b0a258
FMH		 498 trigger_bits |= POST_TRIGGER_BITS;
499 }
30c687c1 500 /* enable external hardware trigger */
01b0a258
FMH		 501 if (cmd->start_src == TRIG_EXT) {
502 trigger_bits |= HW_TRIG_EN;
503 } else if (cmd->start_src == TRIG_OTHER) {
30c687c1 504 /* XXX add support for level/slope start trigger using TRIG_OTHER */
01b0a258
FMH		 505 comedi_error(dev, "you shouldn't see this?");
506 }
30c687c1 507 /* send trigger config bits */
01b0a258
FMH		 508 outw(trigger_bits, dev->iobase + TRIGGER_REG);
509
25985edc 510 /* start acquisition for soft trigger */
a96b98f2 511 if (cmd->start_src == TRIG_NOW)
01b0a258 512 outw(0, dev->iobase + FIFO_START_REG);
01b0a258
FMH		 513#ifdef A2150_DEBUG
514 ni_dump_regs(dev);
515#endif
516
517 return 0;
518}
519
da91b269 520static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 521 struct comedi_insn *insn, unsigned int *data)
01b0a258 522{
9a1a6cf8 523 struct a2150_private *devpriv = dev->private;
01b0a258
FMH		 524 unsigned int i, n;
525 static const int timeout = 100000;
526 static const int filter_delay = 36;
527
30c687c1 528 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 529 outw(0, dev->iobase + FIFO_RESET_REG);
530
531 /* setup chanlist */
532 if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0)
533 return -1;
534
30c687c1 535 /* set dc coupling */
01b0a258
FMH		 536 devpriv->config_bits &= ~AC0_BIT;
537 devpriv->config_bits &= ~AC1_BIT;
538
30c687c1 539 /* send timing, channel, config bits */
01b0a258
FMH		 540 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
541
30c687c1 542 /* disable dma on card */
01b0a258
FMH		 543 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
544 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
545
30c687c1 546 /* setup start triggering */
01b0a258
FMH		 547 outw(0, dev->iobase + TRIGGER_REG);
548
25985edc 549 /* start acquisition for soft trigger */
01b0a258
FMH		 550 outw(0, dev->iobase + FIFO_START_REG);
551
949fd38c
RKM		 552 /*
553 * there is a 35.6 sample delay for data to get through the
554 * antialias filter
555 */
01b0a258
FMH		 556 for (n = 0; n < filter_delay; n++) {
557 for (i = 0; i < timeout; i++) {
558 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
559 break;
5f74ea14 560 udelay(1);
01b0a258
FMH		 561 }
562 if (i == timeout) {
563 comedi_error(dev, "timeout");
564 return -ETIME;
565 }
566 inw(dev->iobase + FIFO_DATA_REG);
567 }
568
30c687c1 569 /* read data */
01b0a258
FMH		 570 for (n = 0; n < insn->n; n++) {
571 for (i = 0; i < timeout; i++) {
572 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
573 break;
5f74ea14 574 udelay(1);
01b0a258
FMH		 575 }
576 if (i == timeout) {
577 comedi_error(dev, "timeout");
578 return -ETIME;
579 }
580#ifdef A2150_DEBUG
581 ni_dump_regs(dev);
582#endif
583 data[n] = inw(dev->iobase + FIFO_DATA_REG);
584#ifdef A2150_DEBUG
5f74ea14 585 printk(" data is %i\n", data[n]);
01b0a258
FMH		 586#endif
587 data[n] ^= 0x8000;
588 }
589
30c687c1 590 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 591 outw(0, dev->iobase + FIFO_RESET_REG);
592
593 return n;
594}
595
949fd38c
RKM		 596/*
597 * sets bits in devpriv->clock_bits to nearest approximation of requested
598 * period, adjusts requested period to actual timing.
599 */
da91b269 600static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
0a85b6f0 601 int flags)
01b0a258 602{
e8e1560a 603 const struct a2150_board *thisboard = comedi_board(dev);
9a1a6cf8 604 struct a2150_private *devpriv = dev->private;
01b0a258
FMH		 605 int lub, glb, temp;
606 int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index;
607 int i, j;
608
30c687c1 609 /* initialize greatest lower and least upper bounds */
01b0a258
FMH		 610 lub_divisor_shift = 3;
611 lub_index = 0;
612 lub = thisboard->clock[lub_index] * (1 << lub_divisor_shift);
613 glb_divisor_shift = 0;
614 glb_index = thisboard->num_clocks - 1;
615 glb = thisboard->clock[glb_index] * (1 << glb_divisor_shift);
616
30c687c1 617 /* make sure period is in available range */
01b0a258
FMH		 618 if (*period < glb)
619 *period = glb;
620 if (*period > lub)
621 *period = lub;
622
30c687c1 623 /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */
01b0a258 624 for (i = 0; i < 4; i++) {
30c687c1 625 /* there are a maximum of 4 master clocks */
01b0a258 626 for (j = 0; j < thisboard->num_clocks; j++) {
30c687c1 627 /* temp is the period in nanosec we are evaluating */
01b0a258 628 temp = thisboard->clock[j] * (1 << i);
30c687c1 629 /* if it is the best match yet */
01b0a258
FMH		 630 if (temp < lub && temp >= *period) {
631 lub_divisor_shift = i;
632 lub_index = j;
633 lub = temp;
634 }
635 if (temp > glb && temp <= *period) {
636 glb_divisor_shift = i;
637 glb_index = j;
638 glb = temp;
639 }
640 }
641 }
642 flags &= TRIG_ROUND_MASK;
643 switch (flags) {
644 case TRIG_ROUND_NEAREST:
645 default:
30c687c1 646 /* if least upper bound is better approximation */
a96b98f2 647 if (lub - *period < *period - glb)
01b0a258 648 *period = lub;
a96b98f2 649 else
01b0a258 650 *period = glb;
01b0a258
FMH		 651 break;
652 case TRIG_ROUND_UP:
653 *period = lub;
654 break;
655 case TRIG_ROUND_DOWN:
656 *period = glb;
657 break;
658 }
659
30c687c1 660 /* set clock bits for config register appropriately */
01b0a258
FMH		 661 devpriv->config_bits &= ~CLOCK_MASK;
662 if (*period == lub) {
663 devpriv->config_bits |=
0a85b6f0
MT		 664 CLOCK_SELECT_BITS(lub_index) |
665 CLOCK_DIVISOR_BITS(lub_divisor_shift);
01b0a258
FMH		 666 } else {
667 devpriv->config_bits |=
0a85b6f0
MT		 668 CLOCK_SELECT_BITS(glb_index) |
669 CLOCK_DIVISOR_BITS(glb_divisor_shift);
01b0a258
FMH		 670 }
671
672 return 0;
673}
674
0a85b6f0
MT		 675static int a2150_set_chanlist(struct comedi_device *dev,
676 unsigned int start_channel,
677 unsigned int num_channels)
01b0a258 678{
9a1a6cf8
HS		 679 struct a2150_private *devpriv = dev->private;
680
01b0a258
FMH		 681 if (start_channel + num_channels > 4)
682 return -1;
683
684 devpriv->config_bits &= ~CHANNEL_MASK;
685
686 switch (num_channels) {
687 case 1:
688 devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel);
689 break;
690 case 2:
691 if (start_channel == 0) {
692 devpriv->config_bits |= CHANNEL_BITS(0x2);
693 } else if (start_channel == 2) {
694 devpriv->config_bits |= CHANNEL_BITS(0x3);
695 } else {
696 return -1;
697 }
698 break;
699 case 4:
700 devpriv->config_bits |= CHANNEL_BITS(0x1);
701 break;
702 default:
703 return -1;
704 break;
705 }
706
707 return 0;
708}
90f703d3 709
fe14fa2b
HS		 710/* probes board type, returns offset */
711static int a2150_probe(struct comedi_device *dev)
712{
713 int status = inw(dev->iobase + STATUS_REG);
714 return ID_BITS(status);
715}
716
717static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it)
718{
e8e1560a 719 const struct a2150_board *thisboard = comedi_board(dev);
9a1a6cf8 720 struct a2150_private *devpriv;
fe14fa2b 721 struct comedi_subdevice *s;
fe14fa2b
HS		 722 unsigned int irq = it->options[1];
723 unsigned int dma = it->options[2];
724 static const int timeout = 2000;
725 int i;
8b6c5694 726 int ret;
fe14fa2b 727
c34fa261
HS		 728 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
729 if (!devpriv)
730 return -ENOMEM;
731 dev->private = devpriv;
fe14fa2b 732
3671cae1
HS		 733 ret = comedi_request_region(dev, it->options[0], A2150_SIZE);
734 if (ret)
735 return ret;
fe14fa2b
HS		 736
737 /* grab our IRQ */
738 if (irq) {
739 /* check that irq is supported */
740 if (irq < 3 || irq == 8 || irq == 13 || irq > 15) {
741 printk(" invalid irq line %u\n", irq);
742 return -EINVAL;
743 }
744 if (request_irq(irq, a2150_interrupt, 0,
745 dev->driver->driver_name, dev)) {
746 printk("unable to allocate irq %u\n", irq);
747 return -EINVAL;
748 }
749 devpriv->irq_dma_bits |= IRQ_LVL_BITS(irq);
750 dev->irq = irq;
751 }
752 /* initialize dma */
753 if (dma) {
754 if (dma == 4 || dma > 7) {
755 printk(" invalid dma channel %u\n", dma);
756 return -EINVAL;
757 }
758 if (request_dma(dma, dev->driver->driver_name)) {
759 printk(" failed to allocate dma channel %u\n", dma);
760 return -EINVAL;
761 }
762 devpriv->dma = dma;
763 devpriv->dma_buffer =
764 kmalloc(A2150_DMA_BUFFER_SIZE, GFP_KERNEL | GFP_DMA);
765 if (devpriv->dma_buffer == NULL)
766 return -ENOMEM;
767
768 disable_dma(dma);
769 set_dma_mode(dma, DMA_MODE_READ);
770
771 devpriv->irq_dma_bits |= DMA_CHAN_BITS(dma);
772 }
773
774 dev->board_ptr = a2150_boards + a2150_probe(dev);
e8e1560a 775 thisboard = comedi_board(dev);
fe14fa2b
HS		 776 dev->board_name = thisboard->name;
777
8b6c5694
HS		 778 ret = comedi_alloc_subdevices(dev, 1);
779 if (ret)
780 return ret;
fe14fa2b
HS		 781
782 /* analog input subdevice */
ca3caabb 783 s = &dev->subdevices[0];
fe14fa2b
HS		 784 dev->read_subdev = s;
785 s->type = COMEDI_SUBD_AI;
786 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER | SDF_CMD_READ;
787 s->n_chan = 4;
788 s->len_chanlist = 4;
789 s->maxdata = 0xffff;
790 s->range_table = &range_a2150;
791 s->do_cmd = a2150_ai_cmd;
792 s->do_cmdtest = a2150_ai_cmdtest;
793 s->insn_read = a2150_ai_rinsn;
794 s->cancel = a2150_cancel;
795
796 /* need to do this for software counting of completed conversions, to
797 * prevent hardware count from stopping acquisition */
798 outw(HW_COUNT_DISABLE, dev->iobase + I8253_MODE_REG);
799
800 /* set card's irq and dma levels */
801 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
802
803 /* reset and sync adc clock circuitry */
804 outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG);
805 outw_p(DPD_BIT, dev->iobase + CONFIG_REG);
806 /* initialize configuration register */
807 devpriv->config_bits = 0;
808 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
809 /* wait until offset calibration is done, then enable analog inputs */
810 for (i = 0; i < timeout; i++) {
811 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
812 break;
813 udelay(1000);
814 }
815 if (i == timeout) {
816 printk
817 (" timed out waiting for offset calibration to complete\n");
818 return -ETIME;
819 }
820 devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT;
821 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
822
823 return 0;
824};
825
484ecc95 826static void a2150_detach(struct comedi_device *dev)
fe14fa2b 827{
9a1a6cf8
HS		 828 struct a2150_private *devpriv = dev->private;
829
a32c6d00 830 if (dev->iobase)
fe14fa2b 831 outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG);
fe14fa2b
HS		 832 if (devpriv) {
833 if (devpriv->dma)
834 free_dma(devpriv->dma);
835 kfree(devpriv->dma_buffer);
836 }
a32c6d00 837 comedi_legacy_detach(dev);
fe14fa2b
HS		 838};
839
840static struct comedi_driver ni_at_a2150_driver = {
841 .driver_name = "ni_at_a2150",
842 .module = THIS_MODULE,
843 .attach = a2150_attach,
844 .detach = a2150_detach,
845};
846module_comedi_driver(ni_at_a2150_driver);
847
90f703d3
AT		 848MODULE_AUTHOR("Comedi http://www.comedi.org");
849MODULE_DESCRIPTION("Comedi low-level driver");
850MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)