projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Staging: comedi: remove C99 comments in s526.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_65xx.c
CommitLineData
5211d97c
JG		 1/*
2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
4
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26/*
27Driver: ni_65xx
28Description: National Instruments 65xx static dio boards
29Author: Jon Grierson <jd@renko.co.uk>, Frank Mori Hess <fmhess@users.sourceforge.net>
30Status: testing
31Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, PCI-6511,
32 PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, PXI-6514, PCI-6515,
33 PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, PCI-6520, PCI-6521, PXI-6521,
34 PCI-6528, PXI-6528
35Updated: Wed Oct 18 08:59:11 EDT 2006
36
37Based on the PCI-6527 driver by ds.
38The interrupt subdevice (subdevice 3) is probably broken for all boards
39except maybe the 6514.
40
41*/
42
43/*
44 Manuals (available from ftp://ftp.natinst.com/support/manuals)
45
46 370106b.pdf 6514 Register Level Programmer Manual
47
48 */
49
50#define _GNU_SOURCE
51#define DEBUG 1
52#define DEBUG_FLAGS
53#include "../comedidev.h"
54
55#include "mite.h"
56
57#define NI6514_DIO_SIZE 4096
58#define NI6514_MITE_SIZE 4096
59
60#define NI_65XX_MAX_NUM_PORTS 12
61static const unsigned ni_65xx_channels_per_port = 8;
62static const unsigned ni_65xx_port_offset = 0x10;
63
64static inline unsigned Port_Data(unsigned port)
65{
66 return 0x40 + port * ni_65xx_port_offset;
67}
68static inline unsigned Port_Select(unsigned port)
69{
70 return 0x41 + port * ni_65xx_port_offset;
71}
72static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
73{
74 return 0x42 + port * ni_65xx_port_offset;
75}
76static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
77{
78 return 0x43 + port * ni_65xx_port_offset;
79}
80static inline unsigned Filter_Enable(unsigned port)
81{
82 return 0x44 + port * ni_65xx_port_offset;
83}
84
85#define ID_Register 0x00
86
87#define Clear_Register 0x01
88#define ClrEdge 0x08
89#define ClrOverflow 0x04
90
91#define Filter_Interval 0x08
92
93#define Change_Status 0x02
94#define MasterInterruptStatus 0x04
95#define Overflow 0x02
96#define EdgeStatus 0x01
97
98#define Master_Interrupt_Control 0x03
99#define FallingEdgeIntEnable 0x10
100#define RisingEdgeIntEnable 0x08
101#define MasterInterruptEnable 0x04
102#define OverflowIntEnable 0x02
103#define EdgeIntEnable 0x01
104
0707bb04 105static int ni_65xx_attach(struct comedi_device * dev, struct comedi_devconfig * it);
71b5f4f1 106static int ni_65xx_detach(struct comedi_device * dev);
139dfbdf 107static struct comedi_driver driver_ni_65xx = {
5211d97c
JG		 108 driver_name:"ni_65xx",
109 module:THIS_MODULE,
110 attach:ni_65xx_attach,
111 detach:ni_65xx_detach,
112};
113
125edf55
BP		 114struct ni_65xx_board {
115
5211d97c
JG		 116 int dev_id;
117 const char *name;
118 unsigned num_dio_ports;
119 unsigned num_di_ports;
120 unsigned num_do_ports;
121 unsigned invert_outputs:1;
125edf55
BP		 122};
123
124static const struct ni_65xx_board ni_65xx_boards[] = {
5211d97c
JG		 125 {
126 dev_id: 0x7085,
127 name: "pci-6509",
128 num_dio_ports:12,
129 invert_outputs:0},
130 {
131 dev_id: 0x1710,
132 name: "pxi-6509",
133 num_dio_ports:12,
134 invert_outputs:0},
135 {
136 dev_id: 0x7124,
137 name: "pci-6510",
138 num_di_ports:4},
139 {
140 dev_id: 0x70c3,
141 name: "pci-6511",
142 num_di_ports:8},
143 {
144 dev_id: 0x70d3,
145 name: "pxi-6511",
146 num_di_ports:8},
147 {
148 dev_id: 0x70cc,
149 name: "pci-6512",
150 num_do_ports:8},
151 {
152 dev_id: 0x70d2,
153 name: "pxi-6512",
154 num_do_ports:8},
155 {
156 dev_id: 0x70c8,
157 name: "pci-6513",
158 num_do_ports:8,
159 invert_outputs:1},
160 {
161 dev_id: 0x70d1,
162 name: "pxi-6513",
163 num_do_ports:8,
164 invert_outputs:1},
165 {
166 dev_id: 0x7088,
167 name: "pci-6514",
168 num_di_ports:4,
169 num_do_ports:4,
170 invert_outputs:1},
171 {
172 dev_id: 0x70CD,
173 name: "pxi-6514",
174 num_di_ports:4,
175 num_do_ports:4,
176 invert_outputs:1},
177 {
178 dev_id: 0x7087,
179 name: "pci-6515",
180 num_di_ports:4,
181 num_do_ports:4,
182 invert_outputs:1},
183 {
184 dev_id: 0x70c9,
185 name: "pxi-6515",
186 num_di_ports:4,
187 num_do_ports:4,
188 invert_outputs:1},
189 {
190 dev_id: 0x7125,
191 name: "pci-6516",
192 num_do_ports:4,
193 invert_outputs:1},
194 {
195 dev_id: 0x7126,
196 name: "pci-6517",
197 num_do_ports:4,
198 invert_outputs:1},
199 {
200 dev_id: 0x7127,
201 name: "pci-6518",
202 num_di_ports:2,
203 num_do_ports:2,
204 invert_outputs:1},
205 {
206 dev_id: 0x7128,
207 name: "pci-6519",
208 num_di_ports:2,
209 num_do_ports:2,
210 invert_outputs:1},
211 {
212 dev_id: 0x71c5,
213 name: "pci-6520",
214 num_di_ports:1,
215 num_do_ports:1,
216 },
217 {
218 dev_id: 0x718b,
219 name: "pci-6521",
220 num_di_ports:1,
221 num_do_ports:1,
222 },
223 {
224 dev_id: 0x718c,
225 name: "pxi-6521",
226 num_di_ports:1,
227 num_do_ports:1,
228 },
229 {
230 dev_id: 0x70a9,
231 name: "pci-6528",
232 num_di_ports:3,
233 num_do_ports:3,
234 },
235 {
236 dev_id: 0x7086,
237 name: "pxi-6528",
238 num_di_ports:3,
239 num_do_ports:3,
240 },
241};
242
243#define n_ni_65xx_boards (sizeof(ni_65xx_boards)/sizeof(ni_65xx_boards[0]))
125edf55 244static inline const struct ni_65xx_board *board(struct comedi_device * dev)
5211d97c
JG		 245{
246 return dev->board_ptr;
247}
248static inline unsigned ni_65xx_port_by_channel(unsigned channel)
249{
250 return channel / ni_65xx_channels_per_port;
251}
125edf55 252static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board * board)
5211d97c
JG		 253{
254 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
255}
256
257static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
258 {PCI_VENDOR_ID_NATINST, 0x1710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NATINST, 0x7085, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
260 {PCI_VENDOR_ID_NATINST, 0x7086, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NATINST, 0x7087, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
262 {PCI_VENDOR_ID_NATINST, 0x7088, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NATINST, 0x70a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
264 {PCI_VENDOR_ID_NATINST, 0x70c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NATINST, 0x70c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
266 {PCI_VENDOR_ID_NATINST, 0x70c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NATINST, 0x70cc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
268 {PCI_VENDOR_ID_NATINST, 0x70CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NATINST, 0x70d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
270 {PCI_VENDOR_ID_NATINST, 0x70d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NATINST, 0x70d3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
272 {PCI_VENDOR_ID_NATINST, 0x7124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NATINST, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
274 {PCI_VENDOR_ID_NATINST, 0x7126, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NATINST, 0x7127, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
276 {PCI_VENDOR_ID_NATINST, 0x7128, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NATINST, 0x718b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
278 {PCI_VENDOR_ID_NATINST, 0x718c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NATINST, 0x71c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
280 {0}
281};
282
283MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
284
47c30a2c 285struct ni_65xx_private {
5211d97c
JG		 286 struct mite_struct *mite;
287 unsigned int filter_interval;
288 unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
289 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
290 unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
47c30a2c
BP		 291};
292
293static inline struct ni_65xx_private *private(struct comedi_device * dev)
5211d97c
JG		 294{
295 return dev->private;
296}
297
6179e3e9 298struct ni_65xx_subdevice_private {
5211d97c 299 unsigned base_port;
6179e3e9
BP		 300};
301
302static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice * subdev)
5211d97c
JG		 303{
304 return subdev->private;
305}
6179e3e9 306static struct ni_65xx_subdevice_private *ni_65xx_alloc_subdevice_private(void)
5211d97c 307{
6179e3e9
BP		 308 struct ni_65xx_subdevice_private *subdev_private =
309 kzalloc(sizeof(struct ni_65xx_subdevice_private), GFP_KERNEL);
5211d97c
JG		 310 if (subdev_private == NULL)
311 return NULL;
312 return subdev_private;
313}
314
71b5f4f1 315static int ni_65xx_find_device(struct comedi_device * dev, int bus, int slot);
5211d97c 316
34c43922 317static int ni_65xx_config_filter(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 318 struct comedi_insn * insn, unsigned int * data)
5211d97c
JG		 319{
320 const unsigned chan = CR_CHAN(insn->chanspec);
321 const unsigned port =
322 sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
323
324 if (data[0] != INSN_CONFIG_FILTER)
325 return -EINVAL;
326 if (data[1]) {
327 static const unsigned filter_resolution_ns = 200;
328 static const unsigned max_filter_interval = 0xfffff;
329 unsigned interval =
330 (data[1] +
331 (filter_resolution_ns / 2)) / filter_resolution_ns;
332 if (interval > max_filter_interval)
333 interval = max_filter_interval;
334 data[1] = interval * filter_resolution_ns;
335
336 if (interval != private(dev)->filter_interval) {
337 writeb(interval,
338 private(dev)->mite->daq_io_addr +
339 Filter_Interval);
340 private(dev)->filter_interval = interval;
341 }
342
343 private(dev)->filter_enable[port] |=
344 1 << (chan % ni_65xx_channels_per_port);
345 } else {
346 private(dev)->filter_enable[port] &=
347 ~(1 << (chan % ni_65xx_channels_per_port));
348 }
349
350 writeb(private(dev)->filter_enable[port],
351 private(dev)->mite->daq_io_addr + Filter_Enable(port));
352
353 return 2;
354}
355
34c43922 356static int ni_65xx_dio_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 357 struct comedi_insn * insn, unsigned int * data)
5211d97c
JG		 358{
359 unsigned port;
360
361 if (insn->n < 1)
362 return -EINVAL;
363 port = sprivate(s)->base_port +
364 ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
365 switch (data[0]) {
366 case INSN_CONFIG_FILTER:
367 return ni_65xx_config_filter(dev, s, insn, data);
368 break;
369 case INSN_CONFIG_DIO_OUTPUT:
370 if (s->type != COMEDI_SUBD_DIO)
371 return -EINVAL;
372 private(dev)->dio_direction[port] = COMEDI_OUTPUT;
373 writeb(0, private(dev)->mite->daq_io_addr + Port_Select(port));
374 return 1;
375 break;
376 case INSN_CONFIG_DIO_INPUT:
377 if (s->type != COMEDI_SUBD_DIO)
378 return -EINVAL;
379 private(dev)->dio_direction[port] = COMEDI_INPUT;
380 writeb(1, private(dev)->mite->daq_io_addr + Port_Select(port));
381 return 1;
382 break;
383 case INSN_CONFIG_DIO_QUERY:
384 if (s->type != COMEDI_SUBD_DIO)
385 return -EINVAL;
386 data[1] = private(dev)->dio_direction[port];
387 return insn->n;
388 break;
389 default:
390 break;
391 }
392 return -EINVAL;
393}
394
34c43922 395static int ni_65xx_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 396 struct comedi_insn * insn, unsigned int * data)
5211d97c
JG		 397{
398 unsigned base_bitfield_channel;
399 const unsigned max_ports_per_bitfield = 5;
400 unsigned read_bits = 0;
401 unsigned j;
402 if (insn->n != 2)
403 return -EINVAL;
404 base_bitfield_channel = CR_CHAN(insn->chanspec);
405 for (j = 0; j < max_ports_per_bitfield; ++j) {
406 const unsigned port =
407 sprivate(s)->base_port +
408 ni_65xx_port_by_channel(base_bitfield_channel) + j;
409 unsigned base_port_channel;
410 unsigned port_mask, port_data, port_read_bits;
411 int bitshift;
412 if (port >= ni_65xx_total_num_ports(board(dev)))
413 break;
414 base_port_channel = port * ni_65xx_channels_per_port;
415 port_mask = data[0];
416 port_data = data[1];
417 bitshift = base_port_channel - base_bitfield_channel;
418 if (bitshift >= 32 || bitshift <= -32)
419 break;
420 if (bitshift > 0) {
421 port_mask >>= bitshift;
422 port_data >>= bitshift;
423 } else {
424 port_mask <<= -bitshift;
425 port_data <<= -bitshift;
426 }
427 port_mask &= 0xff;
428 port_data &= 0xff;
429 if (port_mask) {
430 unsigned bits;
431 private(dev)->output_bits[port] &= ~port_mask;
432 private(dev)->output_bits[port] |=
433 port_data & port_mask;
434 bits = private(dev)->output_bits[port];
435 if (board(dev)->invert_outputs)
436 bits = ~bits;
437 writeb(bits,
438 private(dev)->mite->daq_io_addr +
439 Port_Data(port));
440// rt_printk("wrote 0x%x to port %i\n", bits, port);
441 }
442 port_read_bits =
443 readb(private(dev)->mite->daq_io_addr +
444 Port_Data(port));
445// rt_printk("read 0x%x from port %i\n", port_read_bits, port);
446 if (bitshift > 0) {
447 port_read_bits <<= bitshift;
448 } else {
449 port_read_bits >>= -bitshift;
450 }
451 read_bits |= port_read_bits;
452 }
453 data[1] = read_bits;
454 return insn->n;
455}
456
457static irqreturn_t ni_65xx_interrupt(int irq, void *d PT_REGS_ARG)
458{
71b5f4f1 459 struct comedi_device *dev = d;
34c43922 460 struct comedi_subdevice *s = dev->subdevices + 2;
5211d97c
JG		 461 unsigned int status;
462
463 status = readb(private(dev)->mite->daq_io_addr + Change_Status);
464 if ((status & MasterInterruptStatus) == 0)
465 return IRQ_NONE;
466 if ((status & EdgeStatus) == 0)
467 return IRQ_NONE;
468
469 writeb(ClrEdge | ClrOverflow,
470 private(dev)->mite->daq_io_addr + Clear_Register);
471
472 comedi_buf_put(s->async, 0);
473 s->async->events |= COMEDI_CB_EOS;
474 comedi_event(dev, s);
475 return IRQ_HANDLED;
476}
477
34c43922 478static int ni_65xx_intr_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
ea6d0d4c 479 struct comedi_cmd * cmd)
5211d97c
JG		 480{
481 int err = 0;
482 int tmp;
483
484 /* step 1: make sure trigger sources are trivially valid */
485
486 tmp = cmd->start_src;
487 cmd->start_src &= TRIG_NOW;
488 if (!cmd->start_src || tmp != cmd->start_src)
489 err++;
490
491 tmp = cmd->scan_begin_src;
492 cmd->scan_begin_src &= TRIG_OTHER;
493 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
494 err++;
495
496 tmp = cmd->convert_src;
497 cmd->convert_src &= TRIG_FOLLOW;
498 if (!cmd->convert_src || tmp != cmd->convert_src)
499 err++;
500
501 tmp = cmd->scan_end_src;
502 cmd->scan_end_src &= TRIG_COUNT;
503 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
504 err++;
505
506 tmp = cmd->stop_src;
507 cmd->stop_src &= TRIG_COUNT;
508 if (!cmd->stop_src || tmp != cmd->stop_src)
509 err++;
510
511 if (err)
512 return 1;
513
514 /* step 2: make sure trigger sources are unique and mutually compatible */
515
516 if (err)
517 return 2;
518
519 /* step 3: make sure arguments are trivially compatible */
520
521 if (cmd->start_arg != 0) {
522 cmd->start_arg = 0;
523 err++;
524 }
525 if (cmd->scan_begin_arg != 0) {
526 cmd->scan_begin_arg = 0;
527 err++;
528 }
529 if (cmd->convert_arg != 0) {
530 cmd->convert_arg = 0;
531 err++;
532 }
533
534 if (cmd->scan_end_arg != 1) {
535 cmd->scan_end_arg = 1;
536 err++;
537 }
538 if (cmd->stop_arg != 0) {
539 cmd->stop_arg = 0;
540 err++;
541 }
542
543 if (err)
544 return 3;
545
546 /* step 4: fix up any arguments */
547
548 if (err)
549 return 4;
550
551 return 0;
552}
553
34c43922 554static int ni_65xx_intr_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
5211d97c 555{
ea6d0d4c 556 //struct comedi_cmd *cmd = &s->async->cmd;
5211d97c
JG		 557
558 writeb(ClrEdge | ClrOverflow,
559 private(dev)->mite->daq_io_addr + Clear_Register);
560 writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
561 MasterInterruptEnable | EdgeIntEnable,
562 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
563
564 return 0;
565}
566
34c43922 567static int ni_65xx_intr_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
5211d97c
JG		 568{
569 writeb(0x00,
570 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
571
572 return 0;
573}
574
34c43922 575static int ni_65xx_intr_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 576 struct comedi_insn * insn, unsigned int * data)
5211d97c
JG		 577{
578 if (insn->n < 1)
579 return -EINVAL;
580
581 data[1] = 0;
582 return 2;
583}
584
34c43922 585static int ni_65xx_intr_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
90035c08 586 struct comedi_insn * insn, unsigned int * data)
5211d97c
JG		 587{
588 if (insn->n < 1)
589 return -EINVAL;
590 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
591 return -EINVAL;
592
593 writeb(data[1],
594 private(dev)->mite->daq_io_addr +
595 Rising_Edge_Detection_Enable(0));
596 writeb(data[1] >> 8,
597 private(dev)->mite->daq_io_addr +
598 Rising_Edge_Detection_Enable(0x10));
599 writeb(data[1] >> 16,
600 private(dev)->mite->daq_io_addr +
601 Rising_Edge_Detection_Enable(0x20));
602 writeb(data[1] >> 24,
603 private(dev)->mite->daq_io_addr +
604 Rising_Edge_Detection_Enable(0x30));
605
606 writeb(data[2],
607 private(dev)->mite->daq_io_addr +
608 Falling_Edge_Detection_Enable(0));
609 writeb(data[2] >> 8,
610 private(dev)->mite->daq_io_addr +
611 Falling_Edge_Detection_Enable(0x10));
612 writeb(data[2] >> 16,
613 private(dev)->mite->daq_io_addr +
614 Falling_Edge_Detection_Enable(0x20));
615 writeb(data[2] >> 24,
616 private(dev)->mite->daq_io_addr +
617 Falling_Edge_Detection_Enable(0x30));
618
619 return 2;
620}
621
0707bb04 622static int ni_65xx_attach(struct comedi_device * dev, struct comedi_devconfig * it)
5211d97c 623{
34c43922 624 struct comedi_subdevice *s;
5211d97c
JG		 625 unsigned i;
626 int ret;
627
628 printk("comedi%d: ni_65xx:", dev->minor);
629
47c30a2c 630 if ((ret = alloc_private(dev, sizeof(struct ni_65xx_private))) < 0)
5211d97c
JG		 631 return ret;
632
633 ret = ni_65xx_find_device(dev, it->options[0], it->options[1]);
634 if (ret < 0)
635 return ret;
636
637 ret = mite_setup(private(dev)->mite);
638 if (ret < 0) {
639 printk("error setting up mite\n");
640 return ret;
641 }
642
643 dev->board_name = board(dev)->name;
644 dev->irq = mite_irq(private(dev)->mite);
645 printk(" %s", dev->board_name);
646
647 printk(" ID=0x%02x",
648 readb(private(dev)->mite->daq_io_addr + ID_Register));
649
650 if ((ret = alloc_subdevices(dev, 4)) < 0)
651 return ret;
652
653 s = dev->subdevices + 0;
654 if (board(dev)->num_di_ports) {
655 s->type = COMEDI_SUBD_DI;
656 s->subdev_flags = SDF_READABLE;
657 s->n_chan =
658 board(dev)->num_di_ports * ni_65xx_channels_per_port;
659 s->range_table = &range_digital;
660 s->maxdata = 1;
661 s->insn_config = ni_65xx_dio_insn_config;
662 s->insn_bits = ni_65xx_dio_insn_bits;
663 s->private = ni_65xx_alloc_subdevice_private();
664 if (s->private == NULL)
665 return -ENOMEM;
666 sprivate(s)->base_port = 0;
667 } else {
668 s->type = COMEDI_SUBD_UNUSED;
669 }
670
671 s = dev->subdevices + 1;
672 if (board(dev)->num_do_ports) {
673 s->type = COMEDI_SUBD_DO;
674 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
675 s->n_chan =
676 board(dev)->num_do_ports * ni_65xx_channels_per_port;
677 s->range_table = &range_digital;
678 s->maxdata = 1;
679 s->insn_bits = ni_65xx_dio_insn_bits;
680 s->private = ni_65xx_alloc_subdevice_private();
681 if (s->private == NULL)
682 return -ENOMEM;
683 sprivate(s)->base_port = board(dev)->num_di_ports;
684 } else {
685 s->type = COMEDI_SUBD_UNUSED;
686 }
687
688 s = dev->subdevices + 2;
689 if (board(dev)->num_dio_ports) {
690 s->type = COMEDI_SUBD_DIO;
691 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
692 s->n_chan =
693 board(dev)->num_dio_ports * ni_65xx_channels_per_port;
694 s->range_table = &range_digital;
695 s->maxdata = 1;
696 s->insn_config = ni_65xx_dio_insn_config;
697 s->insn_bits = ni_65xx_dio_insn_bits;
698 s->private = ni_65xx_alloc_subdevice_private();
699 if (s->private == NULL)
700 return -ENOMEM;
701 sprivate(s)->base_port = 0;
702 for (i = 0; i < board(dev)->num_dio_ports; ++i) {
703 // configure all ports for input
704 writeb(0x1,
705 private(dev)->mite->daq_io_addr +
706 Port_Select(i));
707 }
708 } else {
709 s->type = COMEDI_SUBD_UNUSED;
710 }
711
712 s = dev->subdevices + 3;
713 dev->read_subdev = s;
714 s->type = COMEDI_SUBD_DI;
715 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
716 s->n_chan = 1;
717 s->range_table = &range_unknown;
718 s->maxdata = 1;
719 s->do_cmdtest = ni_65xx_intr_cmdtest;
720 s->do_cmd = ni_65xx_intr_cmd;
721 s->cancel = ni_65xx_intr_cancel;
722 s->insn_bits = ni_65xx_intr_insn_bits;
723 s->insn_config = ni_65xx_intr_insn_config;
724
725 for (i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) {
726 writeb(0x00,
727 private(dev)->mite->daq_io_addr + Filter_Enable(i));
728 if (board(dev)->invert_outputs)
729 writeb(0x01,
730 private(dev)->mite->daq_io_addr + Port_Data(i));
731 else
732 writeb(0x00,
733 private(dev)->mite->daq_io_addr + Port_Data(i));
734 }
735 writeb(ClrEdge | ClrOverflow,
736 private(dev)->mite->daq_io_addr + Clear_Register);
737 writeb(0x00,
738 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
739
740 /* Set filter interval to 0 (32bit reg) */
741 writeb(0x00000000, private(dev)->mite->daq_io_addr + Filter_Interval);
742
743 ret = comedi_request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
744 "ni_65xx", dev);
745 if (ret < 0) {
746 dev->irq = 0;
747 printk(" irq not available");
748 }
749
750 printk("\n");
751
752 return 0;
753}
754
71b5f4f1 755static int ni_65xx_detach(struct comedi_device * dev)
5211d97c
JG		 756{
757 if (private(dev) && private(dev)->mite
758 && private(dev)->mite->daq_io_addr) {
759 writeb(0x00,
760 private(dev)->mite->daq_io_addr +
761 Master_Interrupt_Control);
762 }
763
764 if (dev->irq) {
765 comedi_free_irq(dev->irq, dev);
766 }
767
768 if (private(dev)) {
769 unsigned i;
770 for (i = 0; i < dev->n_subdevices; ++i) {
771 if (dev->subdevices[i].private) {
772 kfree(dev->subdevices[i].private);
773 dev->subdevices[i].private = NULL;
774 }
775 }
776 if (private(dev)->mite) {
777 mite_unsetup(private(dev)->mite);
778 }
779 }
780 return 0;
781}
782
71b5f4f1 783static int ni_65xx_find_device(struct comedi_device * dev, int bus, int slot)
5211d97c
JG		 784{
785 struct mite_struct *mite;
786 int i;
787
788 for (mite = mite_devices; mite; mite = mite->next) {
789 if (mite->used)
790 continue;
791 if (bus || slot) {
792 if (bus != mite->pcidev->bus->number ||
793 slot != PCI_SLOT(mite->pcidev->devfn))
794 continue;
795 }
796 for (i = 0; i < n_ni_65xx_boards; i++) {
797 if (mite_device_id(mite) == ni_65xx_boards[i].dev_id) {
798 dev->board_ptr = ni_65xx_boards + i;
799 private(dev)->mite = mite;
800 return 0;
801 }
802 }
803 }
804 printk("no device found\n");
805 mite_list_devices();
806 return -EIO;
807}
808
809COMEDI_PCI_INITCLEANUP(driver_ni_65xx, ni_65xx_pci_table);
kernel source for telekom puls (alcatel/mediatek)