[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / mite.h

/*
    module/mite.h
    Hardware driver for NI Mite PCI interface chip

    COMEDI - Linux Control and Measurement Device Interface
    Copyright (C) 1999 David A. Schleef <ds@schleef.org>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/

#ifndef _MITE_H_
#define _MITE_H_

#include <linux/pci.h>
#include "../comedidev.h"

#define PCI_VENDOR_ID_NATINST		0x1093

/*  #define DEBUG_MITE */
#define PCIMIO_COMPAT

#ifdef DEBUG_MITE
#define MDPRINTK(format, args...)	printk(format , ## args)
#else
#define MDPRINTK(format, args...)
#endif

#define MAX_MITE_DMA_CHANNELS 8

struct mite_dma_descriptor {
	u32 count;
	u32 addr;
	u32 next;
	u32 dar;
};

struct mite_dma_descriptor_ring {
	struct device *hw_dev;
	unsigned int n_links;
	struct mite_dma_descriptor *descriptors;
	dma_addr_t descriptors_dma_addr;
};

struct mite_channel {
	struct mite_struct *mite;
	unsigned channel;
	int dir;
	int done;
	struct mite_dma_descriptor_ring *ring;
};

struct mite_struct {
	struct mite_struct *next;
	int used;

	struct pci_dev *pcidev;
	resource_size_t mite_phys_addr;
	void *mite_io_addr;
	resource_size_t daq_phys_addr;
	void *daq_io_addr;

	struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
	short channel_allocated[MAX_MITE_DMA_CHANNELS];
	int num_channels;
	unsigned fifo_size;
	spinlock_t lock;
};

static inline struct mite_dma_descriptor_ring *mite_alloc_ring(struct
	mite_struct *mite)
{
	struct mite_dma_descriptor_ring *ring =
		kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
	if (ring == NULL)
		return ring;
	ring->hw_dev = get_device(&mite->pcidev->dev);
	if (ring->hw_dev == NULL) {
		kfree(ring);
		return NULL;
	}
	ring->n_links = 0;
	ring->descriptors = NULL;
	ring->descriptors_dma_addr = 0;
	return ring;
};

static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
{
	if (ring) {
		if (ring->descriptors) {
			dma_free_coherent(ring->hw_dev,
				ring->n_links *
				sizeof(struct mite_dma_descriptor),
				ring->descriptors, ring->descriptors_dma_addr);
		}
		put_device(ring->hw_dev);
		kfree(ring);
	}
};

extern struct mite_struct *mite_devices;

static inline unsigned int mite_irq(struct mite_struct *mite)
{
	return mite->pcidev->irq;
};
static inline unsigned int mite_device_id(struct mite_struct *mite)
{
	return mite->pcidev->device;
};

void mite_init(void);
void mite_cleanup(void);
int mite_setup(struct mite_struct *mite);
int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
void mite_unsetup(struct mite_struct *mite);
void mite_list_devices(void);
struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
	struct mite_dma_descriptor_ring *ring, unsigned min_channel,
	unsigned max_channel);
static inline struct mite_channel *mite_request_channel(struct mite_struct
	*mite, struct mite_dma_descriptor_ring *ring)
{
	return mite_request_channel_in_range(mite, ring, 0,
		mite->num_channels - 1);
}
void mite_release_channel(struct mite_channel *mite_chan);

unsigned mite_dma_tcr(struct mite_channel *mite_chan);
void mite_dma_arm(struct mite_channel *mite_chan);
void mite_dma_disarm(struct mite_channel *mite_chan);
int mite_sync_input_dma(struct mite_channel *mite_chan, struct comedi_async * async);
int mite_sync_output_dma(struct mite_channel *mite_chan, struct comedi_async * async);
u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
unsigned mite_get_status(struct mite_channel *mite_chan);
int mite_done(struct mite_channel *mite_chan);

#if 0
unsigned long mite_ll_from_kvmem(struct mite_struct *mite, struct comedi_async * async,
	int len);
void mite_setregs(struct mite_struct *mite, unsigned long ll_start, int chan,
	int dir);
#endif

void mite_prep_dma(struct mite_channel *mite_chan,
	unsigned int num_device_bits, unsigned int num_memory_bits);
int mite_buf_change(struct mite_dma_descriptor_ring *ring,
	struct comedi_async *async);

#ifdef DEBUG_MITE
void mite_print_chsr(unsigned int chsr);
void mite_dump_regs(struct mite_channel *mite_chan);
#endif

static inline int CHAN_OFFSET(int channel)
{
	return 0x500 + 0x100 * channel;
};

enum mite_registers {
	/* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
	   written and read back.  The bits 0x1f always read as 1.
	   The rest always read as zero. */
	MITE_UNKNOWN_DMA_BURST_REG = 0x28,
	MITE_IODWBSR = 0xc0,	/* IO Device Window Base Size Register */
	MITE_IODWBSR_1 = 0xc4,	/*  IO Device Window Base Size Register 1 */
	MITE_IODWCR_1 = 0xf4,
	MITE_PCI_CONFIG_OFFSET = 0x300,
	MITE_CSIGR = 0x460	/* chip signature */
};
static inline int MITE_CHOR(int channel)	/*  channel operation */
{
	return CHAN_OFFSET(channel) + 0x0;
};
static inline int MITE_CHCR(int channel)	/*  channel control */
{
	return CHAN_OFFSET(channel) + 0x4;
};
static inline int MITE_TCR(int channel)	/*  transfer count */
{
	return CHAN_OFFSET(channel) + 0x8;
};
static inline int MITE_MCR(int channel)	/*  memory configuration */
{
	return CHAN_OFFSET(channel) + 0xc;
};
static inline int MITE_MAR(int channel)	/*  memory address */
{
	return CHAN_OFFSET(channel) + 0x10;
};
static inline int MITE_DCR(int channel)	/*  device configuration */
{
	return CHAN_OFFSET(channel) + 0x14;
};
static inline int MITE_DAR(int channel)	/*  device address */
{
	return CHAN_OFFSET(channel) + 0x18;
};
static inline int MITE_LKCR(int channel)	/*  link configuration */
{
	return CHAN_OFFSET(channel) + 0x1c;
};
static inline int MITE_LKAR(int channel)	/*  link address */
{
	return CHAN_OFFSET(channel) + 0x20;
};
static inline int MITE_LLKAR(int channel)	/*  see mite section of tnt5002 manual */
{
	return CHAN_OFFSET(channel) + 0x24;
};
static inline int MITE_BAR(int channel)	/*  base address */
{
	return CHAN_OFFSET(channel) + 0x28;
};
static inline int MITE_BCR(int channel)	/*  base count */
{
	return CHAN_OFFSET(channel) + 0x2c;
};
static inline int MITE_SAR(int channel)	/*  ? address */
{
	return CHAN_OFFSET(channel) + 0x30;
};
static inline int MITE_WSCR(int channel)	/*  ? */
{
	return CHAN_OFFSET(channel) + 0x34;
};
static inline int MITE_WSER(int channel)	/*  ? */
{
	return CHAN_OFFSET(channel) + 0x38;
};
static inline int MITE_CHSR(int channel)	/*  channel status */
{
	return CHAN_OFFSET(channel) + 0x3c;
};
static inline int MITE_FCR(int channel)	/*  fifo count */
{
	return CHAN_OFFSET(channel) + 0x40;
};

enum MITE_IODWBSR_bits {
	WENAB = 0x80,		/*  window enable */
};

static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
{
	unsigned order = 0;
	while (size >>= 1)
		++order;
	BUG_ON(order < 1);
	return (order - 1) & 0x1f;
}

enum MITE_UNKNOWN_DMA_BURST_bits {
	UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
};

static inline int mite_csigr_version(u32 csigr_bits)
{
	return csigr_bits & 0xf;
};
static inline int mite_csigr_type(u32 csigr_bits)
{				/*  original mite = 0, minimite = 1 */
	return (csigr_bits >> 4) & 0xf;
};
static inline int mite_csigr_mmode(u32 csigr_bits)
{				/*  mite mode, minimite = 1 */
	return (csigr_bits >> 8) & 0x3;
};
static inline int mite_csigr_imode(u32 csigr_bits)
{				/*  cpu port interface mode, pci = 0x3 */
	return (csigr_bits >> 12) & 0x3;
};
static inline int mite_csigr_dmac(u32 csigr_bits)
{				/*  number of dma channels */
	return (csigr_bits >> 16) & 0xf;
};
static inline int mite_csigr_wpdep(u32 csigr_bits)
{				/*  write post fifo depth */
	unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
	if (wpdep_bits == 0)
		return 0;
	else
		return 1 << (wpdep_bits - 1);
};
static inline int mite_csigr_wins(u32 csigr_bits)
{
	return (csigr_bits >> 24) & 0x1f;
};
static inline int mite_csigr_iowins(u32 csigr_bits)
{				/*  number of io windows */
	return (csigr_bits >> 29) & 0x7;
};

enum MITE_MCR_bits {
	MCRPON = 0,
};

enum MITE_DCR_bits {
	DCR_NORMAL = (1 << 29),
	DCRPON = 0,
};

enum MITE_CHOR_bits {
	CHOR_DMARESET = (1 << 31),
	CHOR_SET_SEND_TC = (1 << 11),
	CHOR_CLR_SEND_TC = (1 << 10),
	CHOR_SET_LPAUSE = (1 << 9),
	CHOR_CLR_LPAUSE = (1 << 8),
	CHOR_CLRDONE = (1 << 7),
	CHOR_CLRRB = (1 << 6),
	CHOR_CLRLC = (1 << 5),
	CHOR_FRESET = (1 << 4),
	CHOR_ABORT = (1 << 3),	/* stop without emptying fifo */
	CHOR_STOP = (1 << 2),	/* stop after emptying fifo */
	CHOR_CONT = (1 << 1),
	CHOR_START = (1 << 0),
	CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
};

enum MITE_CHCR_bits {
	CHCR_SET_DMA_IE = (1 << 31),
	CHCR_CLR_DMA_IE = (1 << 30),
	CHCR_SET_LINKP_IE = (1 << 29),
	CHCR_CLR_LINKP_IE = (1 << 28),
	CHCR_SET_SAR_IE = (1 << 27),
	CHCR_CLR_SAR_IE = (1 << 26),
	CHCR_SET_DONE_IE = (1 << 25),
	CHCR_CLR_DONE_IE = (1 << 24),
	CHCR_SET_MRDY_IE = (1 << 23),
	CHCR_CLR_MRDY_IE = (1 << 22),
	CHCR_SET_DRDY_IE = (1 << 21),
	CHCR_CLR_DRDY_IE = (1 << 20),
	CHCR_SET_LC_IE = (1 << 19),
	CHCR_CLR_LC_IE = (1 << 18),
	CHCR_SET_CONT_RB_IE = (1 << 17),
	CHCR_CLR_CONT_RB_IE = (1 << 16),
	CHCR_FIFODIS = (1 << 15),
	CHCR_FIFO_ON = 0,
	CHCR_BURSTEN = (1 << 14),
	CHCR_NO_BURSTEN = 0,
	CHCR_BYTE_SWAP_DEVICE = (1 << 6),
	CHCR_BYTE_SWAP_MEMORY = (1 << 4),
	CHCR_DIR = (1 << 3),
	CHCR_DEV_TO_MEM = CHCR_DIR,
	CHCR_MEM_TO_DEV = 0,
	CHCR_NORMAL = (0 << 0),
	CHCR_CONTINUE = (1 << 0),
	CHCR_RINGBUFF = (2 << 0),
	CHCR_LINKSHORT = (4 << 0),
	CHCR_LINKLONG = (5 << 0),
	CHCRPON =
		(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
		CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
		CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
};

enum ConfigRegister_bits {
	CR_REQS_MASK = 0x7 << 16,
	CR_ASEQDONT = 0x0 << 10,
	CR_ASEQUP = 0x1 << 10,
	CR_ASEQDOWN = 0x2 << 10,
	CR_ASEQ_MASK = 0x3 << 10,
	CR_PSIZE8 = (1 << 8),
	CR_PSIZE16 = (2 << 8),
	CR_PSIZE32 = (3 << 8),
	CR_PORTCPU = (0 << 6),
	CR_PORTIO = (1 << 6),
	CR_PORTVXI = (2 << 6),
	CR_PORTMXI = (3 << 6),
	CR_AMDEVICE = (1 << 0),
};
static inline int CR_REQS(int source)
{
	return (source & 0x7) << 16;
};
static inline int CR_REQSDRQ(unsigned drq_line)
{
	/* This also works on m-series when
	   using channels (drq_line) 4 or 5. */
	return CR_REQS((drq_line & 0x3) | 0x4);
}
static inline int CR_RL(unsigned int retry_limit)
{
	int value = 0;

	while (retry_limit) {
		retry_limit >>= 1;
		value++;
	}
	if (value > 0x7)
		rt_printk("comedi: bug! retry_limit too large\n");
	return (value & 0x7) << 21;
}

enum CHSR_bits {
	CHSR_INT = (1 << 31),
	CHSR_LPAUSES = (1 << 29),
	CHSR_SARS = (1 << 27),
	CHSR_DONE = (1 << 25),
	CHSR_MRDY = (1 << 23),
	CHSR_DRDY = (1 << 21),
	CHSR_LINKC = (1 << 19),
	CHSR_CONTS_RB = (1 << 17),
	CHSR_ERROR = (1 << 15),
	CHSR_SABORT = (1 << 14),
	CHSR_HABORT = (1 << 13),
	CHSR_STOPS = (1 << 12),
	CHSR_OPERR_mask = (3 << 10),
	CHSR_OPERR_NOERROR = (0 << 10),
	CHSR_OPERR_FIFOERROR = (1 << 10),
	CHSR_OPERR_LINKERROR = (1 << 10),	/* ??? */
	CHSR_XFERR = (1 << 9),
	CHSR_END = (1 << 8),
	CHSR_DRQ1 = (1 << 7),
	CHSR_DRQ0 = (1 << 6),
	CHSR_LxERR_mask = (3 << 4),
	CHSR_LBERR = (1 << 4),
	CHSR_LRERR = (2 << 4),
	CHSR_LOERR = (3 << 4),
	CHSR_MxERR_mask = (3 << 2),
	CHSR_MBERR = (1 << 2),
	CHSR_MRERR = (2 << 2),
	CHSR_MOERR = (3 << 2),
	CHSR_DxERR_mask = (3 << 0),
	CHSR_DBERR = (1 << 0),
	CHSR_DRERR = (2 << 0),
	CHSR_DOERR = (3 << 0),
};

static inline void mite_dma_reset(struct mite_channel *mite_chan)
{
	writel(CHOR_DMARESET | CHOR_FRESET,
		mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
};

#endif
Commit	Line	Data
bede7290 DS	1	/*
	2	module/mite.h
	3	Hardware driver for NI Mite PCI interface chip
	4
	5	COMEDI - Linux Control and Measurement Device Interface
	6	Copyright (C) 1999 David A. Schleef <ds@schleef.org>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21
	22	*/
	23
	24	#ifndef _MITE_H_
	25	#define _MITE_H_
	26
6fd15040	27	#include <linux/pci.h>
bede7290	28	#include "../comedidev.h"
bede7290 DS	29
	30	#define PCI_VENDOR_ID_NATINST 0x1093
	31
b6c77757	32	/* #define DEBUG_MITE */
bede7290 DS	33	#define PCIMIO_COMPAT
	34
	35	#ifdef DEBUG_MITE
6a98d36e	36	#define MDPRINTK(format, args...) printk(format , ## args)
bede7290	37	#else
8086fff8	38	#define MDPRINTK(format, args...)
bede7290 DS	39	#endif
	40
	41	#define MAX_MITE_DMA_CHANNELS 8
	42
	43	struct mite_dma_descriptor {
	44	u32 count;
	45	u32 addr;
	46	u32 next;
	47	u32 dar;
	48	};
	49
	50	struct mite_dma_descriptor_ring {
	51	struct device *hw_dev;
	52	unsigned int n_links;
	53	struct mite_dma_descriptor *descriptors;
	54	dma_addr_t descriptors_dma_addr;
	55	};
	56
	57	struct mite_channel {
	58	struct mite_struct *mite;
	59	unsigned channel;
	60	int dir;
	61	int done;
	62	struct mite_dma_descriptor_ring *ring;
	63	};
	64
	65	struct mite_struct {
	66	struct mite_struct *next;
	67	int used;
	68
	69	struct pci_dev *pcidev;
	70	resource_size_t mite_phys_addr;
	71	void *mite_io_addr;
	72	resource_size_t daq_phys_addr;
	73	void *daq_io_addr;
	74
	75	struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
	76	short channel_allocated[MAX_MITE_DMA_CHANNELS];
	77	int num_channels;
	78	unsigned fifo_size;
	79	spinlock_t lock;
	80	};
	81
	82	static inline struct mite_dma_descriptor_ring *mite_alloc_ring(struct
	83	mite_struct *mite)
	84	{
	85	struct mite_dma_descriptor_ring *ring =
	86	kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
	87	if (ring == NULL)
	88	return ring;
	89	ring->hw_dev = get_device(&mite->pcidev->dev);
	90	if (ring->hw_dev == NULL) {
	91	kfree(ring);
	92	return NULL;
	93	}
	94	ring->n_links = 0;
	95	ring->descriptors = NULL;
	96	ring->descriptors_dma_addr = 0;
	97	return ring;
	98	};
	99
	100	static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
	101	{
	102	if (ring) {
103	if (ring->descriptors) {
104	dma_free_coherent(ring->hw_dev,
105	ring->n_links *
106	sizeof(struct mite_dma_descriptor),
107	ring->descriptors, ring->descriptors_dma_addr);
108	}
109	put_device(ring->hw_dev);
110	kfree(ring);
111	}
112	};
113
114	extern struct mite_struct *mite_devices;
115
116	static inline unsigned int mite_irq(struct mite_struct *mite)
117	{
118	return mite->pcidev->irq;
119	};
120	static inline unsigned int mite_device_id(struct mite_struct *mite)
121	{
122	return mite->pcidev->device;
123	};
124
125	void mite_init(void);
126	void mite_cleanup(void);
127	int mite_setup(struct mite_struct *mite);
128	int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
129	void mite_unsetup(struct mite_struct *mite);
130	void mite_list_devices(void);
131	struct mite_channel mite_request_channel_in_range(struct mite_struct mite,
132	struct mite_dma_descriptor_ring *ring, unsigned min_channel,
133	unsigned max_channel);
134	static inline struct mite_channel *mite_request_channel(struct mite_struct
135	mite, struct mite_dma_descriptor_ring ring)
136	{
137	return mite_request_channel_in_range(mite, ring, 0,
138	mite->num_channels - 1);
139	}
140	void mite_release_channel(struct mite_channel *mite_chan);
141
142	unsigned mite_dma_tcr(struct mite_channel *mite_chan);
143	void mite_dma_arm(struct mite_channel *mite_chan);
144	void mite_dma_disarm(struct mite_channel *mite_chan);
d163679c BP	145	int mite_sync_input_dma(struct mite_channel mite_chan, struct comedi_async async);
d163679c BP	146	int mite_sync_output_dma(struct mite_channel mite_chan, struct comedi_async async);
bede7290 DS	147	u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
	148	u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
	149	u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
	150	u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
	151	u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
	152	unsigned mite_get_status(struct mite_channel *mite_chan);
	153	int mite_done(struct mite_channel *mite_chan);
	154
	155	#if 0
d163679c	156	unsigned long mite_ll_from_kvmem(struct mite_struct mite, struct comedi_async async,
bede7290 DS	157	int len);
	158	void mite_setregs(struct mite_struct *mite, unsigned long ll_start, int chan,
	159	int dir);
	160	#endif
	161
	162	void mite_prep_dma(struct mite_channel *mite_chan,
	163	unsigned int num_device_bits, unsigned int num_memory_bits);
	164	int mite_buf_change(struct mite_dma_descriptor_ring *ring,
d163679c	165	struct comedi_async *async);
bede7290 DS	166
	167	#ifdef DEBUG_MITE
	168	void mite_print_chsr(unsigned int chsr);
	169	void mite_dump_regs(struct mite_channel *mite_chan);
	170	#endif
	171
	172	static inline int CHAN_OFFSET(int channel)
	173	{
	174	return 0x500 + 0x100 * channel;
	175	};
	176
	177	enum mite_registers {
	178	/* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
	179	written and read back. The bits 0x1f always read as 1.
	180	The rest always read as zero. */
	181	MITE_UNKNOWN_DMA_BURST_REG = 0x28,
b6c77757 BP	182	MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
b6c77757 BP	183	MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
bede7290 DS	184	MITE_IODWCR_1 = 0xf4,
bede7290 DS	185	MITE_PCI_CONFIG_OFFSET = 0x300,
b6c77757	186	MITE_CSIGR = 0x460 /* chip signature */
bede7290	187	};
b6c77757	188	static inline int MITE_CHOR(int channel) /* channel operation */
bede7290 DS	189	{
	190	return CHAN_OFFSET(channel) + 0x0;
	191	};
b6c77757	192	static inline int MITE_CHCR(int channel) /* channel control */
bede7290 DS	193	{
	194	return CHAN_OFFSET(channel) + 0x4;
	195	};
b6c77757	196	static inline int MITE_TCR(int channel) /* transfer count */
bede7290 DS	197	{
	198	return CHAN_OFFSET(channel) + 0x8;
	199	};
b6c77757	200	static inline int MITE_MCR(int channel) /* memory configuration */
bede7290 DS	201	{
	202	return CHAN_OFFSET(channel) + 0xc;
	203	};
b6c77757	204	static inline int MITE_MAR(int channel) /* memory address */
bede7290 DS	205	{
	206	return CHAN_OFFSET(channel) + 0x10;
	207	};
b6c77757	208	static inline int MITE_DCR(int channel) /* device configuration */
bede7290 DS	209	{
	210	return CHAN_OFFSET(channel) + 0x14;
	211	};
b6c77757	212	static inline int MITE_DAR(int channel) /* device address */
bede7290 DS	213	{
	214	return CHAN_OFFSET(channel) + 0x18;
	215	};
b6c77757	216	static inline int MITE_LKCR(int channel) /* link configuration */
bede7290 DS	217	{
	218	return CHAN_OFFSET(channel) + 0x1c;
	219	};
b6c77757	220	static inline int MITE_LKAR(int channel) /* link address */
bede7290 DS	221	{
	222	return CHAN_OFFSET(channel) + 0x20;
	223	};
b6c77757	224	static inline int MITE_LLKAR(int channel) /* see mite section of tnt5002 manual */
bede7290 DS	225	{
	226	return CHAN_OFFSET(channel) + 0x24;
	227	};
b6c77757	228	static inline int MITE_BAR(int channel) /* base address */
bede7290 DS	229	{
	230	return CHAN_OFFSET(channel) + 0x28;
	231	};
b6c77757	232	static inline int MITE_BCR(int channel) /* base count */
bede7290 DS	233	{
	234	return CHAN_OFFSET(channel) + 0x2c;
	235	};
b6c77757	236	static inline int MITE_SAR(int channel) /* ? address */
bede7290 DS	237	{
	238	return CHAN_OFFSET(channel) + 0x30;
	239	};
b6c77757	240	static inline int MITE_WSCR(int channel) /* ? */
bede7290 DS	241	{
	242	return CHAN_OFFSET(channel) + 0x34;
	243	};
b6c77757	244	static inline int MITE_WSER(int channel) /* ? */
bede7290 DS	245	{
	246	return CHAN_OFFSET(channel) + 0x38;
	247	};
b6c77757	248	static inline int MITE_CHSR(int channel) /* channel status */
bede7290 DS	249	{
	250	return CHAN_OFFSET(channel) + 0x3c;
	251	};
b6c77757	252	static inline int MITE_FCR(int channel) /* fifo count */
bede7290 DS	253	{
	254	return CHAN_OFFSET(channel) + 0x40;
	255	};
	256
	257	enum MITE_IODWBSR_bits {
b6c77757	258	WENAB = 0x80, /* window enable */
bede7290 DS	259	};
	260
	261	static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
	262	{
	263	unsigned order = 0;
	264	while (size >>= 1)
	265	++order;
	266	BUG_ON(order < 1);
	267	return (order - 1) & 0x1f;
	268	}
	269
	270	enum MITE_UNKNOWN_DMA_BURST_bits {
	271	UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
	272	};
	273
	274	static inline int mite_csigr_version(u32 csigr_bits)
	275	{
	276	return csigr_bits & 0xf;
	277	};
	278	static inline int mite_csigr_type(u32 csigr_bits)
b6c77757	279	{ /* original mite = 0, minimite = 1 */
bede7290 DS	280	return (csigr_bits >> 4) & 0xf;
	281	};
	282	static inline int mite_csigr_mmode(u32 csigr_bits)
b6c77757	283	{ /* mite mode, minimite = 1 */
bede7290 DS	284	return (csigr_bits >> 8) & 0x3;
	285	};
	286	static inline int mite_csigr_imode(u32 csigr_bits)
b6c77757	287	{ /* cpu port interface mode, pci = 0x3 */
bede7290 DS	288	return (csigr_bits >> 12) & 0x3;
	289	};
	290	static inline int mite_csigr_dmac(u32 csigr_bits)
b6c77757	291	{ /* number of dma channels */
bede7290 DS	292	return (csigr_bits >> 16) & 0xf;
	293	};
	294	static inline int mite_csigr_wpdep(u32 csigr_bits)
b6c77757	295	{ /* write post fifo depth */
bede7290 DS	296	unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
	297	if (wpdep_bits == 0)
	298	return 0;
	299	else
	300	return 1 << (wpdep_bits - 1);
	301	};
	302	static inline int mite_csigr_wins(u32 csigr_bits)
	303	{
	304	return (csigr_bits >> 24) & 0x1f;
	305	};
	306	static inline int mite_csigr_iowins(u32 csigr_bits)
b6c77757	307	{ /* number of io windows */
bede7290 DS	308	return (csigr_bits >> 29) & 0x7;
	309	};
	310
	311	enum MITE_MCR_bits {
	312	MCRPON = 0,
	313	};
	314
	315	enum MITE_DCR_bits {
	316	DCR_NORMAL = (1 << 29),
	317	DCRPON = 0,
	318	};
	319
	320	enum MITE_CHOR_bits {
	321	CHOR_DMARESET = (1 << 31),
	322	CHOR_SET_SEND_TC = (1 << 11),
	323	CHOR_CLR_SEND_TC = (1 << 10),
	324	CHOR_SET_LPAUSE = (1 << 9),
	325	CHOR_CLR_LPAUSE = (1 << 8),
	326	CHOR_CLRDONE = (1 << 7),
	327	CHOR_CLRRB = (1 << 6),
	328	CHOR_CLRLC = (1 << 5),
	329	CHOR_FRESET = (1 << 4),
	330	CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
	331	CHOR_STOP = (1 << 2), /* stop after emptying fifo */
	332	CHOR_CONT = (1 << 1),
	333	CHOR_START = (1 << 0),
	334	CHOR_PON = (CHOR_CLR_SEND_TC \| CHOR_CLR_LPAUSE),
	335	};
	336
	337	enum MITE_CHCR_bits {
	338	CHCR_SET_DMA_IE = (1 << 31),
	339	CHCR_CLR_DMA_IE = (1 << 30),
	340	CHCR_SET_LINKP_IE = (1 << 29),
	341	CHCR_CLR_LINKP_IE = (1 << 28),
	342	CHCR_SET_SAR_IE = (1 << 27),
	343	CHCR_CLR_SAR_IE = (1 << 26),
	344	CHCR_SET_DONE_IE = (1 << 25),
	345	CHCR_CLR_DONE_IE = (1 << 24),
	346	CHCR_SET_MRDY_IE = (1 << 23),
	347	CHCR_CLR_MRDY_IE = (1 << 22),
	348	CHCR_SET_DRDY_IE = (1 << 21),
	349	CHCR_CLR_DRDY_IE = (1 << 20),
	350	CHCR_SET_LC_IE = (1 << 19),
	351	CHCR_CLR_LC_IE = (1 << 18),
	352	CHCR_SET_CONT_RB_IE = (1 << 17),
	353	CHCR_CLR_CONT_RB_IE = (1 << 16),
	354	CHCR_FIFODIS = (1 << 15),
	355	CHCR_FIFO_ON = 0,
	356	CHCR_BURSTEN = (1 << 14),
	357	CHCR_NO_BURSTEN = 0,
	358	CHCR_BYTE_SWAP_DEVICE = (1 << 6),
	359	CHCR_BYTE_SWAP_MEMORY = (1 << 4),
	360	CHCR_DIR = (1 << 3),
	361	CHCR_DEV_TO_MEM = CHCR_DIR,
	362	CHCR_MEM_TO_DEV = 0,
	363	CHCR_NORMAL = (0 << 0),
	364	CHCR_CONTINUE = (1 << 0),
	365	CHCR_RINGBUFF = (2 << 0),
	366	CHCR_LINKSHORT = (4 << 0),
	367	CHCR_LINKLONG = (5 << 0),
	368	CHCRPON =
	369	(CHCR_CLR_DMA_IE \| CHCR_CLR_LINKP_IE \| CHCR_CLR_SAR_IE \|
	370	CHCR_CLR_DONE_IE \| CHCR_CLR_MRDY_IE \| CHCR_CLR_DRDY_IE \|
	371	CHCR_CLR_LC_IE \| CHCR_CLR_CONT_RB_IE),
372	};
373
374	enum ConfigRegister_bits {
375	CR_REQS_MASK = 0x7 << 16,
376	CR_ASEQDONT = 0x0 << 10,
377	CR_ASEQUP = 0x1 << 10,
378	CR_ASEQDOWN = 0x2 << 10,
379	CR_ASEQ_MASK = 0x3 << 10,
380	CR_PSIZE8 = (1 << 8),
381	CR_PSIZE16 = (2 << 8),
382	CR_PSIZE32 = (3 << 8),
383	CR_PORTCPU = (0 << 6),
384	CR_PORTIO = (1 << 6),
385	CR_PORTVXI = (2 << 6),
386	CR_PORTMXI = (3 << 6),
387	CR_AMDEVICE = (1 << 0),
388	};
389	static inline int CR_REQS(int source)
390	{
391	return (source & 0x7) << 16;
392	};
393	static inline int CR_REQSDRQ(unsigned drq_line)
394	{
395	/* This also works on m-series when
396	using channels (drq_line) 4 or 5. */
397	return CR_REQS((drq_line & 0x3) \| 0x4);
398	}
399	static inline int CR_RL(unsigned int retry_limit)
400	{
401	int value = 0;
402
403	while (retry_limit) {
404	retry_limit >>= 1;
405	value++;
406	}
407	if (value > 0x7)
408	rt_printk("comedi: bug! retry_limit too large\n");
409	return (value & 0x7) << 21;
410	}
411
412	enum CHSR_bits {
413	CHSR_INT = (1 << 31),
414	CHSR_LPAUSES = (1 << 29),
415	CHSR_SARS = (1 << 27),
416	CHSR_DONE = (1 << 25),
417	CHSR_MRDY = (1 << 23),
418	CHSR_DRDY = (1 << 21),
419	CHSR_LINKC = (1 << 19),
420	CHSR_CONTS_RB = (1 << 17),
421	CHSR_ERROR = (1 << 15),
422	CHSR_SABORT = (1 << 14),
423	CHSR_HABORT = (1 << 13),
424	CHSR_STOPS = (1 << 12),
425	CHSR_OPERR_mask = (3 << 10),
426	CHSR_OPERR_NOERROR = (0 << 10),
427	CHSR_OPERR_FIFOERROR = (1 << 10),
428	CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
429	CHSR_XFERR = (1 << 9),
430	CHSR_END = (1 << 8),
431	CHSR_DRQ1 = (1 << 7),
432	CHSR_DRQ0 = (1 << 6),
433	CHSR_LxERR_mask = (3 << 4),
434	CHSR_LBERR = (1 << 4),
435	CHSR_LRERR = (2 << 4),
436	CHSR_LOERR = (3 << 4),
437	CHSR_MxERR_mask = (3 << 2),
438	CHSR_MBERR = (1 << 2),
439	CHSR_MRERR = (2 << 2),
440	CHSR_MOERR = (3 << 2),
441	CHSR_DxERR_mask = (3 << 0),
442	CHSR_DBERR = (1 << 0),
443	CHSR_DRERR = (2 << 0),
444	CHSR_DOERR = (3 << 0),
445	};
446
447	static inline void mite_dma_reset(struct mite_channel *mite_chan)
448	{
449	writel(CHOR_DMARESET \| CHOR_FRESET,
450	mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
451	};
452
453	#endif