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7ff7e4c2 IA |
1 | /* comedi/drivers/amplc_dio200_pci.c |
2 | ||
3 | Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296. | |
4 | ||
5 | Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> | |
6 | ||
7 | COMEDI - Linux Control and Measurement Device Interface | |
8 | Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | ||
24 | */ | |
25 | /* | |
26 | * Driver: amplc_dio200_pci | |
27 | * Description: Amplicon 200 Series PCI Digital I/O | |
28 | * Author: Ian Abbott <abbotti@mev.co.uk> | |
29 | * Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236, | |
30 | * PCI272, PCIe296 | |
31 | * Updated: Mon, 18 Mar 2013 15:03:50 +0000 | |
32 | * Status: works | |
33 | * | |
34 | * Configuration options: | |
35 | * none | |
36 | * | |
37 | * Manual configuration of PCI(e) cards is not supported; they are configured | |
38 | * automatically. | |
39 | * | |
40 | * SUBDEVICES | |
41 | * | |
42 | * PCI215 PCIe215 PCIe236 | |
43 | * ------------- ------------- ------------- | |
44 | * Subdevices 5 8 8 | |
45 | * 0 PPI-X PPI-X PPI-X | |
46 | * 1 PPI-Y UNUSED UNUSED | |
47 | * 2 CTR-Z1 PPI-Y UNUSED | |
48 | * 3 CTR-Z2 UNUSED UNUSED | |
49 | * 4 INTERRUPT CTR-Z1 CTR-Z1 | |
50 | * 5 CTR-Z2 CTR-Z2 | |
51 | * 6 TIMER TIMER | |
52 | * 7 INTERRUPT INTERRUPT | |
53 | * | |
54 | * | |
55 | * PCI272 PCIe296 | |
56 | * ------------- ------------- | |
57 | * Subdevices 4 8 | |
58 | * 0 PPI-X PPI-X1 | |
59 | * 1 PPI-Y PPI-X2 | |
60 | * 2 PPI-Z PPI-Y1 | |
61 | * 3 INTERRUPT PPI-Y2 | |
62 | * 4 CTR-Z1 | |
63 | * 5 CTR-Z2 | |
64 | * 6 TIMER | |
65 | * 7 INTERRUPT | |
66 | * | |
67 | * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels | |
68 | * are configurable as inputs or outputs in four groups: | |
69 | * | |
70 | * Port A - channels 0 to 7 | |
71 | * Port B - channels 8 to 15 | |
72 | * Port CL - channels 16 to 19 | |
73 | * Port CH - channels 20 to 23 | |
74 | * | |
75 | * Only mode 0 of the 8255 chips is supported. | |
76 | * | |
77 | * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each | |
78 | * channel is configured individually with INSN_CONFIG instructions. The | |
79 | * specific type of configuration instruction is specified in data[0]. | |
80 | * Some configuration instructions expect an additional parameter in | |
81 | * data[1]; others return a value in data[1]. The following configuration | |
82 | * instructions are supported: | |
83 | * | |
84 | * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and | |
85 | * BCD/binary setting specified in data[1]. | |
86 | * | |
87 | * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the | |
88 | * counter channel into data[1]. | |
89 | * | |
90 | * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as | |
91 | * specified in data[1] (this is a hardware-specific value). Not | |
92 | * supported on PC214E. For the other boards, valid clock sources are | |
93 | * 0 to 7 as follows: | |
94 | * | |
95 | * 0. CLK n, the counter channel's dedicated CLK input from the SK1 | |
96 | * connector. (N.B. for other values, the counter channel's CLKn | |
97 | * pin on the SK1 connector is an output!) | |
98 | * 1. Internal 10 MHz clock. | |
99 | * 2. Internal 1 MHz clock. | |
100 | * 3. Internal 100 kHz clock. | |
101 | * 4. Internal 10 kHz clock. | |
102 | * 5. Internal 1 kHz clock. | |
103 | * 6. OUT n-1, the output of counter channel n-1 (see note 1 below). | |
104 | * 7. Ext Clock, the counter chip's dedicated Ext Clock input from | |
105 | * the SK1 connector. This pin is shared by all three counter | |
106 | * channels on the chip. | |
107 | * | |
108 | * For the PCIe boards, clock sources in the range 0 to 31 are allowed | |
109 | * and the following additional clock sources are defined: | |
110 | * | |
111 | * 8. HIGH logic level. | |
112 | * 9. LOW logic level. | |
113 | * 10. "Pattern present" signal. | |
114 | * 11. Internal 20 MHz clock. | |
115 | * | |
116 | * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current | |
117 | * clock source in data[1]. For internal clock sources, data[2] is set | |
118 | * to the period in ns. | |
119 | * | |
120 | * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as | |
121 | * specified in data[2] (this is a hardware-specific value). Not | |
122 | * supported on PC214E. For the other boards, valid gate sources are 0 | |
123 | * to 7 as follows: | |
124 | * | |
125 | * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled. | |
126 | * 1. GND (internal 0V d.c.), i.e. gate permanently disabled. | |
127 | * 2. GAT n, the counter channel's dedicated GAT input from the SK1 | |
128 | * connector. (N.B. for other values, the counter channel's GATn | |
129 | * pin on the SK1 connector is an output!) | |
130 | * 3. /OUT n-2, the inverted output of counter channel n-2 (see note | |
131 | * 2 below). | |
132 | * 4. Reserved. | |
133 | * 5. Reserved. | |
134 | * 6. Reserved. | |
135 | * 7. Reserved. | |
136 | * | |
137 | * For the PCIe boards, gate sources in the range 0 to 31 are allowed; | |
138 | * the following additional clock sources and clock sources 6 and 7 are | |
139 | * (re)defined: | |
140 | * | |
141 | * 6. /GAT n, negated version of the counter channel's dedicated | |
142 | * GAT input (negated version of gate source 2). | |
143 | * 7. OUT n-2, the non-inverted output of counter channel n-2 | |
144 | * (negated version of gate source 3). | |
145 | * 8. "Pattern present" signal, HIGH while pattern present. | |
146 | * 9. "Pattern occurred" latched signal, latches HIGH when pattern | |
147 | * occurs. | |
148 | * 10. "Pattern gone away" latched signal, latches LOW when pattern | |
149 | * goes away after it occurred. | |
150 | * 11. Negated "pattern present" signal, LOW while pattern present | |
151 | * (negated version of gate source 8). | |
152 | * 12. Negated "pattern occurred" latched signal, latches LOW when | |
153 | * pattern occurs (negated version of gate source 9). | |
154 | * 13. Negated "pattern gone away" latched signal, latches LOW when | |
155 | * pattern goes away after it occurred (negated version of gate | |
156 | * source 10). | |
157 | * | |
158 | * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate | |
159 | * source in data[2]. | |
160 | * | |
161 | * Clock and gate interconnection notes: | |
162 | * | |
163 | * 1. Clock source OUT n-1 is the output of the preceding channel on the | |
164 | * same counter subdevice if n > 0, or the output of channel 2 on the | |
165 | * preceding counter subdevice (see note 3) if n = 0. | |
166 | * | |
167 | * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the | |
168 | * same counter subdevice if n = 2, or the inverted output of channel n+1 | |
169 | * on the preceding counter subdevice (see note 3) if n < 2. | |
170 | * | |
171 | * 3. The counter subdevices are connected in a ring, so the highest | |
172 | * counter subdevice precedes the lowest. | |
173 | * | |
174 | * The 'TIMER' subdevice is a free-running 32-bit timer subdevice. | |
175 | * | |
176 | * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The | |
177 | * digital inputs come from the interrupt status register. The number of | |
178 | * channels matches the number of interrupt sources. The PC214E does not | |
179 | * have an interrupt status register; see notes on 'INTERRUPT SOURCES' | |
180 | * below. | |
181 | * | |
182 | * INTERRUPT SOURCES | |
183 | * | |
184 | * PCI215 PCIe215 PCIe236 | |
185 | * ------------- ------------- ------------- | |
186 | * Sources 6 6 6 | |
187 | * 0 PPI-X-C0 PPI-X-C0 PPI-X-C0 | |
188 | * 1 PPI-X-C3 PPI-X-C3 PPI-X-C3 | |
189 | * 2 PPI-Y-C0 PPI-Y-C0 unused | |
190 | * 3 PPI-Y-C3 PPI-Y-C3 unused | |
191 | * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1 | |
192 | * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1 | |
193 | * | |
194 | * PCI272 PCIe296 | |
195 | * ------------- ------------- | |
196 | * Sources 6 6 | |
197 | * 0 PPI-X-C0 PPI-X1-C0 | |
198 | * 1 PPI-X-C3 PPI-X1-C3 | |
199 | * 2 PPI-Y-C0 PPI-Y1-C0 | |
200 | * 3 PPI-Y-C3 PPI-Y1-C3 | |
201 | * 4 PPI-Z-C0 CTR-Z1-OUT1 | |
202 | * 5 PPI-Z-C3 CTR-Z2-OUT1 | |
203 | * | |
204 | * When an interrupt source is enabled in the interrupt source enable | |
205 | * register, a rising edge on the source signal latches the corresponding | |
206 | * bit to 1 in the interrupt status register. | |
207 | * | |
208 | * When the interrupt status register value as a whole (actually, just the | |
209 | * 6 least significant bits) goes from zero to non-zero, the board will | |
210 | * generate an interrupt. The interrupt will remain asserted until the | |
211 | * interrupt status register is cleared to zero. To clear a bit to zero in | |
212 | * the interrupt status register, the corresponding interrupt source must | |
213 | * be disabled in the interrupt source enable register (there is no | |
214 | * separate interrupt clear register). | |
215 | * | |
216 | * COMMANDS | |
217 | * | |
218 | * The driver supports a read streaming acquisition command on the | |
219 | * 'INTERRUPT' subdevice. The channel list selects the interrupt sources | |
220 | * to be enabled. All channels will be sampled together (convert_src == | |
221 | * TRIG_NOW). The scan begins a short time after the hardware interrupt | |
222 | * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT, | |
223 | * scan_begin_arg == 0). The value read from the interrupt status register | |
224 | * is packed into a short value, one bit per requested channel, in the | |
225 | * order they appear in the channel list. | |
226 | */ | |
227 | ||
228 | #include <linux/pci.h> | |
229 | #include <linux/interrupt.h> | |
230 | #include <linux/slab.h> | |
231 | ||
232 | #include "../comedidev.h" | |
233 | ||
234 | #include "amplc_dio200.h" | |
235 | ||
236 | /* PCI IDs */ | |
237 | #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a | |
238 | #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b | |
239 | #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011 | |
240 | #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012 | |
241 | #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014 | |
242 | ||
243 | /* | |
244 | * Board descriptions. | |
245 | */ | |
246 | ||
247 | enum dio200_pci_model { | |
248 | pci215_model, | |
249 | pci272_model, | |
250 | pcie215_model, | |
251 | pcie236_model, | |
252 | pcie296_model | |
253 | }; | |
254 | ||
255 | static const struct dio200_board dio200_pci_boards[] = { | |
698f57f4 | 256 | [pci215_model] = { |
7ff7e4c2 IA |
257 | .name = "pci215", |
258 | .bustype = pci_bustype, | |
259 | .mainbar = 2, | |
260 | .mainsize = DIO200_IO_SIZE, | |
261 | .layout = { | |
262 | .n_subdevs = 5, | |
263 | .sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr}, | |
264 | .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F}, | |
265 | .has_int_sce = true, | |
266 | .has_clk_gat_sce = true, | |
267 | }, | |
268 | }, | |
698f57f4 | 269 | [pci272_model] = { |
7ff7e4c2 IA |
270 | .name = "pci272", |
271 | .bustype = pci_bustype, | |
272 | .mainbar = 2, | |
273 | .mainsize = DIO200_IO_SIZE, | |
274 | .layout = { | |
275 | .n_subdevs = 4, | |
276 | .sdtype = {sd_8255, sd_8255, sd_8255, sd_intr}, | |
277 | .sdinfo = {0x00, 0x08, 0x10, 0x3F}, | |
278 | .has_int_sce = true, | |
279 | }, | |
280 | }, | |
698f57f4 | 281 | [pcie215_model] = { |
7ff7e4c2 IA |
282 | .name = "pcie215", |
283 | .bustype = pci_bustype, | |
284 | .mainbar = 1, | |
285 | .mainshift = 3, | |
286 | .mainsize = DIO200_PCIE_IO_SIZE, | |
287 | .layout = { | |
288 | .n_subdevs = 8, | |
289 | .sdtype = {sd_8255, sd_none, sd_8255, sd_none, | |
290 | sd_8254, sd_8254, sd_timer, sd_intr}, | |
291 | .sdinfo = {0x00, 0x00, 0x08, 0x00, | |
292 | 0x10, 0x14, 0x00, 0x3F}, | |
293 | .has_int_sce = true, | |
294 | .has_clk_gat_sce = true, | |
295 | .has_enhancements = true, | |
296 | }, | |
297 | }, | |
698f57f4 | 298 | [pcie236_model] = { |
7ff7e4c2 IA |
299 | .name = "pcie236", |
300 | .bustype = pci_bustype, | |
301 | .mainbar = 1, | |
302 | .mainshift = 3, | |
303 | .mainsize = DIO200_PCIE_IO_SIZE, | |
304 | .layout = { | |
305 | .n_subdevs = 8, | |
306 | .sdtype = {sd_8255, sd_none, sd_none, sd_none, | |
307 | sd_8254, sd_8254, sd_timer, sd_intr}, | |
308 | .sdinfo = {0x00, 0x00, 0x00, 0x00, | |
309 | 0x10, 0x14, 0x00, 0x3F}, | |
310 | .has_int_sce = true, | |
311 | .has_clk_gat_sce = true, | |
312 | .has_enhancements = true, | |
313 | }, | |
314 | }, | |
698f57f4 | 315 | [pcie296_model] = { |
7ff7e4c2 IA |
316 | .name = "pcie296", |
317 | .bustype = pci_bustype, | |
318 | .mainbar = 1, | |
319 | .mainshift = 3, | |
320 | .mainsize = DIO200_PCIE_IO_SIZE, | |
321 | .layout = { | |
322 | .n_subdevs = 8, | |
323 | .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255, | |
324 | sd_8254, sd_8254, sd_timer, sd_intr}, | |
325 | .sdinfo = {0x00, 0x04, 0x08, 0x0C, | |
326 | 0x10, 0x14, 0x00, 0x3F}, | |
327 | .has_int_sce = true, | |
328 | .has_clk_gat_sce = true, | |
329 | .has_enhancements = true, | |
330 | }, | |
331 | }, | |
332 | }; | |
333 | ||
334 | /* | |
335 | * This function does some special set-up for the PCIe boards | |
336 | * PCIe215, PCIe236, PCIe296. | |
337 | */ | |
338 | static int dio200_pcie_board_setup(struct comedi_device *dev) | |
339 | { | |
340 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
341 | void __iomem *brbase; | |
7ff7e4c2 IA |
342 | |
343 | /* | |
344 | * The board uses Altera Cyclone IV with PCI-Express hard IP. | |
345 | * The FPGA configuration has the PCI-Express Avalon-MM Bridge | |
346 | * Control registers in PCI BAR 0, offset 0, and the length of | |
347 | * these registers is 0x4000. | |
348 | * | |
349 | * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt | |
350 | * Enable" register at offset 0x50 to allow generation of PCIe | |
351 | * interrupts when RXmlrq_i is asserted in the SOPC Builder system. | |
352 | */ | |
c400c1e1 | 353 | if (pci_resource_len(pcidev, 0) < 0x4000) { |
7ff7e4c2 IA |
354 | dev_err(dev->class_dev, "error! bad PCI region!\n"); |
355 | return -EINVAL; | |
356 | } | |
c400c1e1 | 357 | brbase = pci_ioremap_bar(pcidev, 0); |
7ff7e4c2 IA |
358 | if (!brbase) { |
359 | dev_err(dev->class_dev, "error! failed to map registers!\n"); | |
360 | return -ENOMEM; | |
361 | } | |
362 | writel(0x80, brbase + 0x50); | |
363 | iounmap(brbase); | |
364 | /* Enable "enhanced" features of board. */ | |
365 | amplc_dio200_set_enhance(dev, 1); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | static int dio200_pci_auto_attach(struct comedi_device *dev, | |
370 | unsigned long context_model) | |
371 | { | |
372 | struct pci_dev *pci_dev = comedi_to_pci_dev(dev); | |
373 | const struct dio200_board *thisboard = NULL; | |
374 | struct dio200_private *devpriv; | |
7ff7e4c2 IA |
375 | unsigned int bar; |
376 | int ret; | |
377 | ||
378 | if (context_model < ARRAY_SIZE(dio200_pci_boards)) | |
379 | thisboard = &dio200_pci_boards[context_model]; | |
380 | if (!thisboard) | |
381 | return -EINVAL; | |
382 | dev->board_ptr = thisboard; | |
383 | dev->board_name = thisboard->name; | |
384 | ||
385 | dev_info(dev->class_dev, "%s: attach pci %s (%s)\n", | |
386 | dev->driver->driver_name, pci_name(pci_dev), dev->board_name); | |
387 | ||
388 | devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); | |
389 | if (!devpriv) | |
390 | return -ENOMEM; | |
391 | dev->private = devpriv; | |
392 | ||
393 | ret = comedi_pci_enable(dev); | |
394 | if (ret) | |
395 | return ret; | |
396 | ||
397 | bar = thisboard->mainbar; | |
c400c1e1 | 398 | if (pci_resource_len(pci_dev, bar) < thisboard->mainsize) { |
7ff7e4c2 IA |
399 | dev_err(dev->class_dev, "error! PCI region size too small!\n"); |
400 | return -EINVAL; | |
401 | } | |
402 | if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) { | |
c400c1e1 | 403 | devpriv->io.u.membase = pci_ioremap_bar(pci_dev, bar); |
7ff7e4c2 IA |
404 | if (!devpriv->io.u.membase) { |
405 | dev_err(dev->class_dev, | |
406 | "error! cannot remap registers\n"); | |
407 | return -ENOMEM; | |
408 | } | |
409 | devpriv->io.regtype = mmio_regtype; | |
410 | } else { | |
c400c1e1 | 411 | devpriv->io.u.iobase = pci_resource_start(pci_dev, bar); |
7ff7e4c2 IA |
412 | devpriv->io.regtype = io_regtype; |
413 | } | |
414 | switch (context_model) { | |
415 | case pcie215_model: | |
416 | case pcie236_model: | |
417 | case pcie296_model: | |
418 | ret = dio200_pcie_board_setup(dev); | |
419 | if (ret < 0) | |
420 | return ret; | |
421 | break; | |
422 | default: | |
423 | break; | |
424 | } | |
425 | return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED); | |
426 | } | |
427 | ||
428 | static void dio200_pci_detach(struct comedi_device *dev) | |
429 | { | |
430 | const struct dio200_board *thisboard = comedi_board(dev); | |
431 | struct dio200_private *devpriv = dev->private; | |
432 | ||
433 | if (!thisboard || !devpriv) | |
434 | return; | |
435 | amplc_dio200_common_detach(dev); | |
436 | if (devpriv->io.regtype == mmio_regtype) | |
437 | iounmap(devpriv->io.u.membase); | |
438 | comedi_pci_disable(dev); | |
439 | } | |
440 | ||
441 | static struct comedi_driver dio200_pci_comedi_driver = { | |
442 | .driver_name = "amplc_dio200_pci", | |
443 | .module = THIS_MODULE, | |
444 | .auto_attach = dio200_pci_auto_attach, | |
445 | .detach = dio200_pci_detach, | |
446 | }; | |
447 | ||
448 | static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = { | |
449 | { | |
450 | PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215), | |
451 | pci215_model | |
452 | }, { | |
453 | PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272), | |
454 | pci272_model | |
455 | }, { | |
456 | PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236), | |
457 | pcie236_model | |
458 | }, { | |
459 | PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215), | |
460 | pcie215_model | |
461 | }, { | |
462 | PCI_VDEVICE(AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296), | |
463 | pcie296_model | |
464 | }, | |
465 | {0} | |
466 | }; | |
467 | ||
468 | MODULE_DEVICE_TABLE(pci, dio200_pci_table); | |
469 | ||
470 | static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
471 | { | |
472 | return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver, | |
473 | id->driver_data); | |
474 | } | |
475 | ||
476 | static struct pci_driver dio200_pci_pci_driver = { | |
477 | .name = "amplc_dio200_pci", | |
478 | .id_table = dio200_pci_table, | |
479 | .probe = dio200_pci_probe, | |
480 | .remove = comedi_pci_auto_unconfig, | |
481 | }; | |
482 | module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver); | |
483 | ||
484 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
485 | MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards"); | |
486 | MODULE_LICENSE("GPL"); |