Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
575c5807 | 2 | * MPC8xxx SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
fd8a11e1 | 17 | #include <linux/bug.h> |
35b4b3c0 AV |
18 | #include <linux/errno.h> |
19 | #include <linux/err.h> | |
9effb959 | 20 | #include <linux/io.h> |
ccf06998 KG |
21 | #include <linux/completion.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/spi/spi.h> | |
27 | #include <linux/spi/spi_bitbang.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/fsl_devices.h> | |
35b4b3c0 AV |
30 | #include <linux/of.h> |
31 | #include <linux/of_platform.h> | |
32 | #include <linux/gpio.h> | |
33 | #include <linux/of_gpio.h> | |
34 | #include <linux/of_spi.h> | |
ccf06998 | 35 | |
35b4b3c0 | 36 | #include <sysdev/fsl_soc.h> |
ccf06998 | 37 | #include <asm/irq.h> |
ccf06998 KG |
38 | |
39 | /* SPI Controller registers */ | |
575c5807 | 40 | struct mpc8xxx_spi_reg { |
ccf06998 KG |
41 | u8 res1[0x20]; |
42 | __be32 mode; | |
43 | __be32 event; | |
44 | __be32 mask; | |
45 | __be32 command; | |
46 | __be32 transmit; | |
47 | __be32 receive; | |
48 | }; | |
49 | ||
50 | /* SPI Controller mode register definitions */ | |
2a485d7a | 51 | #define SPMODE_LOOP (1 << 30) |
ccf06998 KG |
52 | #define SPMODE_CI_INACTIVEHIGH (1 << 29) |
53 | #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) | |
54 | #define SPMODE_DIV16 (1 << 27) | |
55 | #define SPMODE_REV (1 << 26) | |
56 | #define SPMODE_MS (1 << 25) | |
57 | #define SPMODE_ENABLE (1 << 24) | |
58 | #define SPMODE_LEN(x) ((x) << 20) | |
59 | #define SPMODE_PM(x) ((x) << 16) | |
f29ba280 | 60 | #define SPMODE_OP (1 << 14) |
c9bfcb31 | 61 | #define SPMODE_CG(x) ((x) << 7) |
ccf06998 KG |
62 | |
63 | /* | |
64 | * Default for SPI Mode: | |
65 | * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk | |
66 | */ | |
67 | #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ | |
68 | SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) | |
69 | ||
70 | /* SPIE register values */ | |
71 | #define SPIE_NE 0x00000200 /* Not empty */ | |
72 | #define SPIE_NF 0x00000100 /* Not full */ | |
73 | ||
74 | /* SPIM register values */ | |
75 | #define SPIM_NE 0x00000200 /* Not empty */ | |
76 | #define SPIM_NF 0x00000100 /* Not full */ | |
77 | ||
78 | /* SPI Controller driver's private data. */ | |
575c5807 AV |
79 | struct mpc8xxx_spi { |
80 | struct mpc8xxx_spi_reg __iomem *base; | |
ccf06998 KG |
81 | |
82 | /* rx & tx bufs from the spi_transfer */ | |
83 | const void *tx; | |
84 | void *rx; | |
85 | ||
86 | /* functions to deal with different sized buffers */ | |
575c5807 AV |
87 | void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); |
88 | u32(*get_tx) (struct mpc8xxx_spi *); | |
ccf06998 KG |
89 | |
90 | unsigned int count; | |
35b4b3c0 | 91 | unsigned int irq; |
ccf06998 KG |
92 | |
93 | unsigned nsecs; /* (clock cycle time)/2 */ | |
94 | ||
e24a4d1e | 95 | u32 spibrg; /* SPIBRG input clock */ |
f29ba280 JT |
96 | u32 rx_shift; /* RX data reg shift when in qe mode */ |
97 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
98 | ||
87ec0e98 AV |
99 | unsigned int flags; |
100 | #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */ | |
f29ba280 | 101 | |
c9bfcb31 JT |
102 | struct workqueue_struct *workqueue; |
103 | struct work_struct work; | |
104 | ||
105 | struct list_head queue; | |
106 | spinlock_t lock; | |
107 | ||
108 | struct completion done; | |
109 | }; | |
110 | ||
575c5807 | 111 | struct spi_mpc8xxx_cs { |
c9bfcb31 | 112 | /* functions to deal with different sized buffers */ |
575c5807 AV |
113 | void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); |
114 | u32 (*get_tx) (struct mpc8xxx_spi *); | |
c9bfcb31 JT |
115 | u32 rx_shift; /* RX data reg shift when in qe mode */ |
116 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
117 | u32 hw_mode; /* Holds HW mode register settings */ | |
ccf06998 KG |
118 | }; |
119 | ||
575c5807 | 120 | static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val) |
ccf06998 KG |
121 | { |
122 | out_be32(reg, val); | |
123 | } | |
124 | ||
575c5807 | 125 | static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg) |
ccf06998 KG |
126 | { |
127 | return in_be32(reg); | |
128 | } | |
129 | ||
130 | #define MPC83XX_SPI_RX_BUF(type) \ | |
34c8a20c | 131 | static \ |
575c5807 | 132 | void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \ |
ccf06998 | 133 | { \ |
575c5807 AV |
134 | type *rx = mpc8xxx_spi->rx; \ |
135 | *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \ | |
136 | mpc8xxx_spi->rx = rx; \ | |
ccf06998 KG |
137 | } |
138 | ||
139 | #define MPC83XX_SPI_TX_BUF(type) \ | |
34c8a20c | 140 | static \ |
575c5807 | 141 | u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \ |
ccf06998 KG |
142 | { \ |
143 | u32 data; \ | |
575c5807 | 144 | const type *tx = mpc8xxx_spi->tx; \ |
4b1badf5 DB |
145 | if (!tx) \ |
146 | return 0; \ | |
575c5807 AV |
147 | data = *tx++ << mpc8xxx_spi->tx_shift; \ |
148 | mpc8xxx_spi->tx = tx; \ | |
ccf06998 KG |
149 | return data; \ |
150 | } | |
151 | ||
152 | MPC83XX_SPI_RX_BUF(u8) | |
153 | MPC83XX_SPI_RX_BUF(u16) | |
154 | MPC83XX_SPI_RX_BUF(u32) | |
155 | MPC83XX_SPI_TX_BUF(u8) | |
156 | MPC83XX_SPI_TX_BUF(u16) | |
157 | MPC83XX_SPI_TX_BUF(u32) | |
158 | ||
a35c1710 AV |
159 | static void mpc8xxx_spi_change_mode(struct spi_device *spi) |
160 | { | |
161 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
162 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
163 | __be32 __iomem *mode = &mspi->base->mode; | |
164 | unsigned long flags; | |
165 | ||
166 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
167 | return; | |
168 | ||
169 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
170 | local_irq_save(flags); | |
171 | ||
172 | /* Turn off SPI unit prior changing mode */ | |
173 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
174 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); | |
175 | ||
176 | local_irq_restore(flags); | |
177 | } | |
178 | ||
575c5807 | 179 | static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 180 | { |
575c5807 | 181 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
364fdbc0 AV |
182 | struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data; |
183 | bool pol = spi->mode & SPI_CS_HIGH; | |
575c5807 | 184 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 185 | |
ccf06998 | 186 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
187 | if (pdata->cs_control) |
188 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
189 | } |
190 | ||
191 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
192 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
193 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
194 | mpc8xxx_spi->get_rx = cs->get_rx; | |
195 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 196 | |
a35c1710 AV |
197 | mpc8xxx_spi_change_mode(spi); |
198 | ||
364fdbc0 AV |
199 | if (pdata->cs_control) |
200 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
201 | } |
202 | } | |
203 | ||
204 | static | |
575c5807 | 205 | int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
ccf06998 | 206 | { |
575c5807 | 207 | struct mpc8xxx_spi *mpc8xxx_spi; |
c9bfcb31 | 208 | u8 bits_per_word, pm; |
ccf06998 | 209 | u32 hz; |
575c5807 | 210 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 211 | |
575c5807 | 212 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 KG |
213 | |
214 | if (t) { | |
215 | bits_per_word = t->bits_per_word; | |
216 | hz = t->speed_hz; | |
217 | } else { | |
218 | bits_per_word = 0; | |
219 | hz = 0; | |
220 | } | |
221 | ||
222 | /* spi_transfer level calls that work per-word */ | |
223 | if (!bits_per_word) | |
224 | bits_per_word = spi->bits_per_word; | |
225 | ||
226 | /* Make sure its a bit width we support [4..16, 32] */ | |
227 | if ((bits_per_word < 4) | |
228 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
229 | return -EINVAL; | |
230 | ||
c9bfcb31 JT |
231 | if (!hz) |
232 | hz = spi->max_speed_hz; | |
233 | ||
234 | cs->rx_shift = 0; | |
235 | cs->tx_shift = 0; | |
ccf06998 | 236 | if (bits_per_word <= 8) { |
575c5807 AV |
237 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
238 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
87ec0e98 | 239 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
c9bfcb31 JT |
240 | cs->rx_shift = 16; |
241 | cs->tx_shift = 24; | |
f29ba280 | 242 | } |
ccf06998 | 243 | } else if (bits_per_word <= 16) { |
575c5807 AV |
244 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
245 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
87ec0e98 | 246 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
c9bfcb31 JT |
247 | cs->rx_shift = 16; |
248 | cs->tx_shift = 16; | |
f29ba280 | 249 | } |
ccf06998 | 250 | } else if (bits_per_word <= 32) { |
575c5807 AV |
251 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
252 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
253 | } else |
254 | return -EINVAL; | |
255 | ||
87ec0e98 AV |
256 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE && |
257 | spi->mode & SPI_LSB_FIRST) { | |
c9bfcb31 | 258 | cs->tx_shift = 0; |
35cc0b97 | 259 | if (bits_per_word <= 8) |
c9bfcb31 | 260 | cs->rx_shift = 8; |
35cc0b97 | 261 | else |
c9bfcb31 | 262 | cs->rx_shift = 0; |
35cc0b97 AV |
263 | } |
264 | ||
575c5807 AV |
265 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
266 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
267 | mpc8xxx_spi->get_rx = cs->get_rx; | |
268 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 KG |
269 | |
270 | if (bits_per_word == 32) | |
271 | bits_per_word = 0; | |
272 | else | |
273 | bits_per_word = bits_per_word - 1; | |
274 | ||
32421daa | 275 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
276 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
277 | | SPMODE_PM(0xF)); | |
278 | ||
279 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
280 | ||
575c5807 | 281 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 282 | cs->hw_mode |= SPMODE_DIV16; |
575c5807 | 283 | pm = mpc8xxx_spi->spibrg / (hz * 64); |
fd8a11e1 AV |
284 | |
285 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
286 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 287 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 288 | if (pm > 16) |
53604dbe | 289 | pm = 16; |
a61f5345 | 290 | } else |
575c5807 | 291 | pm = mpc8xxx_spi->spibrg / (hz * 4); |
a61f5345 CG |
292 | if (pm) |
293 | pm--; | |
294 | ||
295 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 AV |
296 | |
297 | mpc8xxx_spi_change_mode(spi); | |
c9bfcb31 JT |
298 | return 0; |
299 | } | |
ccf06998 | 300 | |
575c5807 | 301 | static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
c9bfcb31 | 302 | { |
575c5807 | 303 | struct mpc8xxx_spi *mpc8xxx_spi; |
c9bfcb31 | 304 | u32 word, len, bits_per_word; |
ccf06998 | 305 | |
575c5807 | 306 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
c9bfcb31 | 307 | |
575c5807 AV |
308 | mpc8xxx_spi->tx = t->tx_buf; |
309 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 JT |
310 | bits_per_word = spi->bits_per_word; |
311 | if (t->bits_per_word) | |
312 | bits_per_word = t->bits_per_word; | |
313 | len = t->len; | |
aa77d96b PK |
314 | if (bits_per_word > 8) { |
315 | /* invalid length? */ | |
316 | if (len & 1) | |
317 | return -EINVAL; | |
c9bfcb31 | 318 | len /= 2; |
aa77d96b PK |
319 | } |
320 | if (bits_per_word > 16) { | |
321 | /* invalid length? */ | |
322 | if (len & 1) | |
323 | return -EINVAL; | |
c9bfcb31 | 324 | len /= 2; |
aa77d96b | 325 | } |
575c5807 | 326 | mpc8xxx_spi->count = len; |
aa77d96b | 327 | |
575c5807 | 328 | INIT_COMPLETION(mpc8xxx_spi->done); |
c9bfcb31 JT |
329 | |
330 | /* enable rx ints */ | |
575c5807 | 331 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE); |
c9bfcb31 JT |
332 | |
333 | /* transmit word */ | |
575c5807 AV |
334 | word = mpc8xxx_spi->get_tx(mpc8xxx_spi); |
335 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word); | |
c9bfcb31 | 336 | |
575c5807 | 337 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
338 | |
339 | /* disable rx ints */ | |
575c5807 | 340 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); |
c9bfcb31 | 341 | |
575c5807 | 342 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
343 | } |
344 | ||
575c5807 | 345 | static void mpc8xxx_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 346 | { |
b9b9af11 AV |
347 | struct spi_device *spi = m->spi; |
348 | struct spi_transfer *t; | |
349 | unsigned int cs_change; | |
350 | const int nsecs = 50; | |
351 | int status; | |
352 | ||
353 | cs_change = 1; | |
354 | status = 0; | |
355 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
356 | if (t->bits_per_word || t->speed_hz) { | |
357 | /* Don't allow changes if CS is active */ | |
358 | status = -EINVAL; | |
359 | ||
360 | if (cs_change) | |
575c5807 | 361 | status = mpc8xxx_spi_setup_transfer(spi, t); |
b9b9af11 | 362 | if (status < 0) |
c9bfcb31 | 363 | break; |
b9b9af11 | 364 | } |
c9bfcb31 | 365 | |
b9b9af11 | 366 | if (cs_change) { |
575c5807 | 367 | mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
368 | ndelay(nsecs); |
369 | } | |
370 | cs_change = t->cs_change; | |
371 | if (t->len) | |
575c5807 | 372 | status = mpc8xxx_spi_bufs(spi, t); |
b9b9af11 AV |
373 | if (status) { |
374 | status = -EMSGSIZE; | |
375 | break; | |
c9bfcb31 | 376 | } |
b9b9af11 | 377 | m->actual_length += t->len; |
c9bfcb31 | 378 | |
b9b9af11 AV |
379 | if (t->delay_usecs) |
380 | udelay(t->delay_usecs); | |
c9bfcb31 | 381 | |
b9b9af11 | 382 | if (cs_change) { |
c9bfcb31 | 383 | ndelay(nsecs); |
575c5807 | 384 | mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 385 | ndelay(nsecs); |
c9bfcb31 | 386 | } |
b9b9af11 AV |
387 | } |
388 | ||
389 | m->status = status; | |
390 | m->complete(m->context); | |
391 | ||
392 | if (status || !cs_change) { | |
393 | ndelay(nsecs); | |
575c5807 | 394 | mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
395 | } |
396 | ||
575c5807 | 397 | mpc8xxx_spi_setup_transfer(spi, NULL); |
b9b9af11 AV |
398 | } |
399 | ||
575c5807 | 400 | static void mpc8xxx_spi_work(struct work_struct *work) |
b9b9af11 | 401 | { |
575c5807 | 402 | struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi, |
b9b9af11 AV |
403 | work); |
404 | ||
575c5807 AV |
405 | spin_lock_irq(&mpc8xxx_spi->lock); |
406 | while (!list_empty(&mpc8xxx_spi->queue)) { | |
407 | struct spi_message *m = container_of(mpc8xxx_spi->queue.next, | |
b9b9af11 AV |
408 | struct spi_message, queue); |
409 | ||
410 | list_del_init(&m->queue); | |
575c5807 | 411 | spin_unlock_irq(&mpc8xxx_spi->lock); |
c9bfcb31 | 412 | |
575c5807 | 413 | mpc8xxx_spi_do_one_msg(m); |
c9bfcb31 | 414 | |
575c5807 | 415 | spin_lock_irq(&mpc8xxx_spi->lock); |
c9bfcb31 | 416 | } |
575c5807 | 417 | spin_unlock_irq(&mpc8xxx_spi->lock); |
ccf06998 KG |
418 | } |
419 | ||
575c5807 | 420 | static int mpc8xxx_spi_setup(struct spi_device *spi) |
ccf06998 | 421 | { |
575c5807 | 422 | struct mpc8xxx_spi *mpc8xxx_spi; |
ccf06998 | 423 | int retval; |
c9bfcb31 | 424 | u32 hw_mode; |
575c5807 | 425 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
426 | |
427 | if (!spi->max_speed_hz) | |
428 | return -EINVAL; | |
429 | ||
c9bfcb31 JT |
430 | if (!cs) { |
431 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
432 | if (!cs) | |
433 | return -ENOMEM; | |
434 | spi->controller_state = cs; | |
435 | } | |
575c5807 | 436 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 437 | |
c9bfcb31 | 438 | hw_mode = cs->hw_mode; /* Save orginal settings */ |
575c5807 | 439 | cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode); |
c9bfcb31 JT |
440 | /* mask out bits we are going to set */ |
441 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
442 | | SPMODE_REV | SPMODE_LOOP); | |
443 | ||
444 | if (spi->mode & SPI_CPHA) | |
445 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
446 | if (spi->mode & SPI_CPOL) | |
447 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
448 | if (!(spi->mode & SPI_LSB_FIRST)) | |
449 | cs->hw_mode |= SPMODE_REV; | |
450 | if (spi->mode & SPI_LOOP) | |
451 | cs->hw_mode |= SPMODE_LOOP; | |
452 | ||
575c5807 | 453 | retval = mpc8xxx_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
454 | if (retval < 0) { |
455 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 456 | return retval; |
c9bfcb31 | 457 | } |
ccf06998 KG |
458 | return 0; |
459 | } | |
460 | ||
575c5807 | 461 | static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data) |
ccf06998 | 462 | { |
575c5807 | 463 | struct mpc8xxx_spi *mpc8xxx_spi = context_data; |
ccf06998 KG |
464 | u32 event; |
465 | irqreturn_t ret = IRQ_NONE; | |
466 | ||
467 | /* Get interrupt events(tx/rx) */ | |
575c5807 | 468 | event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event); |
ccf06998 KG |
469 | |
470 | /* We need handle RX first */ | |
471 | if (event & SPIE_NE) { | |
575c5807 | 472 | u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive); |
ccf06998 | 473 | |
575c5807 AV |
474 | if (mpc8xxx_spi->rx) |
475 | mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi); | |
ccf06998 KG |
476 | |
477 | ret = IRQ_HANDLED; | |
478 | } | |
479 | ||
480 | if ((event & SPIE_NF) == 0) | |
481 | /* spin until TX is done */ | |
482 | while (((event = | |
575c5807 | 483 | mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) & |
ccf06998 | 484 | SPIE_NF) == 0) |
9effb959 | 485 | cpu_relax(); |
ccf06998 | 486 | |
575c5807 AV |
487 | mpc8xxx_spi->count -= 1; |
488 | if (mpc8xxx_spi->count) { | |
489 | u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi); | |
490 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word); | |
ccf06998 | 491 | } else { |
575c5807 | 492 | complete(&mpc8xxx_spi->done); |
ccf06998 KG |
493 | } |
494 | ||
495 | /* Clear the events */ | |
575c5807 | 496 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event); |
ccf06998 KG |
497 | |
498 | return ret; | |
499 | } | |
575c5807 | 500 | static int mpc8xxx_spi_transfer(struct spi_device *spi, |
c9bfcb31 JT |
501 | struct spi_message *m) |
502 | { | |
575c5807 | 503 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
c9bfcb31 JT |
504 | unsigned long flags; |
505 | ||
506 | m->actual_length = 0; | |
507 | m->status = -EINPROGRESS; | |
508 | ||
575c5807 AV |
509 | spin_lock_irqsave(&mpc8xxx_spi->lock, flags); |
510 | list_add_tail(&m->queue, &mpc8xxx_spi->queue); | |
511 | queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work); | |
512 | spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags); | |
c9bfcb31 JT |
513 | |
514 | return 0; | |
515 | } | |
516 | ||
517 | ||
575c5807 | 518 | static void mpc8xxx_spi_cleanup(struct spi_device *spi) |
c9bfcb31 JT |
519 | { |
520 | kfree(spi->controller_state); | |
521 | } | |
ccf06998 | 522 | |
87ec0e98 AV |
523 | static const char *mpc8xxx_spi_strmode(unsigned int flags) |
524 | { | |
525 | if (flags & SPI_QE_CPU_MODE) | |
526 | return "QE CPU"; | |
527 | return "CPU"; | |
528 | } | |
529 | ||
35b4b3c0 | 530 | static struct spi_master * __devinit |
575c5807 | 531 | mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) |
ccf06998 | 532 | { |
35b4b3c0 | 533 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 | 534 | struct spi_master *master; |
575c5807 | 535 | struct mpc8xxx_spi *mpc8xxx_spi; |
ccf06998 KG |
536 | u32 regval; |
537 | int ret = 0; | |
538 | ||
575c5807 | 539 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
540 | if (master == NULL) { |
541 | ret = -ENOMEM; | |
542 | goto err; | |
543 | } | |
544 | ||
35b4b3c0 | 545 | dev_set_drvdata(dev, master); |
ccf06998 | 546 | |
e7db06b5 DB |
547 | /* the spi->mode bits understood by this driver: */ |
548 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
549 | | SPI_LSB_FIRST | SPI_LOOP; | |
550 | ||
575c5807 AV |
551 | master->setup = mpc8xxx_spi_setup; |
552 | master->transfer = mpc8xxx_spi_transfer; | |
553 | master->cleanup = mpc8xxx_spi_cleanup; | |
554 | ||
555 | mpc8xxx_spi = spi_master_get_devdata(master); | |
575c5807 AV |
556 | mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8; |
557 | mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8; | |
87ec0e98 | 558 | mpc8xxx_spi->flags = pdata->flags; |
575c5807 AV |
559 | mpc8xxx_spi->spibrg = pdata->sysclk; |
560 | ||
561 | mpc8xxx_spi->rx_shift = 0; | |
562 | mpc8xxx_spi->tx_shift = 0; | |
87ec0e98 | 563 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
575c5807 AV |
564 | mpc8xxx_spi->rx_shift = 16; |
565 | mpc8xxx_spi->tx_shift = 24; | |
f29ba280 JT |
566 | } |
567 | ||
575c5807 | 568 | init_completion(&mpc8xxx_spi->done); |
ccf06998 | 569 | |
575c5807 AV |
570 | mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1); |
571 | if (mpc8xxx_spi->base == NULL) { | |
ccf06998 KG |
572 | ret = -ENOMEM; |
573 | goto put_master; | |
574 | } | |
575 | ||
575c5807 | 576 | mpc8xxx_spi->irq = irq; |
ccf06998 KG |
577 | |
578 | /* Register for SPI Interrupt */ | |
575c5807 AV |
579 | ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq, |
580 | 0, "mpc8xxx_spi", mpc8xxx_spi); | |
ccf06998 KG |
581 | |
582 | if (ret != 0) | |
583 | goto unmap_io; | |
584 | ||
585 | master->bus_num = pdata->bus_num; | |
586 | master->num_chipselect = pdata->max_chipselect; | |
587 | ||
588 | /* SPI controller initializations */ | |
575c5807 AV |
589 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0); |
590 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); | |
591 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0); | |
592 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff); | |
ccf06998 KG |
593 | |
594 | /* Enable SPI interface */ | |
595 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
87ec0e98 | 596 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
597 | regval |= SPMODE_OP; |
598 | ||
575c5807 AV |
599 | mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval); |
600 | spin_lock_init(&mpc8xxx_spi->lock); | |
601 | init_completion(&mpc8xxx_spi->done); | |
602 | INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work); | |
603 | INIT_LIST_HEAD(&mpc8xxx_spi->queue); | |
ccf06998 | 604 | |
575c5807 | 605 | mpc8xxx_spi->workqueue = create_singlethread_workqueue( |
6c7377ab | 606 | dev_name(master->dev.parent)); |
575c5807 | 607 | if (mpc8xxx_spi->workqueue == NULL) { |
c9bfcb31 | 608 | ret = -EBUSY; |
ccf06998 | 609 | goto free_irq; |
c9bfcb31 JT |
610 | } |
611 | ||
612 | ret = spi_register_master(master); | |
613 | if (ret < 0) | |
614 | goto unreg_master; | |
ccf06998 | 615 | |
87ec0e98 AV |
616 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base, |
617 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); | |
ccf06998 | 618 | |
35b4b3c0 | 619 | return master; |
ccf06998 | 620 | |
c9bfcb31 | 621 | unreg_master: |
575c5807 | 622 | destroy_workqueue(mpc8xxx_spi->workqueue); |
ccf06998 | 623 | free_irq: |
575c5807 | 624 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
ccf06998 | 625 | unmap_io: |
575c5807 | 626 | iounmap(mpc8xxx_spi->base); |
ccf06998 KG |
627 | put_master: |
628 | spi_master_put(master); | |
ccf06998 | 629 | err: |
35b4b3c0 | 630 | return ERR_PTR(ret); |
ccf06998 KG |
631 | } |
632 | ||
575c5807 | 633 | static int __devexit mpc8xxx_spi_remove(struct device *dev) |
ccf06998 | 634 | { |
575c5807 | 635 | struct mpc8xxx_spi *mpc8xxx_spi; |
ccf06998 KG |
636 | struct spi_master *master; |
637 | ||
35b4b3c0 | 638 | master = dev_get_drvdata(dev); |
575c5807 | 639 | mpc8xxx_spi = spi_master_get_devdata(master); |
ccf06998 | 640 | |
575c5807 AV |
641 | flush_workqueue(mpc8xxx_spi->workqueue); |
642 | destroy_workqueue(mpc8xxx_spi->workqueue); | |
c9bfcb31 JT |
643 | spi_unregister_master(master); |
644 | ||
575c5807 AV |
645 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
646 | iounmap(mpc8xxx_spi->base); | |
ccf06998 KG |
647 | |
648 | return 0; | |
649 | } | |
650 | ||
575c5807 | 651 | struct mpc8xxx_spi_probe_info { |
35b4b3c0 AV |
652 | struct fsl_spi_platform_data pdata; |
653 | int *gpios; | |
654 | bool *alow_flags; | |
655 | }; | |
656 | ||
575c5807 | 657 | static struct mpc8xxx_spi_probe_info * |
35b4b3c0 AV |
658 | to_of_pinfo(struct fsl_spi_platform_data *pdata) |
659 | { | |
575c5807 | 660 | return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata); |
35b4b3c0 AV |
661 | } |
662 | ||
575c5807 | 663 | static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 AV |
664 | { |
665 | struct device *dev = spi->dev.parent; | |
575c5807 | 666 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
35b4b3c0 AV |
667 | u16 cs = spi->chip_select; |
668 | int gpio = pinfo->gpios[cs]; | |
669 | bool alow = pinfo->alow_flags[cs]; | |
670 | ||
671 | gpio_set_value(gpio, on ^ alow); | |
672 | } | |
673 | ||
575c5807 | 674 | static int of_mpc8xxx_spi_get_chipselects(struct device *dev) |
35b4b3c0 AV |
675 | { |
676 | struct device_node *np = dev_archdata_get_node(&dev->archdata); | |
677 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 678 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
679 | unsigned int ngpios; |
680 | int i = 0; | |
681 | int ret; | |
682 | ||
683 | ngpios = of_gpio_count(np); | |
684 | if (!ngpios) { | |
685 | /* | |
686 | * SPI w/o chip-select line. One SPI device is still permitted | |
687 | * though. | |
688 | */ | |
689 | pdata->max_chipselect = 1; | |
690 | return 0; | |
691 | } | |
692 | ||
02141546 | 693 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
694 | if (!pinfo->gpios) |
695 | return -ENOMEM; | |
02141546 | 696 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 697 | |
02141546 | 698 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
699 | GFP_KERNEL); |
700 | if (!pinfo->alow_flags) { | |
701 | ret = -ENOMEM; | |
702 | goto err_alloc_flags; | |
703 | } | |
704 | ||
705 | for (; i < ngpios; i++) { | |
706 | int gpio; | |
707 | enum of_gpio_flags flags; | |
708 | ||
709 | gpio = of_get_gpio_flags(np, i, &flags); | |
710 | if (!gpio_is_valid(gpio)) { | |
711 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 712 | ret = gpio; |
35b4b3c0 AV |
713 | goto err_loop; |
714 | } | |
715 | ||
716 | ret = gpio_request(gpio, dev_name(dev)); | |
717 | if (ret) { | |
718 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
719 | goto err_loop; | |
720 | } | |
721 | ||
722 | pinfo->gpios[i] = gpio; | |
723 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
724 | ||
725 | ret = gpio_direction_output(pinfo->gpios[i], | |
726 | pinfo->alow_flags[i]); | |
727 | if (ret) { | |
728 | dev_err(dev, "can't set output direction for gpio " | |
729 | "#%d: %d\n", i, ret); | |
730 | goto err_loop; | |
731 | } | |
732 | } | |
733 | ||
734 | pdata->max_chipselect = ngpios; | |
575c5807 | 735 | pdata->cs_control = mpc8xxx_spi_cs_control; |
35b4b3c0 AV |
736 | |
737 | return 0; | |
738 | ||
739 | err_loop: | |
740 | while (i >= 0) { | |
741 | if (gpio_is_valid(pinfo->gpios[i])) | |
742 | gpio_free(pinfo->gpios[i]); | |
743 | i--; | |
744 | } | |
745 | ||
746 | kfree(pinfo->alow_flags); | |
747 | pinfo->alow_flags = NULL; | |
748 | err_alloc_flags: | |
749 | kfree(pinfo->gpios); | |
750 | pinfo->gpios = NULL; | |
751 | return ret; | |
752 | } | |
753 | ||
575c5807 | 754 | static int of_mpc8xxx_spi_free_chipselects(struct device *dev) |
35b4b3c0 AV |
755 | { |
756 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 757 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
758 | int i; |
759 | ||
760 | if (!pinfo->gpios) | |
761 | return 0; | |
762 | ||
763 | for (i = 0; i < pdata->max_chipselect; i++) { | |
764 | if (gpio_is_valid(pinfo->gpios[i])) | |
765 | gpio_free(pinfo->gpios[i]); | |
766 | } | |
767 | ||
768 | kfree(pinfo->gpios); | |
769 | kfree(pinfo->alow_flags); | |
770 | return 0; | |
771 | } | |
772 | ||
575c5807 | 773 | static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev, |
35b4b3c0 AV |
774 | const struct of_device_id *ofid) |
775 | { | |
776 | struct device *dev = &ofdev->dev; | |
777 | struct device_node *np = ofdev->node; | |
575c5807 | 778 | struct mpc8xxx_spi_probe_info *pinfo; |
35b4b3c0 AV |
779 | struct fsl_spi_platform_data *pdata; |
780 | struct spi_master *master; | |
781 | struct resource mem; | |
782 | struct resource irq; | |
783 | const void *prop; | |
784 | int ret = -ENOMEM; | |
785 | ||
786 | pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL); | |
787 | if (!pinfo) | |
788 | return -ENOMEM; | |
789 | ||
790 | pdata = &pinfo->pdata; | |
791 | dev->platform_data = pdata; | |
792 | ||
793 | /* Allocate bus num dynamically. */ | |
794 | pdata->bus_num = -1; | |
795 | ||
796 | /* SPI controller is either clocked from QE or SoC clock. */ | |
797 | pdata->sysclk = get_brgfreq(); | |
798 | if (pdata->sysclk == -1) { | |
799 | pdata->sysclk = fsl_get_sys_freq(); | |
800 | if (pdata->sysclk == -1) { | |
801 | ret = -ENODEV; | |
802 | goto err_clk; | |
803 | } | |
804 | } | |
805 | ||
806 | prop = of_get_property(np, "mode", NULL); | |
807 | if (prop && !strcmp(prop, "cpu-qe")) | |
87ec0e98 | 808 | pdata->flags = SPI_QE_CPU_MODE; |
35b4b3c0 | 809 | |
575c5807 | 810 | ret = of_mpc8xxx_spi_get_chipselects(dev); |
35b4b3c0 AV |
811 | if (ret) |
812 | goto err; | |
813 | ||
814 | ret = of_address_to_resource(np, 0, &mem); | |
815 | if (ret) | |
816 | goto err; | |
817 | ||
818 | ret = of_irq_to_resource(np, 0, &irq); | |
819 | if (!ret) { | |
820 | ret = -EINVAL; | |
821 | goto err; | |
822 | } | |
823 | ||
575c5807 | 824 | master = mpc8xxx_spi_probe(dev, &mem, irq.start); |
35b4b3c0 AV |
825 | if (IS_ERR(master)) { |
826 | ret = PTR_ERR(master); | |
827 | goto err; | |
828 | } | |
829 | ||
830 | of_register_spi_devices(master, np); | |
831 | ||
832 | return 0; | |
833 | ||
834 | err: | |
575c5807 | 835 | of_mpc8xxx_spi_free_chipselects(dev); |
35b4b3c0 AV |
836 | err_clk: |
837 | kfree(pinfo); | |
838 | return ret; | |
839 | } | |
840 | ||
575c5807 | 841 | static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev) |
35b4b3c0 AV |
842 | { |
843 | int ret; | |
844 | ||
575c5807 | 845 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
846 | if (ret) |
847 | return ret; | |
575c5807 | 848 | of_mpc8xxx_spi_free_chipselects(&ofdev->dev); |
35b4b3c0 AV |
849 | return 0; |
850 | } | |
851 | ||
575c5807 | 852 | static const struct of_device_id of_mpc8xxx_spi_match[] = { |
35b4b3c0 AV |
853 | { .compatible = "fsl,spi" }, |
854 | {}, | |
855 | }; | |
575c5807 | 856 | MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match); |
35b4b3c0 | 857 | |
575c5807 AV |
858 | static struct of_platform_driver of_mpc8xxx_spi_driver = { |
859 | .name = "mpc8xxx_spi", | |
860 | .match_table = of_mpc8xxx_spi_match, | |
861 | .probe = of_mpc8xxx_spi_probe, | |
862 | .remove = __devexit_p(of_mpc8xxx_spi_remove), | |
35b4b3c0 AV |
863 | }; |
864 | ||
865 | #ifdef CONFIG_MPC832x_RDB | |
866 | /* | |
867 | * XXX XXX XXX | |
868 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards | |
869 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
870 | * tree can work with OpenFirmware driver. But for now we support old trees | |
871 | * as well. | |
872 | */ | |
575c5807 | 873 | static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
874 | { |
875 | struct resource *mem; | |
876 | unsigned int irq; | |
877 | struct spi_master *master; | |
878 | ||
879 | if (!pdev->dev.platform_data) | |
880 | return -EINVAL; | |
881 | ||
882 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
883 | if (!mem) | |
884 | return -EINVAL; | |
885 | ||
886 | irq = platform_get_irq(pdev, 0); | |
887 | if (!irq) | |
888 | return -EINVAL; | |
889 | ||
575c5807 | 890 | master = mpc8xxx_spi_probe(&pdev->dev, mem, irq); |
35b4b3c0 AV |
891 | if (IS_ERR(master)) |
892 | return PTR_ERR(master); | |
893 | return 0; | |
894 | } | |
895 | ||
575c5807 | 896 | static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 897 | { |
575c5807 | 898 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
899 | } |
900 | ||
575c5807 AV |
901 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
902 | static struct platform_driver mpc8xxx_spi_driver = { | |
903 | .probe = plat_mpc8xxx_spi_probe, | |
904 | .remove = __exit_p(plat_mpc8xxx_spi_remove), | |
ccf06998 | 905 | .driver = { |
575c5807 | 906 | .name = "mpc8xxx_spi", |
7e38c3c4 | 907 | .owner = THIS_MODULE, |
ccf06998 KG |
908 | }, |
909 | }; | |
910 | ||
35b4b3c0 AV |
911 | static bool legacy_driver_failed; |
912 | ||
913 | static void __init legacy_driver_register(void) | |
914 | { | |
575c5807 | 915 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
916 | } |
917 | ||
918 | static void __exit legacy_driver_unregister(void) | |
919 | { | |
920 | if (legacy_driver_failed) | |
921 | return; | |
575c5807 | 922 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
923 | } |
924 | #else | |
925 | static void __init legacy_driver_register(void) {} | |
926 | static void __exit legacy_driver_unregister(void) {} | |
927 | #endif /* CONFIG_MPC832x_RDB */ | |
928 | ||
575c5807 | 929 | static int __init mpc8xxx_spi_init(void) |
ccf06998 | 930 | { |
35b4b3c0 | 931 | legacy_driver_register(); |
575c5807 | 932 | return of_register_platform_driver(&of_mpc8xxx_spi_driver); |
ccf06998 KG |
933 | } |
934 | ||
575c5807 | 935 | static void __exit mpc8xxx_spi_exit(void) |
ccf06998 | 936 | { |
575c5807 | 937 | of_unregister_platform_driver(&of_mpc8xxx_spi_driver); |
35b4b3c0 | 938 | legacy_driver_unregister(); |
ccf06998 KG |
939 | } |
940 | ||
575c5807 AV |
941 | module_init(mpc8xxx_spi_init); |
942 | module_exit(mpc8xxx_spi_exit); | |
ccf06998 KG |
943 | |
944 | MODULE_AUTHOR("Kumar Gala"); | |
575c5807 | 945 | MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver"); |
ccf06998 | 946 | MODULE_LICENSE("GPL"); |