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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ryusuke...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_mpc8xxx.c
CommitLineData
ccf06998 1/*
575c5807 2 * MPC8xxx SPI controller driver.
ccf06998
KG		 3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
4c1fba44
AV		 8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
ccf06998
KG		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
fd8a11e1 21#include <linux/bug.h>
35b4b3c0
AV		 22#include <linux/errno.h>
23#include <linux/err.h>
9effb959 24#include <linux/io.h>
ccf06998
KG		 25#include <linux/completion.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/irq.h>
29#include <linux/device.h>
30#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h>
32#include <linux/platform_device.h>
33#include <linux/fsl_devices.h>
4c1fba44
AV		 34#include <linux/dma-mapping.h>
35#include <linux/mm.h>
36#include <linux/mutex.h>
35b4b3c0
AV		 37#include <linux/of.h>
38#include <linux/of_platform.h>
39#include <linux/gpio.h>
40#include <linux/of_gpio.h>
5a0e3ad6 41#include <linux/slab.h>
ccf06998 42
35b4b3c0 43#include <sysdev/fsl_soc.h>
4c1fba44
AV		 44#include <asm/cpm.h>
45#include <asm/qe.h>
ccf06998 46#include <asm/irq.h>
ccf06998 47
4c1fba44
AV		 48/* CPM1 and CPM2 are mutually exclusive. */
49#ifdef CONFIG_CPM1
50#include <asm/cpm1.h>
51#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
52#else
53#include <asm/cpm2.h>
54#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
55#endif
56
ccf06998 57/* SPI Controller registers */
575c5807 58struct mpc8xxx_spi_reg {
ccf06998
KG		 59 u8 res1[0x20];
60 __be32 mode;
61 __be32 event;
62 __be32 mask;
63 __be32 command;
64 __be32 transmit;
65 __be32 receive;
66};
67
68/* SPI Controller mode register definitions */
2a485d7a 69#define SPMODE_LOOP (1 << 30)
ccf06998
KG		 70#define SPMODE_CI_INACTIVEHIGH (1 << 29)
71#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
72#define SPMODE_DIV16 (1 << 27)
73#define SPMODE_REV (1 << 26)
74#define SPMODE_MS (1 << 25)
75#define SPMODE_ENABLE (1 << 24)
76#define SPMODE_LEN(x) ((x) << 20)
77#define SPMODE_PM(x) ((x) << 16)
f29ba280 78#define SPMODE_OP (1 << 14)
c9bfcb31 79#define SPMODE_CG(x) ((x) << 7)
ccf06998
KG		 80
81/*
82 * Default for SPI Mode:
83 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
84 */
85#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
86 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
87
88/* SPIE register values */
89#define SPIE_NE 0x00000200 /* Not empty */
90#define SPIE_NF 0x00000100 /* Not full */
91
92/* SPIM register values */
93#define SPIM_NE 0x00000200 /* Not empty */
94#define SPIM_NF 0x00000100 /* Not full */
95
4c1fba44
AV		 96#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
97#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
98
99/* SPCOM register values */
100#define SPCOM_STR (1 << 23) /* Start transmit */
101
102#define SPI_PRAM_SIZE 0x100
103#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
104
ccf06998 105/* SPI Controller driver's private data. */
575c5807 106struct mpc8xxx_spi {
4c1fba44 107 struct device *dev;
575c5807 108 struct mpc8xxx_spi_reg __iomem *base;
ccf06998
KG		 109
110 /* rx & tx bufs from the spi_transfer */
111 const void *tx;
112 void *rx;
113
4c1fba44
AV		 114 int subblock;
115 struct spi_pram __iomem *pram;
116 struct cpm_buf_desc __iomem *tx_bd;
117 struct cpm_buf_desc __iomem *rx_bd;
118
119 struct spi_transfer *xfer_in_progress;
120
121 /* dma addresses for CPM transfers */
122 dma_addr_t tx_dma;
123 dma_addr_t rx_dma;
124 bool map_tx_dma;
125 bool map_rx_dma;
126
127 dma_addr_t dma_dummy_tx;
128 dma_addr_t dma_dummy_rx;
129
ccf06998 130 /* functions to deal with different sized buffers */
575c5807
AV		 131 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
132 u32(*get_tx) (struct mpc8xxx_spi *);
ccf06998
KG		 133
134 unsigned int count;
35b4b3c0 135 unsigned int irq;
ccf06998
KG		 136
137 unsigned nsecs; /* (clock cycle time)/2 */
138
e24a4d1e 139 u32 spibrg; /* SPIBRG input clock */
f29ba280
JT		 140 u32 rx_shift; /* RX data reg shift when in qe mode */
141 u32 tx_shift; /* TX data reg shift when in qe mode */
142
87ec0e98 143 unsigned int flags;
f29ba280 144
c9bfcb31
JT		 145 struct workqueue_struct *workqueue;
146 struct work_struct work;
147
148 struct list_head queue;
149 spinlock_t lock;
150
151 struct completion done;
152};
153
4c1fba44
AV		 154static void *mpc8xxx_dummy_rx;
155static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
156static int mpc8xxx_dummy_rx_refcnt;
157
575c5807 158struct spi_mpc8xxx_cs {
c9bfcb31 159 /* functions to deal with different sized buffers */
575c5807
AV		 160 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
161 u32 (*get_tx) (struct mpc8xxx_spi *);
c9bfcb31
JT		 162 u32 rx_shift; /* RX data reg shift when in qe mode */
163 u32 tx_shift; /* TX data reg shift when in qe mode */
164 u32 hw_mode; /* Holds HW mode register settings */
ccf06998
KG		 165};
166
575c5807 167static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
ccf06998
KG		 168{
169 out_be32(reg, val);
170}
171
575c5807 172static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
ccf06998
KG		 173{
174 return in_be32(reg);
175}
176
177#define MPC83XX_SPI_RX_BUF(type) \
34c8a20c 178static \
575c5807 179void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
ccf06998 180{ \
575c5807
AV		 181 type *rx = mpc8xxx_spi->rx; \
182 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
183 mpc8xxx_spi->rx = rx; \
ccf06998
KG		 184}
185
186#define MPC83XX_SPI_TX_BUF(type) \
34c8a20c 187static \
575c5807 188u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
ccf06998
KG		 189{ \
190 u32 data; \
575c5807 191 const type *tx = mpc8xxx_spi->tx; \
4b1badf5
DB		 192 if (!tx) \
193 return 0; \
575c5807
AV		 194 data = *tx++ << mpc8xxx_spi->tx_shift; \
195 mpc8xxx_spi->tx = tx; \
ccf06998
KG		 196 return data; \
197}
198
199MPC83XX_SPI_RX_BUF(u8)
200MPC83XX_SPI_RX_BUF(u16)
201MPC83XX_SPI_RX_BUF(u32)
202MPC83XX_SPI_TX_BUF(u8)
203MPC83XX_SPI_TX_BUF(u16)
204MPC83XX_SPI_TX_BUF(u32)
205
a35c1710
AV		 206static void mpc8xxx_spi_change_mode(struct spi_device *spi)
207{
208 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
209 struct spi_mpc8xxx_cs *cs = spi->controller_state;
210 __be32 __iomem *mode = &mspi->base->mode;
211 unsigned long flags;
212
213 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
214 return;
215
216 /* Turn off IRQs locally to minimize time that SPI is disabled. */
217 local_irq_save(flags);
218
219 /* Turn off SPI unit prior changing mode */
220 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
a35c1710 221
4c1fba44
AV		 222 /* When in CPM mode, we need to reinit tx and rx. */
223 if (mspi->flags & SPI_CPM_MODE) {
224 if (mspi->flags & SPI_QE) {
225 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
226 QE_CR_PROTOCOL_UNSPECIFIED, 0);
227 } else {
228 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
229 if (mspi->flags & SPI_CPM1) {
230 out_be16(&mspi->pram->rbptr,
231 in_be16(&mspi->pram->rbase));
232 out_be16(&mspi->pram->tbptr,
233 in_be16(&mspi->pram->tbase));
234 }
235 }
236 }
f9218c2a 237 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
a35c1710
AV		 238 local_irq_restore(flags);
239}
240
575c5807 241static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
ccf06998 242{
575c5807 243 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
364fdbc0
AV		 244 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
245 bool pol = spi->mode & SPI_CS_HIGH;
575c5807 246 struct spi_mpc8xxx_cs *cs = spi->controller_state;
ccf06998 247
ccf06998 248 if (value == BITBANG_CS_INACTIVE) {
364fdbc0
AV		 249 if (pdata->cs_control)
250 pdata->cs_control(spi, !pol);
ccf06998
KG		 251 }
252
253 if (value == BITBANG_CS_ACTIVE) {
575c5807
AV		 254 mpc8xxx_spi->rx_shift = cs->rx_shift;
255 mpc8xxx_spi->tx_shift = cs->tx_shift;
256 mpc8xxx_spi->get_rx = cs->get_rx;
257 mpc8xxx_spi->get_tx = cs->get_tx;
c9bfcb31 258
a35c1710
AV		 259 mpc8xxx_spi_change_mode(spi);
260
364fdbc0
AV		 261 if (pdata->cs_control)
262 pdata->cs_control(spi, pol);
ccf06998
KG		 263 }
264}
265
0398fb70
JT		 266static int
267mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
268 struct spi_device *spi,
269 struct mpc8xxx_spi *mpc8xxx_spi,
270 int bits_per_word)
ccf06998 271{
c9bfcb31
JT		 272 cs->rx_shift = 0;
273 cs->tx_shift = 0;
ccf06998 274 if (bits_per_word <= 8) {
575c5807
AV		 275 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
276 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
87ec0e98 277 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
c9bfcb31
JT		 278 cs->rx_shift = 16;
279 cs->tx_shift = 24;
f29ba280 280 }
ccf06998 281 } else if (bits_per_word <= 16) {
575c5807
AV		 282 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
283 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
87ec0e98 284 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
c9bfcb31
JT		 285 cs->rx_shift = 16;
286 cs->tx_shift = 16;
f29ba280 287 }
ccf06998 288 } else if (bits_per_word <= 32) {
575c5807
AV		 289 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
290 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
ccf06998
KG		 291 } else
292 return -EINVAL;
293
87ec0e98 294 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
0398fb70 295 spi->mode & SPI_LSB_FIRST) {
c9bfcb31 296 cs->tx_shift = 0;
35cc0b97 297 if (bits_per_word <= 8)
c9bfcb31 298 cs->rx_shift = 8;
35cc0b97 299 else
c9bfcb31 300 cs->rx_shift = 0;
35cc0b97 301 }
575c5807
AV		 302 mpc8xxx_spi->rx_shift = cs->rx_shift;
303 mpc8xxx_spi->tx_shift = cs->tx_shift;
304 mpc8xxx_spi->get_rx = cs->get_rx;
305 mpc8xxx_spi->get_tx = cs->get_tx;
ccf06998 306
0398fb70
JT		 307 return bits_per_word;
308}
309
310static int
311mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
312 struct spi_device *spi,
313 int bits_per_word)
314{
315 /* QE uses Little Endian for words > 8
316 * so transform all words > 8 into 8 bits
317 * Unfortnatly that doesn't work for LSB so
318 * reject these for now */
319 /* Note: 32 bits word, LSB works iff
320 * tfcr/rfcr is set to CPMFCR_GBL */
321 if (spi->mode & SPI_LSB_FIRST &&
322 bits_per_word > 8)
323 return -EINVAL;
324 if (bits_per_word > 8)
325 return 8; /* pretend its 8 bits */
326 return bits_per_word;
327}
328
329static
330int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
331{
332 struct mpc8xxx_spi *mpc8xxx_spi;
333 int bits_per_word;
334 u8 pm;
335 u32 hz;
336 struct spi_mpc8xxx_cs *cs = spi->controller_state;
337
338 mpc8xxx_spi = spi_master_get_devdata(spi->master);
339
340 if (t) {
341 bits_per_word = t->bits_per_word;
342 hz = t->speed_hz;
343 } else {
344 bits_per_word = 0;
345 hz = 0;
346 }
347
348 /* spi_transfer level calls that work per-word */
349 if (!bits_per_word)
350 bits_per_word = spi->bits_per_word;
351
352 /* Make sure its a bit width we support [4..16, 32] */
353 if ((bits_per_word < 4)
354 || ((bits_per_word > 16) && (bits_per_word != 32)))
355 return -EINVAL;
356
357 if (!hz)
358 hz = spi->max_speed_hz;
359
360 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
361 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
362 mpc8xxx_spi,
363 bits_per_word);
364 else if (mpc8xxx_spi->flags & SPI_QE)
365 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
366 bits_per_word);
367
368 if (bits_per_word < 0)
369 return bits_per_word;
370
ccf06998
KG		 371 if (bits_per_word == 32)
372 bits_per_word = 0;
373 else
374 bits_per_word = bits_per_word - 1;
375
32421daa 376 /* mask out bits we are going to set */
c9bfcb31
JT		 377 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
378 | SPMODE_PM(0xF));
379
380 cs->hw_mode |= SPMODE_LEN(bits_per_word);
381
575c5807 382 if ((mpc8xxx_spi->spibrg / hz) > 64) {
53604dbe 383 cs->hw_mode |= SPMODE_DIV16;
4f4517c4 384 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
fd8a11e1
AV		 385
386 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
387 "Will use %d Hz instead.\n", dev_name(&spi->dev),
575c5807 388 hz, mpc8xxx_spi->spibrg / 1024);
fd8a11e1 389 if (pm > 16)
53604dbe 390 pm = 16;
a61f5345 391 } else
4f4517c4 392 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
a61f5345
CG		 393 if (pm)
394 pm--;
395
396 cs->hw_mode |= SPMODE_PM(pm);
a35c1710
AV		 397
398 mpc8xxx_spi_change_mode(spi);
c9bfcb31
JT		 399 return 0;
400}
ccf06998 401
4c1fba44 402static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
c9bfcb31 403{
4c1fba44
AV		 404 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
405 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
406 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
407 unsigned int xfer_ofs;
ccf06998 408
4c1fba44
AV		 409 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
410
411 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
412 out_be16(&rx_bd->cbd_datlen, 0);
413 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
414
415 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
416 out_be16(&tx_bd->cbd_datlen, xfer_len);
417 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
418 BD_SC_LAST);
419
420 /* start transfer */
421 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
422}
423
424static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
425 struct spi_transfer *t, bool is_dma_mapped)
426{
427 struct device *dev = mspi->dev;
428
429 if (is_dma_mapped) {
430 mspi->map_tx_dma = 0;
431 mspi->map_rx_dma = 0;
432 } else {
433 mspi->map_tx_dma = 1;
434 mspi->map_rx_dma = 1;
435 }
436
437 if (!t->tx_buf) {
438 mspi->tx_dma = mspi->dma_dummy_tx;
439 mspi->map_tx_dma = 0;
440 }
441
442 if (!t->rx_buf) {
443 mspi->rx_dma = mspi->dma_dummy_rx;
444 mspi->map_rx_dma = 0;
445 }
446
447 if (mspi->map_tx_dma) {
448 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
449
450 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
451 DMA_TO_DEVICE);
452 if (dma_mapping_error(dev, mspi->tx_dma)) {
453 dev_err(dev, "unable to map tx dma\n");
454 return -ENOMEM;
455 }
f9218c2a 456 } else if (t->tx_buf) {
4c1fba44
AV		 457 mspi->tx_dma = t->tx_dma;
458 }
459
460 if (mspi->map_rx_dma) {
461 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
462 DMA_FROM_DEVICE);
463 if (dma_mapping_error(dev, mspi->rx_dma)) {
464 dev_err(dev, "unable to map rx dma\n");
465 goto err_rx_dma;
466 }
f9218c2a 467 } else if (t->rx_buf) {
4c1fba44
AV		 468 mspi->rx_dma = t->rx_dma;
469 }
470
471 /* enable rx ints */
472 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
473
474 mspi->xfer_in_progress = t;
475 mspi->count = t->len;
476
477 /* start CPM transfers */
478 mpc8xxx_spi_cpm_bufs_start(mspi);
479
480 return 0;
481
482err_rx_dma:
483 if (mspi->map_tx_dma)
484 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
485 return -ENOMEM;
486}
487
488static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
489{
490 struct device *dev = mspi->dev;
491 struct spi_transfer *t = mspi->xfer_in_progress;
492
493 if (mspi->map_tx_dma)
494 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
338ff298 495 if (mspi->map_rx_dma)
4c1fba44
AV		 496 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
497 mspi->xfer_in_progress = NULL;
498}
499
500static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
501 struct spi_transfer *t, unsigned int len)
502{
503 u32 word;
504
505 mspi->count = len;
506
507 /* enable rx ints */
508 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
509
510 /* transmit word */
511 word = mspi->get_tx(mspi);
512 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
513
514 return 0;
515}
516
517static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
518 bool is_dma_mapped)
519{
520 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
521 unsigned int len = t->len;
522 u8 bits_per_word;
523 int ret;
c9bfcb31 524
c9bfcb31
JT		 525 bits_per_word = spi->bits_per_word;
526 if (t->bits_per_word)
527 bits_per_word = t->bits_per_word;
4c1fba44 528
aa77d96b
PK		 529 if (bits_per_word > 8) {
530 /* invalid length? */
531 if (len & 1)
532 return -EINVAL;
c9bfcb31 533 len /= 2;
aa77d96b
PK		 534 }
535 if (bits_per_word > 16) {
536 /* invalid length? */
537 if (len & 1)
538 return -EINVAL;
c9bfcb31 539 len /= 2;
aa77d96b 540 }
aa77d96b 541
4c1fba44
AV		 542 mpc8xxx_spi->tx = t->tx_buf;
543 mpc8xxx_spi->rx = t->rx_buf;
c9bfcb31 544
4c1fba44 545 INIT_COMPLETION(mpc8xxx_spi->done);
c9bfcb31 546
4c1fba44
AV		 547 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
548 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
549 else
550 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
551 if (ret)
552 return ret;
c9bfcb31 553
575c5807 554 wait_for_completion(&mpc8xxx_spi->done);
c9bfcb31
JT		 555
556 /* disable rx ints */
575c5807 557 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
c9bfcb31 558
4c1fba44
AV		 559 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
560 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
561
575c5807 562 return mpc8xxx_spi->count;
c9bfcb31
JT		 563}
564
575c5807 565static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
c9bfcb31 566{
b9b9af11
AV		 567 struct spi_device *spi = m->spi;
568 struct spi_transfer *t;
569 unsigned int cs_change;
570 const int nsecs = 50;
571 int status;
572
573 cs_change = 1;
574 status = 0;
575 list_for_each_entry(t, &m->transfers, transfer_list) {
576 if (t->bits_per_word || t->speed_hz) {
577 /* Don't allow changes if CS is active */
578 status = -EINVAL;
579
580 if (cs_change)
575c5807 581 status = mpc8xxx_spi_setup_transfer(spi, t);
b9b9af11 582 if (status < 0)
c9bfcb31 583 break;
b9b9af11 584 }
c9bfcb31 585
b9b9af11 586 if (cs_change) {
575c5807 587 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
b9b9af11
AV		 588 ndelay(nsecs);
589 }
590 cs_change = t->cs_change;
591 if (t->len)
4c1fba44 592 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
b9b9af11
AV		 593 if (status) {
594 status = -EMSGSIZE;
595 break;
c9bfcb31 596 }
b9b9af11 597 m->actual_length += t->len;
c9bfcb31 598
b9b9af11
AV		 599 if (t->delay_usecs)
600 udelay(t->delay_usecs);
c9bfcb31 601
b9b9af11 602 if (cs_change) {
c9bfcb31 603 ndelay(nsecs);
575c5807 604 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
b9b9af11 605 ndelay(nsecs);
c9bfcb31 606 }
b9b9af11
AV		 607 }
608
609 m->status = status;
610 m->complete(m->context);
611
612 if (status || !cs_change) {
613 ndelay(nsecs);
575c5807 614 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
b9b9af11
AV		 615 }
616
575c5807 617 mpc8xxx_spi_setup_transfer(spi, NULL);
b9b9af11
AV		 618}
619
575c5807 620static void mpc8xxx_spi_work(struct work_struct *work)
b9b9af11 621{
575c5807 622 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
b9b9af11
AV		 623 work);
624
575c5807
AV		 625 spin_lock_irq(&mpc8xxx_spi->lock);
626 while (!list_empty(&mpc8xxx_spi->queue)) {
627 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
b9b9af11
AV		 628 struct spi_message, queue);
629
630 list_del_init(&m->queue);
575c5807 631 spin_unlock_irq(&mpc8xxx_spi->lock);
c9bfcb31 632
575c5807 633 mpc8xxx_spi_do_one_msg(m);
c9bfcb31 634
575c5807 635 spin_lock_irq(&mpc8xxx_spi->lock);
c9bfcb31 636 }
575c5807 637 spin_unlock_irq(&mpc8xxx_spi->lock);
ccf06998
KG		 638}
639
575c5807 640static int mpc8xxx_spi_setup(struct spi_device *spi)
ccf06998 641{
575c5807 642 struct mpc8xxx_spi *mpc8xxx_spi;
ccf06998 643 int retval;
c9bfcb31 644 u32 hw_mode;
575c5807 645 struct spi_mpc8xxx_cs *cs = spi->controller_state;
ccf06998
KG		 646
647 if (!spi->max_speed_hz)
648 return -EINVAL;
649
c9bfcb31
JT		 650 if (!cs) {
651 cs = kzalloc(sizeof *cs, GFP_KERNEL);
652 if (!cs)
653 return -ENOMEM;
654 spi->controller_state = cs;
655 }
575c5807 656 mpc8xxx_spi = spi_master_get_devdata(spi->master);
ccf06998 657
88393161 658 hw_mode = cs->hw_mode; /* Save original settings */
575c5807 659 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
c9bfcb31
JT		 660 /* mask out bits we are going to set */
661 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
662 | SPMODE_REV | SPMODE_LOOP);
663
664 if (spi->mode & SPI_CPHA)
665 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
666 if (spi->mode & SPI_CPOL)
667 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
668 if (!(spi->mode & SPI_LSB_FIRST))
669 cs->hw_mode |= SPMODE_REV;
670 if (spi->mode & SPI_LOOP)
671 cs->hw_mode |= SPMODE_LOOP;
672
575c5807 673 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
c9bfcb31
JT		 674 if (retval < 0) {
675 cs->hw_mode = hw_mode; /* Restore settings */
ccf06998 676 return retval;
c9bfcb31 677 }
ccf06998
KG		 678 return 0;
679}
680
4c1fba44 681static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
ccf06998 682{
4c1fba44 683 u16 len;
ccf06998 684
4c1fba44
AV		 685 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
686 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
ccf06998 687
4c1fba44
AV		 688 len = in_be16(&mspi->rx_bd->cbd_datlen);
689 if (len > mspi->count) {
690 WARN_ON(1);
691 len = mspi->count;
692 }
ccf06998 693
4c1fba44
AV		 694 /* Clear the events */
695 mpc8xxx_spi_write_reg(&mspi->base->event, events);
ccf06998 696
4c1fba44
AV		 697 mspi->count -= len;
698 if (mspi->count)
699 mpc8xxx_spi_cpm_bufs_start(mspi);
700 else
701 complete(&mspi->done);
702}
703
704static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
705{
706 /* We need handle RX first */
707 if (events & SPIE_NE) {
708 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
709
710 if (mspi->rx)
711 mspi->get_rx(rx_data, mspi);
ccf06998
KG		 712 }
713
4c1fba44 714 if ((events & SPIE_NF) == 0)
ccf06998 715 /* spin until TX is done */
4c1fba44
AV		 716 while (((events =
717 mpc8xxx_spi_read_reg(&mspi->base->event)) &
ccf06998 718 SPIE_NF) == 0)
9effb959 719 cpu_relax();
ccf06998 720
4c1fba44
AV		 721 /* Clear the events */
722 mpc8xxx_spi_write_reg(&mspi->base->event, events);
723
724 mspi->count -= 1;
725 if (mspi->count) {
726 u32 word = mspi->get_tx(mspi);
727
728 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
ccf06998 729 } else {
4c1fba44 730 complete(&mspi->done);
ccf06998 731 }
4c1fba44 732}
ccf06998 733
4c1fba44
AV		 734static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
735{
736 struct mpc8xxx_spi *mspi = context_data;
737 irqreturn_t ret = IRQ_NONE;
738 u32 events;
739
740 /* Get interrupt events(tx/rx) */
741 events = mpc8xxx_spi_read_reg(&mspi->base->event);
742 if (events)
743 ret = IRQ_HANDLED;
744
745 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
746
747 if (mspi->flags & SPI_CPM_MODE)
748 mpc8xxx_spi_cpm_irq(mspi, events);
749 else
750 mpc8xxx_spi_cpu_irq(mspi, events);
ccf06998
KG		 751
752 return ret;
753}
4c1fba44 754
575c5807 755static int mpc8xxx_spi_transfer(struct spi_device *spi,
c9bfcb31
JT		 756 struct spi_message *m)
757{
575c5807 758 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
c9bfcb31
JT		 759 unsigned long flags;
760
761 m->actual_length = 0;
762 m->status = -EINPROGRESS;
763
575c5807
AV		 764 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
765 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
766 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
767 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
c9bfcb31
JT		 768
769 return 0;
770}
771
772
575c5807 773static void mpc8xxx_spi_cleanup(struct spi_device *spi)
c9bfcb31
JT		 774{
775 kfree(spi->controller_state);
776}
ccf06998 777
4c1fba44
AV		 778static void *mpc8xxx_spi_alloc_dummy_rx(void)
779{
780 mutex_lock(&mpc8xxx_dummy_rx_lock);
781
782 if (!mpc8xxx_dummy_rx)
783 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
784 if (mpc8xxx_dummy_rx)
785 mpc8xxx_dummy_rx_refcnt++;
786
787 mutex_unlock(&mpc8xxx_dummy_rx_lock);
788
789 return mpc8xxx_dummy_rx;
790}
791
792static void mpc8xxx_spi_free_dummy_rx(void)
793{
794 mutex_lock(&mpc8xxx_dummy_rx_lock);
795
796 switch (mpc8xxx_dummy_rx_refcnt) {
797 case 0:
798 WARN_ON(1);
799 break;
800 case 1:
801 kfree(mpc8xxx_dummy_rx);
802 mpc8xxx_dummy_rx = NULL;
803 /* fall through */
804 default:
805 mpc8xxx_dummy_rx_refcnt--;
806 break;
807 }
808
809 mutex_unlock(&mpc8xxx_dummy_rx_lock);
810}
811
812static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
813{
814 struct device *dev = mspi->dev;
61c7a080 815 struct device_node *np = dev->of_node;
4c1fba44
AV		 816 const u32 *iprop;
817 int size;
818 unsigned long spi_base_ofs;
819 unsigned long pram_ofs = -ENOMEM;
820
821 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
822 iprop = of_get_property(np, "reg", &size);
823
824 /* QE with a fixed pram location? */
825 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
826 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
827
828 /* QE but with a dynamic pram location? */
829 if (mspi->flags & SPI_QE) {
830 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
831 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
832 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
833 return pram_ofs;
834 }
835
836 /* CPM1 and CPM2 pram must be at a fixed addr. */
837 if (!iprop || size != sizeof(*iprop) * 4)
838 return -ENOMEM;
839
840 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
841 if (IS_ERR_VALUE(spi_base_ofs))
842 return -ENOMEM;
843
844 if (mspi->flags & SPI_CPM2) {
845 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
846 if (!IS_ERR_VALUE(pram_ofs)) {
847 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
848
849 out_be16(spi_base, pram_ofs);
850 }
851 } else {
852 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
853 u16 rpbase = in_be16(&pram->rpbase);
854
855 /* Microcode relocation patch applied? */
856 if (rpbase)
857 pram_ofs = rpbase;
858 else
859 return spi_base_ofs;
860 }
861
862 cpm_muram_free(spi_base_ofs);
863 return pram_ofs;
864}
865
866static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
867{
868 struct device *dev = mspi->dev;
61c7a080 869 struct device_node *np = dev->of_node;
4c1fba44
AV		 870 const u32 *iprop;
871 int size;
872 unsigned long pram_ofs;
873 unsigned long bds_ofs;
874
875 if (!(mspi->flags & SPI_CPM_MODE))
876 return 0;
877
878 if (!mpc8xxx_spi_alloc_dummy_rx())
879 return -ENOMEM;
880
881 if (mspi->flags & SPI_QE) {
882 iprop = of_get_property(np, "cell-index", &size);
883 if (iprop && size == sizeof(*iprop))
884 mspi->subblock = *iprop;
885
886 switch (mspi->subblock) {
887 default:
888 dev_warn(dev, "cell-index unspecified, assuming SPI1");
889 /* fall through */
890 case 0:
891 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
892 break;
893 case 1:
894 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
895 break;
896 }
897 }
898
899 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
900 if (IS_ERR_VALUE(pram_ofs)) {
901 dev_err(dev, "can't allocate spi parameter ram\n");
902 goto err_pram;
903 }
904
905 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
906 sizeof(*mspi->rx_bd), 8);
907 if (IS_ERR_VALUE(bds_ofs)) {
908 dev_err(dev, "can't allocate bds\n");
909 goto err_bds;
910 }
911
912 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
913 DMA_TO_DEVICE);
914 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
915 dev_err(dev, "unable to map dummy tx buffer\n");
916 goto err_dummy_tx;
917 }
918
919 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
920 DMA_FROM_DEVICE);
921 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
922 dev_err(dev, "unable to map dummy rx buffer\n");
923 goto err_dummy_rx;
924 }
925
926 mspi->pram = cpm_muram_addr(pram_ofs);
927
928 mspi->tx_bd = cpm_muram_addr(bds_ofs);
929 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
930
931 /* Initialize parameter ram. */
932 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
933 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
934 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
935 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
936 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
937 out_be32(&mspi->pram->rstate, 0);
938 out_be32(&mspi->pram->rdp, 0);
939 out_be16(&mspi->pram->rbptr, 0);
940 out_be16(&mspi->pram->rbc, 0);
941 out_be32(&mspi->pram->rxtmp, 0);
942 out_be32(&mspi->pram->tstate, 0);
943 out_be32(&mspi->pram->tdp, 0);
944 out_be16(&mspi->pram->tbptr, 0);
945 out_be16(&mspi->pram->tbc, 0);
946 out_be32(&mspi->pram->txtmp, 0);
947
948 return 0;
949
950err_dummy_rx:
951 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
952err_dummy_tx:
953 cpm_muram_free(bds_ofs);
954err_bds:
955 cpm_muram_free(pram_ofs);
956err_pram:
957 mpc8xxx_spi_free_dummy_rx();
958 return -ENOMEM;
959}
960
961static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
962{
963 struct device *dev = mspi->dev;
964
965 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
966 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
967 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
968 cpm_muram_free(cpm_muram_offset(mspi->pram));
969 mpc8xxx_spi_free_dummy_rx();
970}
971
87ec0e98
AV		 972static const char *mpc8xxx_spi_strmode(unsigned int flags)
973{
4c1fba44 974 if (flags & SPI_QE_CPU_MODE) {
87ec0e98 975 return "QE CPU";
4c1fba44
AV		 976 } else if (flags & SPI_CPM_MODE) {
977 if (flags & SPI_QE)
978 return "QE";
979 else if (flags & SPI_CPM2)
980 return "CPM2";
981 else
982 return "CPM1";
983 }
87ec0e98
AV		 984 return "CPU";
985}
986
35b4b3c0 987static struct spi_master * __devinit
575c5807 988mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
ccf06998 989{
35b4b3c0 990 struct fsl_spi_platform_data *pdata = dev->platform_data;
ccf06998 991 struct spi_master *master;
575c5807 992 struct mpc8xxx_spi *mpc8xxx_spi;
ccf06998
KG		 993 u32 regval;
994 int ret = 0;
995
575c5807 996 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
ccf06998
KG		 997 if (master == NULL) {
998 ret = -ENOMEM;
999 goto err;
1000 }
1001
35b4b3c0 1002 dev_set_drvdata(dev, master);
ccf06998 1003
e7db06b5
DB		 1004 /* the spi->mode bits understood by this driver: */
1005 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
1006 | SPI_LSB_FIRST | SPI_LOOP;
1007
575c5807
AV		 1008 master->setup = mpc8xxx_spi_setup;
1009 master->transfer = mpc8xxx_spi_transfer;
1010 master->cleanup = mpc8xxx_spi_cleanup;
12b15e83 1011 master->dev.of_node = dev->of_node;
575c5807
AV		 1012
1013 mpc8xxx_spi = spi_master_get_devdata(master);
4c1fba44 1014 mpc8xxx_spi->dev = dev;
575c5807
AV		 1015 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
1016 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
87ec0e98 1017 mpc8xxx_spi->flags = pdata->flags;
575c5807
AV		 1018 mpc8xxx_spi->spibrg = pdata->sysclk;
1019
4c1fba44
AV		 1020 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1021 if (ret)
1022 goto err_cpm_init;
1023
575c5807
AV		 1024 mpc8xxx_spi->rx_shift = 0;
1025 mpc8xxx_spi->tx_shift = 0;
87ec0e98 1026 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
575c5807
AV		 1027 mpc8xxx_spi->rx_shift = 16;
1028 mpc8xxx_spi->tx_shift = 24;
f29ba280
JT		 1029 }
1030
575c5807 1031 init_completion(&mpc8xxx_spi->done);
ccf06998 1032
82de7651 1033 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
575c5807 1034 if (mpc8xxx_spi->base == NULL) {
ccf06998 1035 ret = -ENOMEM;
4c1fba44 1036 goto err_ioremap;
ccf06998
KG		 1037 }
1038
575c5807 1039 mpc8xxx_spi->irq = irq;
ccf06998
KG		 1040
1041 /* Register for SPI Interrupt */
575c5807
AV		 1042 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1043 0, "mpc8xxx_spi", mpc8xxx_spi);
ccf06998
KG		 1044
1045 if (ret != 0)
1046 goto unmap_io;
1047
1048 master->bus_num = pdata->bus_num;
1049 master->num_chipselect = pdata->max_chipselect;
1050
1051 /* SPI controller initializations */
575c5807
AV		 1052 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1053 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1054 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1055 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
ccf06998
KG		 1056
1057 /* Enable SPI interface */
1058 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
87ec0e98 1059 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
f29ba280
JT		 1060 regval |= SPMODE_OP;
1061
575c5807
AV		 1062 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1063 spin_lock_init(&mpc8xxx_spi->lock);
1064 init_completion(&mpc8xxx_spi->done);
1065 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1066 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
ccf06998 1067
575c5807 1068 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
6c7377ab 1069 dev_name(master->dev.parent));
575c5807 1070 if (mpc8xxx_spi->workqueue == NULL) {
c9bfcb31 1071 ret = -EBUSY;
ccf06998 1072 goto free_irq;
c9bfcb31
JT		 1073 }
1074
1075 ret = spi_register_master(master);
1076 if (ret < 0)
1077 goto unreg_master;
ccf06998 1078
87ec0e98
AV		 1079 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1080 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
ccf06998 1081
35b4b3c0 1082 return master;
ccf06998 1083
c9bfcb31 1084unreg_master:
575c5807 1085 destroy_workqueue(mpc8xxx_spi->workqueue);
ccf06998 1086free_irq:
575c5807 1087 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
ccf06998 1088unmap_io:
575c5807 1089 iounmap(mpc8xxx_spi->base);
4c1fba44
AV		 1090err_ioremap:
1091 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1092err_cpm_init:
ccf06998 1093 spi_master_put(master);
ccf06998 1094err:
35b4b3c0 1095 return ERR_PTR(ret);
ccf06998
KG		 1096}
1097
575c5807 1098static int __devexit mpc8xxx_spi_remove(struct device *dev)
ccf06998 1099{
575c5807 1100 struct mpc8xxx_spi *mpc8xxx_spi;
ccf06998
KG		 1101 struct spi_master *master;
1102
35b4b3c0 1103 master = dev_get_drvdata(dev);
575c5807 1104 mpc8xxx_spi = spi_master_get_devdata(master);
ccf06998 1105
575c5807
AV		 1106 flush_workqueue(mpc8xxx_spi->workqueue);
1107 destroy_workqueue(mpc8xxx_spi->workqueue);
c9bfcb31
JT		 1108 spi_unregister_master(master);
1109
575c5807
AV		 1110 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1111 iounmap(mpc8xxx_spi->base);
4c1fba44 1112 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
ccf06998
KG		 1113
1114 return 0;
1115}
1116
575c5807 1117struct mpc8xxx_spi_probe_info {
35b4b3c0
AV		 1118 struct fsl_spi_platform_data pdata;
1119 int *gpios;
1120 bool *alow_flags;
1121};
1122
575c5807 1123static struct mpc8xxx_spi_probe_info *
35b4b3c0
AV		 1124to_of_pinfo(struct fsl_spi_platform_data *pdata)
1125{
575c5807 1126 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
35b4b3c0
AV		 1127}
1128
575c5807 1129static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
35b4b3c0
AV		 1130{
1131 struct device *dev = spi->dev.parent;
575c5807 1132 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
35b4b3c0
AV		 1133 u16 cs = spi->chip_select;
1134 int gpio = pinfo->gpios[cs];
1135 bool alow = pinfo->alow_flags[cs];
1136
1137 gpio_set_value(gpio, on ^ alow);
1138}
1139
575c5807 1140static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
35b4b3c0 1141{
61c7a080 1142 struct device_node *np = dev->of_node;
35b4b3c0 1143 struct fsl_spi_platform_data *pdata = dev->platform_data;
575c5807 1144 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
35b4b3c0
AV		 1145 unsigned int ngpios;
1146 int i = 0;
1147 int ret;
1148
1149 ngpios = of_gpio_count(np);
1150 if (!ngpios) {
1151 /*
1152 * SPI w/o chip-select line. One SPI device is still permitted
1153 * though.
1154 */
1155 pdata->max_chipselect = 1;
1156 return 0;
1157 }
1158
02141546 1159 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
35b4b3c0
AV		 1160 if (!pinfo->gpios)
1161 return -ENOMEM;
02141546 1162 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
35b4b3c0 1163
02141546 1164 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
35b4b3c0
AV		 1165 GFP_KERNEL);
1166 if (!pinfo->alow_flags) {
1167 ret = -ENOMEM;
1168 goto err_alloc_flags;
1169 }
1170
1171 for (; i < ngpios; i++) {
1172 int gpio;
1173 enum of_gpio_flags flags;
1174
1175 gpio = of_get_gpio_flags(np, i, &flags);
1176 if (!gpio_is_valid(gpio)) {
1177 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
783058fd 1178 ret = gpio;
35b4b3c0
AV		 1179 goto err_loop;
1180 }
1181
1182 ret = gpio_request(gpio, dev_name(dev));
1183 if (ret) {
1184 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1185 goto err_loop;
1186 }
1187
1188 pinfo->gpios[i] = gpio;
1189 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1190
1191 ret = gpio_direction_output(pinfo->gpios[i],
1192 pinfo->alow_flags[i]);
1193 if (ret) {
1194 dev_err(dev, "can't set output direction for gpio "
1195 "#%d: %d\n", i, ret);
1196 goto err_loop;
1197 }
1198 }
1199
1200 pdata->max_chipselect = ngpios;
575c5807 1201 pdata->cs_control = mpc8xxx_spi_cs_control;
35b4b3c0
AV		 1202
1203 return 0;
1204
1205err_loop:
1206 while (i >= 0) {
1207 if (gpio_is_valid(pinfo->gpios[i]))
1208 gpio_free(pinfo->gpios[i]);
1209 i--;
1210 }
1211
1212 kfree(pinfo->alow_flags);
1213 pinfo->alow_flags = NULL;
1214err_alloc_flags:
1215 kfree(pinfo->gpios);
1216 pinfo->gpios = NULL;
1217 return ret;
1218}
1219
575c5807 1220static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
35b4b3c0
AV		 1221{
1222 struct fsl_spi_platform_data *pdata = dev->platform_data;
575c5807 1223 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
35b4b3c0
AV		 1224 int i;
1225
1226 if (!pinfo->gpios)
1227 return 0;
1228
1229 for (i = 0; i < pdata->max_chipselect; i++) {
1230 if (gpio_is_valid(pinfo->gpios[i]))
1231 gpio_free(pinfo->gpios[i]);
1232 }
1233
1234 kfree(pinfo->gpios);
1235 kfree(pinfo->alow_flags);
1236 return 0;
1237}
1238
575c5807 1239static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
35b4b3c0
AV		 1240 const struct of_device_id *ofid)
1241{
1242 struct device *dev = &ofdev->dev;
61c7a080 1243 struct device_node *np = ofdev->dev.of_node;
575c5807 1244 struct mpc8xxx_spi_probe_info *pinfo;
35b4b3c0
AV		 1245 struct fsl_spi_platform_data *pdata;
1246 struct spi_master *master;
1247 struct resource mem;
1248 struct resource irq;
1249 const void *prop;
1250 int ret = -ENOMEM;
1251
1252 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1253 if (!pinfo)
1254 return -ENOMEM;
1255
1256 pdata = &pinfo->pdata;
1257 dev->platform_data = pdata;
1258
1259 /* Allocate bus num dynamically. */
1260 pdata->bus_num = -1;
1261
1262 /* SPI controller is either clocked from QE or SoC clock. */
1263 pdata->sysclk = get_brgfreq();
1264 if (pdata->sysclk == -1) {
1265 pdata->sysclk = fsl_get_sys_freq();
1266 if (pdata->sysclk == -1) {
1267 ret = -ENODEV;
1268 goto err_clk;
1269 }
1270 }
1271
1272 prop = of_get_property(np, "mode", NULL);
1273 if (prop && !strcmp(prop, "cpu-qe"))
87ec0e98 1274 pdata->flags = SPI_QE_CPU_MODE;
4c1fba44
AV		 1275 else if (prop && !strcmp(prop, "qe"))
1276 pdata->flags = SPI_CPM_MODE | SPI_QE;
1277 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1278 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1279 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1280 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
35b4b3c0 1281
575c5807 1282 ret = of_mpc8xxx_spi_get_chipselects(dev);
35b4b3c0
AV		 1283 if (ret)
1284 goto err;
1285
1286 ret = of_address_to_resource(np, 0, &mem);
1287 if (ret)
1288 goto err;
1289
1290 ret = of_irq_to_resource(np, 0, &irq);
1291 if (!ret) {
1292 ret = -EINVAL;
1293 goto err;
1294 }
1295
575c5807 1296 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
35b4b3c0
AV		 1297 if (IS_ERR(master)) {
1298 ret = PTR_ERR(master);
1299 goto err;
1300 }
1301
35b4b3c0
AV		 1302 return 0;
1303
1304err:
575c5807 1305 of_mpc8xxx_spi_free_chipselects(dev);
35b4b3c0
AV		 1306err_clk:
1307 kfree(pinfo);
1308 return ret;
1309}
1310
575c5807 1311static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
35b4b3c0
AV		 1312{
1313 int ret;
1314
575c5807 1315 ret = mpc8xxx_spi_remove(&ofdev->dev);
35b4b3c0
AV		 1316 if (ret)
1317 return ret;
575c5807 1318 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
35b4b3c0
AV		 1319 return 0;
1320}
1321
575c5807 1322static const struct of_device_id of_mpc8xxx_spi_match[] = {
35b4b3c0
AV		 1323 { .compatible = "fsl,spi" },
1324 {},
1325};
575c5807 1326MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
35b4b3c0 1327
575c5807 1328static struct of_platform_driver of_mpc8xxx_spi_driver = {
4018294b
GL		 1329 .driver = {
1330 .name = "mpc8xxx_spi",
1331 .owner = THIS_MODULE,
1332 .of_match_table = of_mpc8xxx_spi_match,
1333 },
575c5807
AV		 1334 .probe = of_mpc8xxx_spi_probe,
1335 .remove = __devexit_p(of_mpc8xxx_spi_remove),
35b4b3c0
AV		 1336};
1337
1338#ifdef CONFIG_MPC832x_RDB
1339/*
1340 * XXX XXX XXX
1341 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1342 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1343 * tree can work with OpenFirmware driver. But for now we support old trees
1344 * as well.
1345 */
575c5807 1346static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
35b4b3c0
AV		 1347{
1348 struct resource *mem;
e9a172f0 1349 int irq;
35b4b3c0
AV		 1350 struct spi_master *master;
1351
1352 if (!pdev->dev.platform_data)
1353 return -EINVAL;
1354
1355 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 if (!mem)
1357 return -EINVAL;
1358
1359 irq = platform_get_irq(pdev, 0);
e9a172f0 1360 if (irq <= 0)
35b4b3c0
AV		 1361 return -EINVAL;
1362
575c5807 1363 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
35b4b3c0
AV		 1364 if (IS_ERR(master))
1365 return PTR_ERR(master);
1366 return 0;
1367}
1368
575c5807 1369static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
35b4b3c0 1370{
575c5807 1371 return mpc8xxx_spi_remove(&pdev->dev);
35b4b3c0
AV		 1372}
1373
575c5807
AV		 1374MODULE_ALIAS("platform:mpc8xxx_spi");
1375static struct platform_driver mpc8xxx_spi_driver = {
1376 .probe = plat_mpc8xxx_spi_probe,
b3a08945 1377 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
ccf06998 1378 .driver = {
575c5807 1379 .name = "mpc8xxx_spi",
7e38c3c4 1380 .owner = THIS_MODULE,
ccf06998
KG		 1381 },
1382};
1383
35b4b3c0
AV		 1384static bool legacy_driver_failed;
1385
1386static void __init legacy_driver_register(void)
1387{
575c5807 1388 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
35b4b3c0
AV		 1389}
1390
1391static void __exit legacy_driver_unregister(void)
1392{
1393 if (legacy_driver_failed)
1394 return;
575c5807 1395 platform_driver_unregister(&mpc8xxx_spi_driver);
35b4b3c0
AV		 1396}
1397#else
1398static void __init legacy_driver_register(void) {}
1399static void __exit legacy_driver_unregister(void) {}
1400#endif /* CONFIG_MPC832x_RDB */
1401
575c5807 1402static int __init mpc8xxx_spi_init(void)
ccf06998 1403{
35b4b3c0 1404 legacy_driver_register();
575c5807 1405 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
ccf06998
KG		 1406}
1407
575c5807 1408static void __exit mpc8xxx_spi_exit(void)
ccf06998 1409{
575c5807 1410 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
35b4b3c0 1411 legacy_driver_unregister();
ccf06998
KG		 1412}
1413
575c5807
AV		 1414module_init(mpc8xxx_spi_init);
1415module_exit(mpc8xxx_spi_exit);
ccf06998
KG		 1416
1417MODULE_AUTHOR("Kumar Gala");
575c5807 1418MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
ccf06998 1419MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)