[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_mpc83xx.c

/*
 * MPC83xx SPI controller driver.
 *
 * Maintainer: Kumar Gala
 *
 * Copyright (C) 2006 Polycom, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>

#include <asm/irq.h>
#include <asm/io.h>

/* SPI Controller registers */
struct mpc83xx_spi_reg {
	u8 res1[0x20];
	__be32 mode;
	__be32 event;
	__be32 mask;
	__be32 command;
	__be32 transmit;
	__be32 receive;
};

/* SPI Controller mode register definitions */
#define	SPMODE_LOOP		(1 << 30)
#define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
#define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
#define	SPMODE_DIV16		(1 << 27)
#define	SPMODE_REV		(1 << 26)
#define	SPMODE_MS		(1 << 25)
#define	SPMODE_ENABLE		(1 << 24)
#define	SPMODE_LEN(x)		((x) << 20)
#define	SPMODE_PM(x)		((x) << 16)
#define	SPMODE_OP		(1 << 14)

/*
 * Default for SPI Mode:
 * 	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
 */
#define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))

/* SPIE register values */
#define	SPIE_NE		0x00000200	/* Not empty */
#define	SPIE_NF		0x00000100	/* Not full */

/* SPIM register values */
#define	SPIM_NE		0x00000200	/* Not empty */
#define	SPIM_NF		0x00000100	/* Not full */

/* SPI Controller driver's private data. */
struct mpc83xx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;

	struct mpc83xx_spi_reg __iomem *base;

	/* rx & tx bufs from the spi_transfer */
	const void *tx;
	void *rx;

	/* functions to deal with different sized buffers */
	void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
	u32(*get_tx) (struct mpc83xx_spi *);

	unsigned int count;
	u32 irq;

	unsigned nsecs;		/* (clock cycle time)/2 */

	u32 sysclk;
	u32 rx_shift;		/* RX data reg shift when in qe mode */
	u32 tx_shift;		/* TX data reg shift when in qe mode */

	bool qe_mode;

	void (*activate_cs) (u8 cs, u8 polarity);
	void (*deactivate_cs) (u8 cs, u8 polarity);
};

static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
{
	out_be32(reg, val);
}

static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
{
	return in_be32(reg);
}

#define MPC83XX_SPI_RX_BUF(type) 					  \
void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
{									  \
	type * rx = mpc83xx_spi->rx;					  \
	*rx++ = (type)(data >> mpc83xx_spi->rx_shift);			  \
	mpc83xx_spi->rx = rx;						  \
}

#define MPC83XX_SPI_TX_BUF(type)				\
u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)	\
{								\
	u32 data;						\
	const type * tx = mpc83xx_spi->tx;			\
	if (!tx)						\
		return 0;					\
	data = *tx++ << mpc83xx_spi->tx_shift;			\
	mpc83xx_spi->tx = tx;					\
	return data;						\
}

MPC83XX_SPI_RX_BUF(u8)
MPC83XX_SPI_RX_BUF(u16)
MPC83XX_SPI_RX_BUF(u32)
MPC83XX_SPI_TX_BUF(u8)
MPC83XX_SPI_TX_BUF(u16)
MPC83XX_SPI_TX_BUF(u32)

static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (value == BITBANG_CS_INACTIVE) {
		if (mpc83xx_spi->deactivate_cs)
			mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
	}

	if (value == BITBANG_CS_ACTIVE) {
		u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
		u32 len = spi->bits_per_word;
		if (len == 32)
			len = 0;
		else
			len = len - 1;

		/* mask out bits we are going to set */
		regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
				| SPMODE_LEN(0xF) | SPMODE_DIV16
				| SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP);

		if (spi->mode & SPI_CPHA)
			regval |= SPMODE_CP_BEGIN_EDGECLK;
		if (spi->mode & SPI_CPOL)
			regval |= SPMODE_CI_INACTIVEHIGH;
		if (!(spi->mode & SPI_LSB_FIRST))
			regval |= SPMODE_REV;
		if (spi->mode & SPI_LOOP)
			regval |= SPMODE_LOOP;

		regval |= SPMODE_LEN(len);

		if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
			u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
			if (pm > 0x0f) {
				printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
						"Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
						spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
				pm = 0x0f;
			}
			regval |= SPMODE_PM(pm) | SPMODE_DIV16;
		} else {
			u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
			regval |= SPMODE_PM(pm);
		}

		/* Turn off SPI unit prior changing mode */
		mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
		mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
		if (mpc83xx_spi->activate_cs)
			mpc83xx_spi->activate_cs(spi->chip_select, pol);
	}
}

static
int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u32 regval;
	u8 bits_per_word;
	u32 hz;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/* Make sure its a bit width we support [4..16, 32] */
	if ((bits_per_word < 4)
	    || ((bits_per_word > 16) && (bits_per_word != 32)))
		return -EINVAL;

	mpc83xx_spi->rx_shift = 0;
	mpc83xx_spi->tx_shift = 0;
	if (bits_per_word <= 8) {
		mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
		mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
		if (mpc83xx_spi->qe_mode) {
			mpc83xx_spi->rx_shift = 16;
			mpc83xx_spi->tx_shift = 24;
		}
	} else if (bits_per_word <= 16) {
		mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
		mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
		if (mpc83xx_spi->qe_mode) {
			mpc83xx_spi->rx_shift = 16;
			mpc83xx_spi->tx_shift = 16;
		}
	} else if (bits_per_word <= 32) {
		mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
		mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
	} else
		return -EINVAL;

	if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
		mpc83xx_spi->tx_shift = 0;
		if (bits_per_word <= 8)
			mpc83xx_spi->rx_shift = 8;
		else
			mpc83xx_spi->rx_shift = 0;
	}

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
	if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
		return -EINVAL;

	if (bits_per_word == 32)
		bits_per_word = 0;
	else
		bits_per_word = bits_per_word - 1;

	regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);

	/* mask out bits we are going to set */
	regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
	regval |= SPMODE_LEN(bits_per_word);
	if (!(spi->mode & SPI_LSB_FIRST))
		regval |= SPMODE_REV;

	/* Turn off SPI unit prior changing mode */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);

	return 0;
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS	(SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
			| SPI_LSB_FIRST | SPI_LOOP)

static int mpc83xx_spi_setup(struct spi_device *spi)
{
	struct spi_bitbang *bitbang;
	struct mpc83xx_spi *mpc83xx_spi;
	int retval;

	if (spi->mode & ~MODEBITS) {
		dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
			spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	if (!spi->max_speed_hz)
		return -EINVAL;

	bitbang = spi_master_get_devdata(spi->master);
	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	retval = mpc83xx_spi_setup_transfer(spi, NULL);
	if (retval < 0)
		return retval;

	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
		__FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
		spi->bits_per_word, 2 * mpc83xx_spi->nsecs);

	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	spin_lock(&bitbang->lock);
	if (!bitbang->busy) {
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(mpc83xx_spi->nsecs);
	}
	spin_unlock(&bitbang->lock);

	return 0;
}

static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u32 word;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	mpc83xx_spi->tx = t->tx_buf;
	mpc83xx_spi->rx = t->rx_buf;
	mpc83xx_spi->count = t->len;
	INIT_COMPLETION(mpc83xx_spi->done);

	/* enable rx ints */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);

	/* transmit word */
	word = mpc83xx_spi->get_tx(mpc83xx_spi);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);

	wait_for_completion(&mpc83xx_spi->done);

	/* disable rx ints */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);

	return t->len - mpc83xx_spi->count;
}

irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
{
	struct mpc83xx_spi *mpc83xx_spi = context_data;
	u32 event;
	irqreturn_t ret = IRQ_NONE;

	/* Get interrupt events(tx/rx) */
	event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);

	/* We need handle RX first */
	if (event & SPIE_NE) {
		u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);

		if (mpc83xx_spi->rx)
			mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);

		ret = IRQ_HANDLED;
	}

	if ((event & SPIE_NF) == 0)
		/* spin until TX is done */
		while (((event =
			 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
						SPIE_NF) == 0)
			 cpu_relax();

	mpc83xx_spi->count -= 1;
	if (mpc83xx_spi->count) {
		if (mpc83xx_spi->tx) {
			u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
			mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
					      word);
		}
	} else {
		complete(&mpc83xx_spi->done);
	}

	/* Clear the events */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);

	return ret;
}

static int __init mpc83xx_spi_probe(struct platform_device *dev)
{
	struct spi_master *master;
	struct mpc83xx_spi *mpc83xx_spi;
	struct fsl_spi_platform_data *pdata;
	struct resource *r;
	u32 regval;
	int ret = 0;

	/* Get resources(memory, IRQ) associated with the device */
	master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));

	if (master == NULL) {
		ret = -ENOMEM;
		goto err;
	}

	platform_set_drvdata(dev, master);
	pdata = dev->dev.platform_data;

	if (pdata == NULL) {
		ret = -ENODEV;
		goto free_master;
	}

	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENODEV;
		goto free_master;
	}
	mpc83xx_spi = spi_master_get_devdata(master);
	mpc83xx_spi->bitbang.master = spi_master_get(master);
	mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
	mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
	mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
	mpc83xx_spi->sysclk = pdata->sysclk;
	mpc83xx_spi->activate_cs = pdata->activate_cs;
	mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
	mpc83xx_spi->qe_mode = pdata->qe_mode;
	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;

	mpc83xx_spi->rx_shift = 0;
	mpc83xx_spi->tx_shift = 0;
	if (mpc83xx_spi->qe_mode) {
		mpc83xx_spi->rx_shift = 16;
		mpc83xx_spi->tx_shift = 24;
	}

	mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
	init_completion(&mpc83xx_spi->done);

	mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
	if (mpc83xx_spi->base == NULL) {
		ret = -ENOMEM;
		goto put_master;
	}

	mpc83xx_spi->irq = platform_get_irq(dev, 0);

	if (mpc83xx_spi->irq < 0) {
		ret = -ENXIO;
		goto unmap_io;
	}

	/* Register for SPI Interrupt */
	ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
			  0, "mpc83xx_spi", mpc83xx_spi);

	if (ret != 0)
		goto unmap_io;

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->max_chipselect;

	/* SPI controller initializations */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);

	/* Enable SPI interface */
	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
	if (pdata->qe_mode)
		regval |= SPMODE_OP;

	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);

	ret = spi_bitbang_start(&mpc83xx_spi->bitbang);

	if (ret != 0)
		goto free_irq;

	printk(KERN_INFO
	       "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
	       dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);

	return ret;

free_irq:
	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
unmap_io:
	iounmap(mpc83xx_spi->base);
put_master:
	spi_master_put(master);
free_master:
	kfree(master);
err:
	return ret;
}

static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
{
	struct mpc83xx_spi *mpc83xx_spi;
	struct spi_master *master;

	master = platform_get_drvdata(dev);
	mpc83xx_spi = spi_master_get_devdata(master);

	spi_bitbang_stop(&mpc83xx_spi->bitbang);
	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	iounmap(mpc83xx_spi->base);
	spi_master_put(mpc83xx_spi->bitbang.master);

	return 0;
}

static struct platform_driver mpc83xx_spi_driver = {
	.probe = mpc83xx_spi_probe,
	.remove = __devexit_p(mpc83xx_spi_remove),
	.driver = {
		   .name = "mpc83xx_spi",
	},
};

static int __init mpc83xx_spi_init(void)
{
	return platform_driver_register(&mpc83xx_spi_driver);
}

static void __exit mpc83xx_spi_exit(void)
{
	platform_driver_unregister(&mpc83xx_spi_driver);
}

module_init(mpc83xx_spi_init);
module_exit(mpc83xx_spi_exit);

MODULE_AUTHOR("Kumar Gala");
MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ccf06998 KG	1	/*
	2	* MPC83xx SPI controller driver.
	3	*
	4	* Maintainer: Kumar Gala
	5	*
	6	* Copyright (C) 2006 Polycom, Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
	17	#include <linux/completion.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/delay.h>
	20	#include <linux/irq.h>
	21	#include <linux/device.h>
	22	#include <linux/spi/spi.h>
	23	#include <linux/spi/spi_bitbang.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/fsl_devices.h>
	26
	27	#include <asm/irq.h>
	28	#include <asm/io.h>
	29
	30	/* SPI Controller registers */
	31	struct mpc83xx_spi_reg {
	32	u8 res1[0x20];
	33	__be32 mode;
	34	__be32 event;
	35	__be32 mask;
	36	__be32 command;
	37	__be32 transmit;
	38	__be32 receive;
	39	};
	40
	41	/* SPI Controller mode register definitions */
2a485d7a	42	#define SPMODE_LOOP (1 << 30)
ccf06998 KG	43	#define SPMODE_CI_INACTIVEHIGH (1 << 29)
	44	#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
	45	#define SPMODE_DIV16 (1 << 27)
	46	#define SPMODE_REV (1 << 26)
	47	#define SPMODE_MS (1 << 25)
	48	#define SPMODE_ENABLE (1 << 24)
	49	#define SPMODE_LEN(x) ((x) << 20)
	50	#define SPMODE_PM(x) ((x) << 16)
f29ba280	51	#define SPMODE_OP (1 << 14)
ccf06998 KG	52
	53	/*
	54	* Default for SPI Mode:
	55	* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
	56	*/
	57	#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH \| SPMODE_DIV16 \| SPMODE_REV \| \
	58	SPMODE_MS \| SPMODE_LEN(7) \| SPMODE_PM(0xf))
	59
	60	/* SPIE register values */
	61	#define SPIE_NE 0x00000200 /* Not empty */
	62	#define SPIE_NF 0x00000100 /* Not full */
	63
	64	/* SPIM register values */
	65	#define SPIM_NE 0x00000200 /* Not empty */
	66	#define SPIM_NF 0x00000100 /* Not full */
	67
	68	/* SPI Controller driver's private data. */
	69	struct mpc83xx_spi {
	70	/* bitbang has to be first */
	71	struct spi_bitbang bitbang;
	72	struct completion done;
	73
	74	struct mpc83xx_spi_reg __iomem *base;
	75
	76	/* rx & tx bufs from the spi_transfer */
	77	const void *tx;
	78	void *rx;
	79
	80	/* functions to deal with different sized buffers */
	81	void (get_rx) (u32 rx_data, struct mpc83xx_spi );
	82	u32(get_tx) (struct mpc83xx_spi );
	83
	84	unsigned int count;
	85	u32 irq;
	86
	87	unsigned nsecs; /* (clock cycle time)/2 */
	88
	89	u32 sysclk;
f29ba280 JT	90	u32 rx_shift; /* RX data reg shift when in qe mode */
	91	u32 tx_shift; /* TX data reg shift when in qe mode */
	92
	93	bool qe_mode;
	94
ccf06998 KG	95	void (*activate_cs) (u8 cs, u8 polarity);
	96	void (*deactivate_cs) (u8 cs, u8 polarity);
	97	};
	98
	99	static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
	100	{
	101	out_be32(reg, val);
	102	}
	103
	104	static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
	105	{
	106	return in_be32(reg);
	107	}
	108
	109	#define MPC83XX_SPI_RX_BUF(type) \
	110	void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
	111	{ \
	112	type * rx = mpc83xx_spi->rx; \
f29ba280	113	*rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
ccf06998 KG	114	mpc83xx_spi->rx = rx; \
	115	}
	116
	117	#define MPC83XX_SPI_TX_BUF(type) \
	118	u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
	119	{ \
	120	u32 data; \
	121	const type * tx = mpc83xx_spi->tx; \
4b1badf5 DB	122	if (!tx) \
4b1badf5 DB	123	return 0; \
f29ba280	124	data = *tx++ << mpc83xx_spi->tx_shift; \
ccf06998 KG	125	mpc83xx_spi->tx = tx; \
	126	return data; \
	127	}
	128
	129	MPC83XX_SPI_RX_BUF(u8)
	130	MPC83XX_SPI_RX_BUF(u16)
	131	MPC83XX_SPI_RX_BUF(u32)
	132	MPC83XX_SPI_TX_BUF(u8)
	133	MPC83XX_SPI_TX_BUF(u16)
	134	MPC83XX_SPI_TX_BUF(u32)
	135
	136	static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
	137	{
	138	struct mpc83xx_spi *mpc83xx_spi;
	139	u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
	140
	141	mpc83xx_spi = spi_master_get_devdata(spi->master);
	142
	143	if (value == BITBANG_CS_INACTIVE) {
	144	if (mpc83xx_spi->deactivate_cs)
	145	mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
	146	}
	147
	148	if (value == BITBANG_CS_ACTIVE) {
	149	u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	150	u32 len = spi->bits_per_word;
	151	if (len == 32)
	152	len = 0;
	153	else
	154	len = len - 1;
	155
	156	/* mask out bits we are going to set */
32421daa AV	157	regval &= ~(SPMODE_CP_BEGIN_EDGECLK \| SPMODE_CI_INACTIVEHIGH
32421daa AV	158	\| SPMODE_LEN(0xF) \| SPMODE_DIV16
2a485d7a	159	\| SPMODE_PM(0xF) \| SPMODE_REV \| SPMODE_LOOP);
ccf06998 KG	160
	161	if (spi->mode & SPI_CPHA)
	162	regval \|= SPMODE_CP_BEGIN_EDGECLK;
	163	if (spi->mode & SPI_CPOL)
	164	regval \|= SPMODE_CI_INACTIVEHIGH;
32421daa AV	165	if (!(spi->mode & SPI_LSB_FIRST))
32421daa AV	166	regval \|= SPMODE_REV;
2a485d7a AV	167	if (spi->mode & SPI_LOOP)
2a485d7a AV	168	regval \|= SPMODE_LOOP;
ccf06998 KG	169
	170	regval \|= SPMODE_LEN(len);
	171
	172	if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
	173	u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
698ca47e CW	174	if (pm > 0x0f) {
	175	printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
	176	"Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
	177	spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
	178	pm = 0x0f;
	179	}
ccf06998 KG	180	regval \|= SPMODE_PM(pm) \| SPMODE_DIV16;
	181	} else {
	182	u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
	183	regval \|= SPMODE_PM(pm);
	184	}
	185
49bb2300 AV	186	/* Turn off SPI unit prior changing mode */
49bb2300 AV	187	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
ccf06998 KG	188	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
	189	if (mpc83xx_spi->activate_cs)
	190	mpc83xx_spi->activate_cs(spi->chip_select, pol);
	191	}
	192	}
	193
	194	static
	195	int mpc83xx_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	196	{
	197	struct mpc83xx_spi *mpc83xx_spi;
	198	u32 regval;
	199	u8 bits_per_word;
	200	u32 hz;
	201
	202	mpc83xx_spi = spi_master_get_devdata(spi->master);
	203
	204	if (t) {
	205	bits_per_word = t->bits_per_word;
	206	hz = t->speed_hz;
	207	} else {
	208	bits_per_word = 0;
	209	hz = 0;
	210	}
	211
	212	/* spi_transfer level calls that work per-word */
	213	if (!bits_per_word)
	214	bits_per_word = spi->bits_per_word;
	215
	216	/* Make sure its a bit width we support [4..16, 32] */
	217	if ((bits_per_word < 4)
	218	\|\| ((bits_per_word > 16) && (bits_per_word != 32)))
	219	return -EINVAL;
	220
f29ba280 JT	221	mpc83xx_spi->rx_shift = 0;
f29ba280 JT	222	mpc83xx_spi->tx_shift = 0;
ccf06998 KG	223	if (bits_per_word <= 8) {
	224	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
	225	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
f29ba280 JT	226	if (mpc83xx_spi->qe_mode) {
	227	mpc83xx_spi->rx_shift = 16;
	228	mpc83xx_spi->tx_shift = 24;
	229	}
ccf06998 KG	230	} else if (bits_per_word <= 16) {
	231	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
	232	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
f29ba280 JT	233	if (mpc83xx_spi->qe_mode) {
	234	mpc83xx_spi->rx_shift = 16;
	235	mpc83xx_spi->tx_shift = 16;
	236	}
ccf06998 KG	237	} else if (bits_per_word <= 32) {
	238	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
	239	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
	240	} else
	241	return -EINVAL;
	242
35cc0b97 AV	243	if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
	244	mpc83xx_spi->tx_shift = 0;
	245	if (bits_per_word <= 8)
	246	mpc83xx_spi->rx_shift = 8;
	247	else
	248	mpc83xx_spi->rx_shift = 0;
	249	}
	250
ccf06998 KG	251	/* nsecs = (clock period)/2 */
	252	if (!hz)
	253	hz = spi->max_speed_hz;
	254	mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
	255	if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
	256	return -EINVAL;
	257
	258	if (bits_per_word == 32)
	259	bits_per_word = 0;
	260	else
	261	bits_per_word = bits_per_word - 1;
	262
	263	regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	264
32421daa AV	265	/* mask out bits we are going to set */
32421daa AV	266	regval &= ~(SPMODE_LEN(0xF) \| SPMODE_REV);
ccf06998	267	regval \|= SPMODE_LEN(bits_per_word);
32421daa AV	268	if (!(spi->mode & SPI_LSB_FIRST))
32421daa AV	269	regval \|= SPMODE_REV;
ccf06998	270
49bb2300 AV	271	/* Turn off SPI unit prior changing mode */
49bb2300 AV	272	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
ccf06998 KG	273	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
	274
	275	return 0;
	276	}
	277
dccd573b	278	/* the spi->mode bits understood by this driver: */
2a485d7a AV	279	#define MODEBITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
2a485d7a AV	280	\| SPI_LSB_FIRST \| SPI_LOOP)
dccd573b	281
ccf06998 KG	282	static int mpc83xx_spi_setup(struct spi_device *spi)
	283	{
	284	struct spi_bitbang *bitbang;
	285	struct mpc83xx_spi *mpc83xx_spi;
	286	int retval;
	287
dccd573b DB	288	if (spi->mode & ~MODEBITS) {
	289	dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
	290	spi->mode & ~MODEBITS);
	291	return -EINVAL;
	292	}
	293
ccf06998 KG	294	if (!spi->max_speed_hz)
	295	return -EINVAL;
	296
	297	bitbang = spi_master_get_devdata(spi->master);
	298	mpc83xx_spi = spi_master_get_devdata(spi->master);
	299
	300	if (!spi->bits_per_word)
	301	spi->bits_per_word = 8;
	302
	303	retval = mpc83xx_spi_setup_transfer(spi, NULL);
	304	if (retval < 0)
	305	return retval;
	306
	307	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
	308	__FUNCTION__, spi->mode & (SPI_CPOL \| SPI_CPHA),
	309	spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
	310
	311	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	312	* setup, unless the hardware defaults cooperate to avoid confusion
	313	* between normal (active low) and inverted chipselects.
	314	*/
	315
	316	/* deselect chip (low or high) */
	317	spin_lock(&bitbang->lock);
	318	if (!bitbang->busy) {
	319	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	320	ndelay(mpc83xx_spi->nsecs);
	321	}
	322	spin_unlock(&bitbang->lock);
	323
	324	return 0;
	325	}
	326
	327	static int mpc83xx_spi_bufs(struct spi_device spi, struct spi_transfer t)
	328	{
	329	struct mpc83xx_spi *mpc83xx_spi;
	330	u32 word;
	331
	332	mpc83xx_spi = spi_master_get_devdata(spi->master);
	333
	334	mpc83xx_spi->tx = t->tx_buf;
	335	mpc83xx_spi->rx = t->rx_buf;
	336	mpc83xx_spi->count = t->len;
	337	INIT_COMPLETION(mpc83xx_spi->done);
	338
	339	/* enable rx ints */
	340	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
	341
	342	/* transmit word */
	343	word = mpc83xx_spi->get_tx(mpc83xx_spi);
	344	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
	345
	346	wait_for_completion(&mpc83xx_spi->done);
	347
	348	/* disable rx ints */
	349	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	350
	351	return t->len - mpc83xx_spi->count;
	352	}
	353
7d12e780	354	irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
ccf06998 KG	355	{
	356	struct mpc83xx_spi *mpc83xx_spi = context_data;
	357	u32 event;
	358	irqreturn_t ret = IRQ_NONE;
	359
	360	/* Get interrupt events(tx/rx) */
	361	event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
	362
	363	/* We need handle RX first */
	364	if (event & SPIE_NE) {
	365	u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
	366
	367	if (mpc83xx_spi->rx)
	368	mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
	369
	370	ret = IRQ_HANDLED;
	371	}
	372
	373	if ((event & SPIE_NF) == 0)
	374	/* spin until TX is done */
	375	while (((event =
	376	mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
	377	SPIE_NF) == 0)
	378	cpu_relax();
	379
	380	mpc83xx_spi->count -= 1;
	381	if (mpc83xx_spi->count) {
	382	if (mpc83xx_spi->tx) {
	383	u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
	384	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
	385	word);
	386	}
	387	} else {
	388	complete(&mpc83xx_spi->done);
	389	}
	390
	391	/* Clear the events */
	392	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
	393
	394	return ret;
	395	}
	396
	397	static int __init mpc83xx_spi_probe(struct platform_device *dev)
	398	{
	399	struct spi_master *master;
	400	struct mpc83xx_spi *mpc83xx_spi;
	401	struct fsl_spi_platform_data *pdata;
	402	struct resource *r;
	403	u32 regval;
	404	int ret = 0;
	405
	406	/* Get resources(memory, IRQ) associated with the device */
	407	master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
	408
	409	if (master == NULL) {
	410	ret = -ENOMEM;
	411	goto err;
	412	}
	413
	414	platform_set_drvdata(dev, master);
	415	pdata = dev->dev.platform_data;
	416
	417	if (pdata == NULL) {
	418	ret = -ENODEV;
419	goto free_master;
420	}
421
422	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
423	if (r == NULL) {
424	ret = -ENODEV;
425	goto free_master;
426	}
ccf06998 KG	427	mpc83xx_spi = spi_master_get_devdata(master);
	428	mpc83xx_spi->bitbang.master = spi_master_get(master);
	429	mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
	430	mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
	431	mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
	432	mpc83xx_spi->sysclk = pdata->sysclk;
	433	mpc83xx_spi->activate_cs = pdata->activate_cs;
	434	mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
f29ba280	435	mpc83xx_spi->qe_mode = pdata->qe_mode;
ccf06998 KG	436	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
	437	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
	438
f29ba280 JT	439	mpc83xx_spi->rx_shift = 0;
	440	mpc83xx_spi->tx_shift = 0;
	441	if (mpc83xx_spi->qe_mode) {
	442	mpc83xx_spi->rx_shift = 16;
	443	mpc83xx_spi->tx_shift = 24;
	444	}
	445
ccf06998 KG	446	mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
	447	init_completion(&mpc83xx_spi->done);
	448
	449	mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
	450	if (mpc83xx_spi->base == NULL) {
	451	ret = -ENOMEM;
	452	goto put_master;
	453	}
	454
	455	mpc83xx_spi->irq = platform_get_irq(dev, 0);
	456
	457	if (mpc83xx_spi->irq < 0) {
	458	ret = -ENXIO;
	459	goto unmap_io;
	460	}
	461
	462	/* Register for SPI Interrupt */
	463	ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
	464	0, "mpc83xx_spi", mpc83xx_spi);
	465
	466	if (ret != 0)
	467	goto unmap_io;
	468
	469	master->bus_num = pdata->bus_num;
	470	master->num_chipselect = pdata->max_chipselect;
	471
	472	/* SPI controller initializations */
	473	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	474	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	475	mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
	476	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
	477
	478	/* Enable SPI interface */
	479	regval = pdata->initial_spmode \| SPMODE_INIT_VAL \| SPMODE_ENABLE;
f29ba280 JT	480	if (pdata->qe_mode)
	481	regval \|= SPMODE_OP;
	482
ccf06998 KG	483	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
	484
	485	ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
	486
	487	if (ret != 0)
	488	goto free_irq;
	489
	490	printk(KERN_INFO
	491	"%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
	492	dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
	493
	494	return ret;
	495
	496	free_irq:
	497	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	498	unmap_io:
	499	iounmap(mpc83xx_spi->base);
	500	put_master:
	501	spi_master_put(master);
	502	free_master:
	503	kfree(master);
	504	err:
	505	return ret;
	506	}
	507
	508	static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
	509	{
	510	struct mpc83xx_spi *mpc83xx_spi;
	511	struct spi_master *master;
	512
	513	master = platform_get_drvdata(dev);
	514	mpc83xx_spi = spi_master_get_devdata(master);
	515
	516	spi_bitbang_stop(&mpc83xx_spi->bitbang);
	517	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	518	iounmap(mpc83xx_spi->base);
	519	spi_master_put(mpc83xx_spi->bitbang.master);
	520
	521	return 0;
	522	}
	523
	524	static struct platform_driver mpc83xx_spi_driver = {
	525	.probe = mpc83xx_spi_probe,
	526	.remove = __devexit_p(mpc83xx_spi_remove),
	527	.driver = {
	528	.name = "mpc83xx_spi",
	529	},
	530	};
	531
	532	static int __init mpc83xx_spi_init(void)
	533	{
	534	return platform_driver_register(&mpc83xx_spi_driver);
	535	}
	536
	537	static void __exit mpc83xx_spi_exit(void)
	538	{
	539	platform_driver_unregister(&mpc83xx_spi_driver);
	540	}
	541
	542	module_init(mpc83xx_spi_init);
	543	module_exit(mpc83xx_spi_exit);
	544
	545	MODULE_AUTHOR("Kumar Gala");
	546	MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
547	MODULE_LICENSE("GPL");