Commit | Line | Data |
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ccf06998 KG |
1 | /* |
2 | * MPC83xx SPI controller driver. | |
3 | * | |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
35b4b3c0 AV |
17 | #include <linux/errno.h> |
18 | #include <linux/err.h> | |
ccf06998 KG |
19 | #include <linux/completion.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/spi/spi_bitbang.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/fsl_devices.h> | |
35b4b3c0 AV |
28 | #include <linux/of.h> |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_gpio.h> | |
32 | #include <linux/of_spi.h> | |
ccf06998 | 33 | |
35b4b3c0 | 34 | #include <sysdev/fsl_soc.h> |
ccf06998 KG |
35 | #include <asm/irq.h> |
36 | #include <asm/io.h> | |
37 | ||
38 | /* SPI Controller registers */ | |
39 | struct mpc83xx_spi_reg { | |
40 | u8 res1[0x20]; | |
41 | __be32 mode; | |
42 | __be32 event; | |
43 | __be32 mask; | |
44 | __be32 command; | |
45 | __be32 transmit; | |
46 | __be32 receive; | |
47 | }; | |
48 | ||
49 | /* SPI Controller mode register definitions */ | |
2a485d7a | 50 | #define SPMODE_LOOP (1 << 30) |
ccf06998 KG |
51 | #define SPMODE_CI_INACTIVEHIGH (1 << 29) |
52 | #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) | |
53 | #define SPMODE_DIV16 (1 << 27) | |
54 | #define SPMODE_REV (1 << 26) | |
55 | #define SPMODE_MS (1 << 25) | |
56 | #define SPMODE_ENABLE (1 << 24) | |
57 | #define SPMODE_LEN(x) ((x) << 20) | |
58 | #define SPMODE_PM(x) ((x) << 16) | |
f29ba280 | 59 | #define SPMODE_OP (1 << 14) |
c9bfcb31 | 60 | #define SPMODE_CG(x) ((x) << 7) |
ccf06998 KG |
61 | |
62 | /* | |
63 | * Default for SPI Mode: | |
64 | * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk | |
65 | */ | |
66 | #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ | |
67 | SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) | |
68 | ||
69 | /* SPIE register values */ | |
70 | #define SPIE_NE 0x00000200 /* Not empty */ | |
71 | #define SPIE_NF 0x00000100 /* Not full */ | |
72 | ||
73 | /* SPIM register values */ | |
74 | #define SPIM_NE 0x00000200 /* Not empty */ | |
75 | #define SPIM_NF 0x00000100 /* Not full */ | |
76 | ||
77 | /* SPI Controller driver's private data. */ | |
78 | struct mpc83xx_spi { | |
ccf06998 KG |
79 | struct mpc83xx_spi_reg __iomem *base; |
80 | ||
81 | /* rx & tx bufs from the spi_transfer */ | |
82 | const void *tx; | |
83 | void *rx; | |
84 | ||
85 | /* functions to deal with different sized buffers */ | |
86 | void (*get_rx) (u32 rx_data, struct mpc83xx_spi *); | |
87 | u32(*get_tx) (struct mpc83xx_spi *); | |
88 | ||
89 | unsigned int count; | |
35b4b3c0 | 90 | unsigned int irq; |
ccf06998 KG |
91 | |
92 | unsigned nsecs; /* (clock cycle time)/2 */ | |
93 | ||
e24a4d1e | 94 | u32 spibrg; /* SPIBRG input clock */ |
f29ba280 JT |
95 | u32 rx_shift; /* RX data reg shift when in qe mode */ |
96 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
97 | ||
98 | bool qe_mode; | |
99 | ||
c9bfcb31 JT |
100 | u8 busy; |
101 | ||
102 | struct workqueue_struct *workqueue; | |
103 | struct work_struct work; | |
104 | ||
105 | struct list_head queue; | |
106 | spinlock_t lock; | |
107 | ||
108 | struct completion done; | |
109 | }; | |
110 | ||
111 | struct spi_mpc83xx_cs { | |
112 | /* functions to deal with different sized buffers */ | |
113 | void (*get_rx) (u32 rx_data, struct mpc83xx_spi *); | |
114 | u32 (*get_tx) (struct mpc83xx_spi *); | |
115 | u32 rx_shift; /* RX data reg shift when in qe mode */ | |
116 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
117 | u32 hw_mode; /* Holds HW mode register settings */ | |
ccf06998 KG |
118 | }; |
119 | ||
120 | static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val) | |
121 | { | |
122 | out_be32(reg, val); | |
123 | } | |
124 | ||
125 | static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg) | |
126 | { | |
127 | return in_be32(reg); | |
128 | } | |
129 | ||
130 | #define MPC83XX_SPI_RX_BUF(type) \ | |
34c8a20c | 131 | static \ |
ccf06998 KG |
132 | void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \ |
133 | { \ | |
134 | type * rx = mpc83xx_spi->rx; \ | |
f29ba280 | 135 | *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \ |
ccf06998 KG |
136 | mpc83xx_spi->rx = rx; \ |
137 | } | |
138 | ||
139 | #define MPC83XX_SPI_TX_BUF(type) \ | |
34c8a20c | 140 | static \ |
ccf06998 KG |
141 | u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \ |
142 | { \ | |
143 | u32 data; \ | |
144 | const type * tx = mpc83xx_spi->tx; \ | |
4b1badf5 DB |
145 | if (!tx) \ |
146 | return 0; \ | |
f29ba280 | 147 | data = *tx++ << mpc83xx_spi->tx_shift; \ |
ccf06998 KG |
148 | mpc83xx_spi->tx = tx; \ |
149 | return data; \ | |
150 | } | |
151 | ||
152 | MPC83XX_SPI_RX_BUF(u8) | |
153 | MPC83XX_SPI_RX_BUF(u16) | |
154 | MPC83XX_SPI_RX_BUF(u32) | |
155 | MPC83XX_SPI_TX_BUF(u8) | |
156 | MPC83XX_SPI_TX_BUF(u16) | |
157 | MPC83XX_SPI_TX_BUF(u32) | |
158 | ||
159 | static void mpc83xx_spi_chipselect(struct spi_device *spi, int value) | |
160 | { | |
364fdbc0 AV |
161 | struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master); |
162 | struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data; | |
163 | bool pol = spi->mode & SPI_CS_HIGH; | |
c9bfcb31 | 164 | struct spi_mpc83xx_cs *cs = spi->controller_state; |
ccf06998 | 165 | |
ccf06998 | 166 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
167 | if (pdata->cs_control) |
168 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
169 | } |
170 | ||
171 | if (value == BITBANG_CS_ACTIVE) { | |
172 | u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); | |
a44648b0 | 173 | |
c9bfcb31 JT |
174 | mpc83xx_spi->rx_shift = cs->rx_shift; |
175 | mpc83xx_spi->tx_shift = cs->tx_shift; | |
176 | mpc83xx_spi->get_rx = cs->get_rx; | |
177 | mpc83xx_spi->get_tx = cs->get_tx; | |
178 | ||
179 | if (cs->hw_mode != regval) { | |
180 | unsigned long flags; | |
34c8a20c | 181 | __be32 __iomem *mode = &mpc83xx_spi->base->mode; |
c9bfcb31 JT |
182 | |
183 | regval = cs->hw_mode; | |
184 | /* Turn off IRQs locally to minimize time that | |
185 | * SPI is disabled | |
186 | */ | |
187 | local_irq_save(flags); | |
188 | /* Turn off SPI unit prior changing mode */ | |
34c8a20c AV |
189 | mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE); |
190 | mpc83xx_spi_write_reg(mode, regval); | |
c9bfcb31 | 191 | local_irq_restore(flags); |
ccf06998 | 192 | } |
364fdbc0 AV |
193 | if (pdata->cs_control) |
194 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
195 | } |
196 | } | |
197 | ||
198 | static | |
199 | int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
200 | { | |
201 | struct mpc83xx_spi *mpc83xx_spi; | |
202 | u32 regval; | |
c9bfcb31 | 203 | u8 bits_per_word, pm; |
ccf06998 | 204 | u32 hz; |
c9bfcb31 | 205 | struct spi_mpc83xx_cs *cs = spi->controller_state; |
ccf06998 KG |
206 | |
207 | mpc83xx_spi = spi_master_get_devdata(spi->master); | |
208 | ||
209 | if (t) { | |
210 | bits_per_word = t->bits_per_word; | |
211 | hz = t->speed_hz; | |
212 | } else { | |
213 | bits_per_word = 0; | |
214 | hz = 0; | |
215 | } | |
216 | ||
217 | /* spi_transfer level calls that work per-word */ | |
218 | if (!bits_per_word) | |
219 | bits_per_word = spi->bits_per_word; | |
220 | ||
221 | /* Make sure its a bit width we support [4..16, 32] */ | |
222 | if ((bits_per_word < 4) | |
223 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
224 | return -EINVAL; | |
225 | ||
c9bfcb31 JT |
226 | if (!hz) |
227 | hz = spi->max_speed_hz; | |
228 | ||
229 | cs->rx_shift = 0; | |
230 | cs->tx_shift = 0; | |
ccf06998 | 231 | if (bits_per_word <= 8) { |
c9bfcb31 JT |
232 | cs->get_rx = mpc83xx_spi_rx_buf_u8; |
233 | cs->get_tx = mpc83xx_spi_tx_buf_u8; | |
f29ba280 | 234 | if (mpc83xx_spi->qe_mode) { |
c9bfcb31 JT |
235 | cs->rx_shift = 16; |
236 | cs->tx_shift = 24; | |
f29ba280 | 237 | } |
ccf06998 | 238 | } else if (bits_per_word <= 16) { |
c9bfcb31 JT |
239 | cs->get_rx = mpc83xx_spi_rx_buf_u16; |
240 | cs->get_tx = mpc83xx_spi_tx_buf_u16; | |
f29ba280 | 241 | if (mpc83xx_spi->qe_mode) { |
c9bfcb31 JT |
242 | cs->rx_shift = 16; |
243 | cs->tx_shift = 16; | |
f29ba280 | 244 | } |
ccf06998 | 245 | } else if (bits_per_word <= 32) { |
c9bfcb31 JT |
246 | cs->get_rx = mpc83xx_spi_rx_buf_u32; |
247 | cs->get_tx = mpc83xx_spi_tx_buf_u32; | |
ccf06998 KG |
248 | } else |
249 | return -EINVAL; | |
250 | ||
35cc0b97 | 251 | if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) { |
c9bfcb31 | 252 | cs->tx_shift = 0; |
35cc0b97 | 253 | if (bits_per_word <= 8) |
c9bfcb31 | 254 | cs->rx_shift = 8; |
35cc0b97 | 255 | else |
c9bfcb31 | 256 | cs->rx_shift = 0; |
35cc0b97 AV |
257 | } |
258 | ||
c9bfcb31 JT |
259 | mpc83xx_spi->rx_shift = cs->rx_shift; |
260 | mpc83xx_spi->tx_shift = cs->tx_shift; | |
261 | mpc83xx_spi->get_rx = cs->get_rx; | |
262 | mpc83xx_spi->get_tx = cs->get_tx; | |
ccf06998 KG |
263 | |
264 | if (bits_per_word == 32) | |
265 | bits_per_word = 0; | |
266 | else | |
267 | bits_per_word = bits_per_word - 1; | |
268 | ||
32421daa | 269 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
270 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
271 | | SPMODE_PM(0xF)); | |
272 | ||
273 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
274 | ||
a61f5345 | 275 | if ((mpc83xx_spi->spibrg / hz) > 64) { |
53604dbe | 276 | cs->hw_mode |= SPMODE_DIV16; |
a61f5345 CG |
277 | pm = mpc83xx_spi->spibrg / (hz * 64); |
278 | if (pm > 16) { | |
53604dbe PK |
279 | dev_err(&spi->dev, "Requested speed is too " |
280 | "low: %d Hz. Will use %d Hz instead.\n", | |
281 | hz, mpc83xx_spi->spibrg / 1024); | |
282 | pm = 16; | |
c9bfcb31 | 283 | } |
a61f5345 | 284 | } else |
c9bfcb31 | 285 | pm = mpc83xx_spi->spibrg / (hz * 4); |
a61f5345 CG |
286 | if (pm) |
287 | pm--; | |
288 | ||
289 | cs->hw_mode |= SPMODE_PM(pm); | |
c9bfcb31 JT |
290 | regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); |
291 | if (cs->hw_mode != regval) { | |
292 | unsigned long flags; | |
34c8a20c | 293 | __be32 __iomem *mode = &mpc83xx_spi->base->mode; |
c9bfcb31 JT |
294 | |
295 | regval = cs->hw_mode; | |
296 | /* Turn off IRQs locally to minimize time | |
297 | * that SPI is disabled | |
298 | */ | |
299 | local_irq_save(flags); | |
300 | /* Turn off SPI unit prior changing mode */ | |
34c8a20c AV |
301 | mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE); |
302 | mpc83xx_spi_write_reg(mode, regval); | |
c9bfcb31 JT |
303 | local_irq_restore(flags); |
304 | } | |
305 | return 0; | |
306 | } | |
ccf06998 | 307 | |
c9bfcb31 JT |
308 | static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
309 | { | |
310 | struct mpc83xx_spi *mpc83xx_spi; | |
311 | u32 word, len, bits_per_word; | |
ccf06998 | 312 | |
c9bfcb31 JT |
313 | mpc83xx_spi = spi_master_get_devdata(spi->master); |
314 | ||
315 | mpc83xx_spi->tx = t->tx_buf; | |
316 | mpc83xx_spi->rx = t->rx_buf; | |
317 | bits_per_word = spi->bits_per_word; | |
318 | if (t->bits_per_word) | |
319 | bits_per_word = t->bits_per_word; | |
320 | len = t->len; | |
aa77d96b PK |
321 | if (bits_per_word > 8) { |
322 | /* invalid length? */ | |
323 | if (len & 1) | |
324 | return -EINVAL; | |
c9bfcb31 | 325 | len /= 2; |
aa77d96b PK |
326 | } |
327 | if (bits_per_word > 16) { | |
328 | /* invalid length? */ | |
329 | if (len & 1) | |
330 | return -EINVAL; | |
c9bfcb31 | 331 | len /= 2; |
aa77d96b | 332 | } |
c9bfcb31 | 333 | mpc83xx_spi->count = len; |
aa77d96b | 334 | |
c9bfcb31 JT |
335 | INIT_COMPLETION(mpc83xx_spi->done); |
336 | ||
337 | /* enable rx ints */ | |
338 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE); | |
339 | ||
340 | /* transmit word */ | |
341 | word = mpc83xx_spi->get_tx(mpc83xx_spi); | |
342 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word); | |
343 | ||
344 | wait_for_completion(&mpc83xx_spi->done); | |
345 | ||
346 | /* disable rx ints */ | |
347 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0); | |
348 | ||
349 | return mpc83xx_spi->count; | |
350 | } | |
351 | ||
352 | static void mpc83xx_spi_work(struct work_struct *work) | |
353 | { | |
354 | struct mpc83xx_spi *mpc83xx_spi = | |
355 | container_of(work, struct mpc83xx_spi, work); | |
356 | ||
357 | spin_lock_irq(&mpc83xx_spi->lock); | |
358 | mpc83xx_spi->busy = 1; | |
359 | while (!list_empty(&mpc83xx_spi->queue)) { | |
360 | struct spi_message *m; | |
361 | struct spi_device *spi; | |
362 | struct spi_transfer *t = NULL; | |
363 | unsigned cs_change; | |
364 | int status, nsecs = 50; | |
365 | ||
366 | m = container_of(mpc83xx_spi->queue.next, | |
367 | struct spi_message, queue); | |
368 | list_del_init(&m->queue); | |
369 | spin_unlock_irq(&mpc83xx_spi->lock); | |
370 | ||
371 | spi = m->spi; | |
372 | cs_change = 1; | |
373 | status = 0; | |
374 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
375 | if (t->bits_per_word || t->speed_hz) { | |
376 | /* Don't allow changes if CS is active */ | |
377 | status = -EINVAL; | |
378 | ||
379 | if (cs_change) | |
380 | status = mpc83xx_spi_setup_transfer(spi, t); | |
381 | if (status < 0) | |
382 | break; | |
383 | } | |
384 | ||
385 | if (cs_change) | |
386 | mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE); | |
387 | cs_change = t->cs_change; | |
388 | if (t->len) | |
389 | status = mpc83xx_spi_bufs(spi, t); | |
390 | if (status) { | |
391 | status = -EMSGSIZE; | |
392 | break; | |
393 | } | |
394 | m->actual_length += t->len; | |
395 | ||
396 | if (t->delay_usecs) | |
397 | udelay(t->delay_usecs); | |
398 | ||
399 | if (cs_change) { | |
400 | ndelay(nsecs); | |
401 | mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
402 | ndelay(nsecs); | |
403 | } | |
404 | } | |
405 | ||
406 | m->status = status; | |
407 | m->complete(m->context); | |
408 | ||
409 | if (status || !cs_change) { | |
410 | ndelay(nsecs); | |
411 | mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
412 | } | |
413 | ||
414 | mpc83xx_spi_setup_transfer(spi, NULL); | |
415 | ||
416 | spin_lock_irq(&mpc83xx_spi->lock); | |
417 | } | |
418 | mpc83xx_spi->busy = 0; | |
419 | spin_unlock_irq(&mpc83xx_spi->lock); | |
ccf06998 KG |
420 | } |
421 | ||
dccd573b | 422 | /* the spi->mode bits understood by this driver: */ |
2a485d7a AV |
423 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
424 | | SPI_LSB_FIRST | SPI_LOOP) | |
dccd573b | 425 | |
ccf06998 KG |
426 | static int mpc83xx_spi_setup(struct spi_device *spi) |
427 | { | |
ccf06998 KG |
428 | struct mpc83xx_spi *mpc83xx_spi; |
429 | int retval; | |
c9bfcb31 JT |
430 | u32 hw_mode; |
431 | struct spi_mpc83xx_cs *cs = spi->controller_state; | |
ccf06998 | 432 | |
dccd573b DB |
433 | if (spi->mode & ~MODEBITS) { |
434 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
435 | spi->mode & ~MODEBITS); | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
ccf06998 KG |
439 | if (!spi->max_speed_hz) |
440 | return -EINVAL; | |
441 | ||
c9bfcb31 JT |
442 | if (!cs) { |
443 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
444 | if (!cs) | |
445 | return -ENOMEM; | |
446 | spi->controller_state = cs; | |
447 | } | |
ccf06998 KG |
448 | mpc83xx_spi = spi_master_get_devdata(spi->master); |
449 | ||
450 | if (!spi->bits_per_word) | |
451 | spi->bits_per_word = 8; | |
452 | ||
c9bfcb31 JT |
453 | hw_mode = cs->hw_mode; /* Save orginal settings */ |
454 | cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); | |
455 | /* mask out bits we are going to set */ | |
456 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
457 | | SPMODE_REV | SPMODE_LOOP); | |
458 | ||
459 | if (spi->mode & SPI_CPHA) | |
460 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
461 | if (spi->mode & SPI_CPOL) | |
462 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
463 | if (!(spi->mode & SPI_LSB_FIRST)) | |
464 | cs->hw_mode |= SPMODE_REV; | |
465 | if (spi->mode & SPI_LOOP) | |
466 | cs->hw_mode |= SPMODE_LOOP; | |
467 | ||
ccf06998 | 468 | retval = mpc83xx_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
469 | if (retval < 0) { |
470 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 471 | return retval; |
c9bfcb31 | 472 | } |
ccf06998 | 473 | |
c9bfcb31 | 474 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n", |
b687d2a8 | 475 | __func__, spi->mode & (SPI_CPOL | SPI_CPHA), |
c9bfcb31 JT |
476 | spi->bits_per_word, spi->max_speed_hz); |
477 | #if 0 /* Don't think this is needed */ | |
ccf06998 KG |
478 | /* NOTE we _need_ to call chipselect() early, ideally with adapter |
479 | * setup, unless the hardware defaults cooperate to avoid confusion | |
480 | * between normal (active low) and inverted chipselects. | |
481 | */ | |
482 | ||
483 | /* deselect chip (low or high) */ | |
c9bfcb31 JT |
484 | spin_lock(&mpc83xx_spi->lock); |
485 | if (!mpc83xx_spi->busy) | |
486 | mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
487 | spin_unlock(&mpc83xx_spi->lock); | |
488 | #endif | |
ccf06998 KG |
489 | return 0; |
490 | } | |
491 | ||
34c8a20c | 492 | static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data) |
ccf06998 KG |
493 | { |
494 | struct mpc83xx_spi *mpc83xx_spi = context_data; | |
495 | u32 event; | |
496 | irqreturn_t ret = IRQ_NONE; | |
497 | ||
498 | /* Get interrupt events(tx/rx) */ | |
499 | event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event); | |
500 | ||
501 | /* We need handle RX first */ | |
502 | if (event & SPIE_NE) { | |
503 | u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive); | |
504 | ||
505 | if (mpc83xx_spi->rx) | |
506 | mpc83xx_spi->get_rx(rx_data, mpc83xx_spi); | |
507 | ||
508 | ret = IRQ_HANDLED; | |
509 | } | |
510 | ||
511 | if ((event & SPIE_NF) == 0) | |
512 | /* spin until TX is done */ | |
513 | while (((event = | |
514 | mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) & | |
515 | SPIE_NF) == 0) | |
516 | cpu_relax(); | |
517 | ||
518 | mpc83xx_spi->count -= 1; | |
519 | if (mpc83xx_spi->count) { | |
65e213cd JA |
520 | u32 word = mpc83xx_spi->get_tx(mpc83xx_spi); |
521 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word); | |
ccf06998 KG |
522 | } else { |
523 | complete(&mpc83xx_spi->done); | |
524 | } | |
525 | ||
526 | /* Clear the events */ | |
527 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event); | |
528 | ||
529 | return ret; | |
530 | } | |
c9bfcb31 JT |
531 | static int mpc83xx_spi_transfer(struct spi_device *spi, |
532 | struct spi_message *m) | |
533 | { | |
534 | struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master); | |
535 | unsigned long flags; | |
536 | ||
537 | m->actual_length = 0; | |
538 | m->status = -EINPROGRESS; | |
539 | ||
540 | spin_lock_irqsave(&mpc83xx_spi->lock, flags); | |
541 | list_add_tail(&m->queue, &mpc83xx_spi->queue); | |
542 | queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work); | |
543 | spin_unlock_irqrestore(&mpc83xx_spi->lock, flags); | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | ||
549 | static void mpc83xx_spi_cleanup(struct spi_device *spi) | |
550 | { | |
551 | kfree(spi->controller_state); | |
552 | } | |
ccf06998 | 553 | |
35b4b3c0 AV |
554 | static struct spi_master * __devinit |
555 | mpc83xx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) | |
ccf06998 | 556 | { |
35b4b3c0 | 557 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 KG |
558 | struct spi_master *master; |
559 | struct mpc83xx_spi *mpc83xx_spi; | |
ccf06998 KG |
560 | u32 regval; |
561 | int ret = 0; | |
562 | ||
35b4b3c0 | 563 | master = spi_alloc_master(dev, sizeof(struct mpc83xx_spi)); |
ccf06998 KG |
564 | if (master == NULL) { |
565 | ret = -ENOMEM; | |
566 | goto err; | |
567 | } | |
568 | ||
35b4b3c0 | 569 | dev_set_drvdata(dev, master); |
ccf06998 | 570 | |
c9bfcb31 JT |
571 | master->setup = mpc83xx_spi_setup; |
572 | master->transfer = mpc83xx_spi_transfer; | |
573 | master->cleanup = mpc83xx_spi_cleanup; | |
574 | ||
ccf06998 | 575 | mpc83xx_spi = spi_master_get_devdata(master); |
f29ba280 | 576 | mpc83xx_spi->qe_mode = pdata->qe_mode; |
ccf06998 KG |
577 | mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8; |
578 | mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8; | |
59a0ea50 | 579 | mpc83xx_spi->spibrg = pdata->sysclk; |
e24a4d1e | 580 | |
f29ba280 JT |
581 | mpc83xx_spi->rx_shift = 0; |
582 | mpc83xx_spi->tx_shift = 0; | |
583 | if (mpc83xx_spi->qe_mode) { | |
584 | mpc83xx_spi->rx_shift = 16; | |
585 | mpc83xx_spi->tx_shift = 24; | |
586 | } | |
587 | ||
ccf06998 KG |
588 | init_completion(&mpc83xx_spi->done); |
589 | ||
35b4b3c0 | 590 | mpc83xx_spi->base = ioremap(mem->start, mem->end - mem->start + 1); |
ccf06998 KG |
591 | if (mpc83xx_spi->base == NULL) { |
592 | ret = -ENOMEM; | |
593 | goto put_master; | |
594 | } | |
595 | ||
35b4b3c0 | 596 | mpc83xx_spi->irq = irq; |
ccf06998 KG |
597 | |
598 | /* Register for SPI Interrupt */ | |
599 | ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq, | |
600 | 0, "mpc83xx_spi", mpc83xx_spi); | |
601 | ||
602 | if (ret != 0) | |
603 | goto unmap_io; | |
604 | ||
605 | master->bus_num = pdata->bus_num; | |
606 | master->num_chipselect = pdata->max_chipselect; | |
607 | ||
608 | /* SPI controller initializations */ | |
609 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0); | |
610 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0); | |
611 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0); | |
612 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff); | |
613 | ||
614 | /* Enable SPI interface */ | |
615 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
f29ba280 JT |
616 | if (pdata->qe_mode) |
617 | regval |= SPMODE_OP; | |
618 | ||
ccf06998 | 619 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); |
c9bfcb31 JT |
620 | spin_lock_init(&mpc83xx_spi->lock); |
621 | init_completion(&mpc83xx_spi->done); | |
622 | INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work); | |
623 | INIT_LIST_HEAD(&mpc83xx_spi->queue); | |
ccf06998 | 624 | |
c9bfcb31 | 625 | mpc83xx_spi->workqueue = create_singlethread_workqueue( |
6c7377ab | 626 | dev_name(master->dev.parent)); |
c9bfcb31 JT |
627 | if (mpc83xx_spi->workqueue == NULL) { |
628 | ret = -EBUSY; | |
ccf06998 | 629 | goto free_irq; |
c9bfcb31 JT |
630 | } |
631 | ||
632 | ret = spi_register_master(master); | |
633 | if (ret < 0) | |
634 | goto unreg_master; | |
ccf06998 KG |
635 | |
636 | printk(KERN_INFO | |
637 | "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n", | |
35b4b3c0 | 638 | dev_name(dev), mpc83xx_spi->base, mpc83xx_spi->irq); |
ccf06998 | 639 | |
35b4b3c0 | 640 | return master; |
ccf06998 | 641 | |
c9bfcb31 JT |
642 | unreg_master: |
643 | destroy_workqueue(mpc83xx_spi->workqueue); | |
ccf06998 KG |
644 | free_irq: |
645 | free_irq(mpc83xx_spi->irq, mpc83xx_spi); | |
646 | unmap_io: | |
647 | iounmap(mpc83xx_spi->base); | |
648 | put_master: | |
649 | spi_master_put(master); | |
ccf06998 | 650 | err: |
35b4b3c0 | 651 | return ERR_PTR(ret); |
ccf06998 KG |
652 | } |
653 | ||
35b4b3c0 | 654 | static int __devexit mpc83xx_spi_remove(struct device *dev) |
ccf06998 KG |
655 | { |
656 | struct mpc83xx_spi *mpc83xx_spi; | |
657 | struct spi_master *master; | |
658 | ||
35b4b3c0 | 659 | master = dev_get_drvdata(dev); |
ccf06998 KG |
660 | mpc83xx_spi = spi_master_get_devdata(master); |
661 | ||
c9bfcb31 JT |
662 | flush_workqueue(mpc83xx_spi->workqueue); |
663 | destroy_workqueue(mpc83xx_spi->workqueue); | |
664 | spi_unregister_master(master); | |
665 | ||
ccf06998 KG |
666 | free_irq(mpc83xx_spi->irq, mpc83xx_spi); |
667 | iounmap(mpc83xx_spi->base); | |
ccf06998 KG |
668 | |
669 | return 0; | |
670 | } | |
671 | ||
35b4b3c0 AV |
672 | struct mpc83xx_spi_probe_info { |
673 | struct fsl_spi_platform_data pdata; | |
674 | int *gpios; | |
675 | bool *alow_flags; | |
676 | }; | |
677 | ||
678 | static struct mpc83xx_spi_probe_info * | |
679 | to_of_pinfo(struct fsl_spi_platform_data *pdata) | |
680 | { | |
681 | return container_of(pdata, struct mpc83xx_spi_probe_info, pdata); | |
682 | } | |
683 | ||
684 | static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on) | |
685 | { | |
686 | struct device *dev = spi->dev.parent; | |
687 | struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); | |
688 | u16 cs = spi->chip_select; | |
689 | int gpio = pinfo->gpios[cs]; | |
690 | bool alow = pinfo->alow_flags[cs]; | |
691 | ||
692 | gpio_set_value(gpio, on ^ alow); | |
693 | } | |
694 | ||
695 | static int of_mpc83xx_spi_get_chipselects(struct device *dev) | |
696 | { | |
697 | struct device_node *np = dev_archdata_get_node(&dev->archdata); | |
698 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
699 | struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
700 | unsigned int ngpios; | |
701 | int i = 0; | |
702 | int ret; | |
703 | ||
704 | ngpios = of_gpio_count(np); | |
705 | if (!ngpios) { | |
706 | /* | |
707 | * SPI w/o chip-select line. One SPI device is still permitted | |
708 | * though. | |
709 | */ | |
710 | pdata->max_chipselect = 1; | |
711 | return 0; | |
712 | } | |
713 | ||
714 | pinfo->gpios = kmalloc(ngpios * sizeof(pinfo->gpios), GFP_KERNEL); | |
715 | if (!pinfo->gpios) | |
716 | return -ENOMEM; | |
717 | memset(pinfo->gpios, -1, ngpios * sizeof(pinfo->gpios)); | |
718 | ||
719 | pinfo->alow_flags = kzalloc(ngpios * sizeof(pinfo->alow_flags), | |
720 | GFP_KERNEL); | |
721 | if (!pinfo->alow_flags) { | |
722 | ret = -ENOMEM; | |
723 | goto err_alloc_flags; | |
724 | } | |
725 | ||
726 | for (; i < ngpios; i++) { | |
727 | int gpio; | |
728 | enum of_gpio_flags flags; | |
729 | ||
730 | gpio = of_get_gpio_flags(np, i, &flags); | |
731 | if (!gpio_is_valid(gpio)) { | |
732 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
733 | goto err_loop; | |
734 | } | |
735 | ||
736 | ret = gpio_request(gpio, dev_name(dev)); | |
737 | if (ret) { | |
738 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
739 | goto err_loop; | |
740 | } | |
741 | ||
742 | pinfo->gpios[i] = gpio; | |
743 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
744 | ||
745 | ret = gpio_direction_output(pinfo->gpios[i], | |
746 | pinfo->alow_flags[i]); | |
747 | if (ret) { | |
748 | dev_err(dev, "can't set output direction for gpio " | |
749 | "#%d: %d\n", i, ret); | |
750 | goto err_loop; | |
751 | } | |
752 | } | |
753 | ||
754 | pdata->max_chipselect = ngpios; | |
755 | pdata->cs_control = mpc83xx_spi_cs_control; | |
756 | ||
757 | return 0; | |
758 | ||
759 | err_loop: | |
760 | while (i >= 0) { | |
761 | if (gpio_is_valid(pinfo->gpios[i])) | |
762 | gpio_free(pinfo->gpios[i]); | |
763 | i--; | |
764 | } | |
765 | ||
766 | kfree(pinfo->alow_flags); | |
767 | pinfo->alow_flags = NULL; | |
768 | err_alloc_flags: | |
769 | kfree(pinfo->gpios); | |
770 | pinfo->gpios = NULL; | |
771 | return ret; | |
772 | } | |
773 | ||
774 | static int of_mpc83xx_spi_free_chipselects(struct device *dev) | |
775 | { | |
776 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
777 | struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
778 | int i; | |
779 | ||
780 | if (!pinfo->gpios) | |
781 | return 0; | |
782 | ||
783 | for (i = 0; i < pdata->max_chipselect; i++) { | |
784 | if (gpio_is_valid(pinfo->gpios[i])) | |
785 | gpio_free(pinfo->gpios[i]); | |
786 | } | |
787 | ||
788 | kfree(pinfo->gpios); | |
789 | kfree(pinfo->alow_flags); | |
790 | return 0; | |
791 | } | |
792 | ||
793 | static int __devinit of_mpc83xx_spi_probe(struct of_device *ofdev, | |
794 | const struct of_device_id *ofid) | |
795 | { | |
796 | struct device *dev = &ofdev->dev; | |
797 | struct device_node *np = ofdev->node; | |
798 | struct mpc83xx_spi_probe_info *pinfo; | |
799 | struct fsl_spi_platform_data *pdata; | |
800 | struct spi_master *master; | |
801 | struct resource mem; | |
802 | struct resource irq; | |
803 | const void *prop; | |
804 | int ret = -ENOMEM; | |
805 | ||
806 | pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL); | |
807 | if (!pinfo) | |
808 | return -ENOMEM; | |
809 | ||
810 | pdata = &pinfo->pdata; | |
811 | dev->platform_data = pdata; | |
812 | ||
813 | /* Allocate bus num dynamically. */ | |
814 | pdata->bus_num = -1; | |
815 | ||
816 | /* SPI controller is either clocked from QE or SoC clock. */ | |
817 | pdata->sysclk = get_brgfreq(); | |
818 | if (pdata->sysclk == -1) { | |
819 | pdata->sysclk = fsl_get_sys_freq(); | |
820 | if (pdata->sysclk == -1) { | |
821 | ret = -ENODEV; | |
822 | goto err_clk; | |
823 | } | |
824 | } | |
825 | ||
826 | prop = of_get_property(np, "mode", NULL); | |
827 | if (prop && !strcmp(prop, "cpu-qe")) | |
828 | pdata->qe_mode = 1; | |
829 | ||
830 | ret = of_mpc83xx_spi_get_chipselects(dev); | |
831 | if (ret) | |
832 | goto err; | |
833 | ||
834 | ret = of_address_to_resource(np, 0, &mem); | |
835 | if (ret) | |
836 | goto err; | |
837 | ||
838 | ret = of_irq_to_resource(np, 0, &irq); | |
839 | if (!ret) { | |
840 | ret = -EINVAL; | |
841 | goto err; | |
842 | } | |
843 | ||
844 | master = mpc83xx_spi_probe(dev, &mem, irq.start); | |
845 | if (IS_ERR(master)) { | |
846 | ret = PTR_ERR(master); | |
847 | goto err; | |
848 | } | |
849 | ||
850 | of_register_spi_devices(master, np); | |
851 | ||
852 | return 0; | |
853 | ||
854 | err: | |
855 | of_mpc83xx_spi_free_chipselects(dev); | |
856 | err_clk: | |
857 | kfree(pinfo); | |
858 | return ret; | |
859 | } | |
860 | ||
861 | static int __devexit of_mpc83xx_spi_remove(struct of_device *ofdev) | |
862 | { | |
863 | int ret; | |
864 | ||
865 | ret = mpc83xx_spi_remove(&ofdev->dev); | |
866 | if (ret) | |
867 | return ret; | |
868 | of_mpc83xx_spi_free_chipselects(&ofdev->dev); | |
869 | return 0; | |
870 | } | |
871 | ||
872 | static const struct of_device_id of_mpc83xx_spi_match[] = { | |
873 | { .compatible = "fsl,spi" }, | |
874 | {}, | |
875 | }; | |
876 | MODULE_DEVICE_TABLE(of, of_mpc83xx_spi_match); | |
877 | ||
878 | static struct of_platform_driver of_mpc83xx_spi_driver = { | |
879 | .name = "mpc83xx_spi", | |
880 | .match_table = of_mpc83xx_spi_match, | |
881 | .probe = of_mpc83xx_spi_probe, | |
882 | .remove = __devexit_p(of_mpc83xx_spi_remove), | |
883 | }; | |
884 | ||
885 | #ifdef CONFIG_MPC832x_RDB | |
886 | /* | |
887 | * XXX XXX XXX | |
888 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards | |
889 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
890 | * tree can work with OpenFirmware driver. But for now we support old trees | |
891 | * as well. | |
892 | */ | |
893 | static int __devinit plat_mpc83xx_spi_probe(struct platform_device *pdev) | |
894 | { | |
895 | struct resource *mem; | |
896 | unsigned int irq; | |
897 | struct spi_master *master; | |
898 | ||
899 | if (!pdev->dev.platform_data) | |
900 | return -EINVAL; | |
901 | ||
902 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
903 | if (!mem) | |
904 | return -EINVAL; | |
905 | ||
906 | irq = platform_get_irq(pdev, 0); | |
907 | if (!irq) | |
908 | return -EINVAL; | |
909 | ||
910 | master = mpc83xx_spi_probe(&pdev->dev, mem, irq); | |
911 | if (IS_ERR(master)) | |
912 | return PTR_ERR(master); | |
913 | return 0; | |
914 | } | |
915 | ||
916 | static int __devexit plat_mpc83xx_spi_remove(struct platform_device *pdev) | |
917 | { | |
918 | return mpc83xx_spi_remove(&pdev->dev); | |
919 | } | |
920 | ||
7e38c3c4 | 921 | MODULE_ALIAS("platform:mpc83xx_spi"); |
ccf06998 | 922 | static struct platform_driver mpc83xx_spi_driver = { |
35b4b3c0 AV |
923 | .probe = plat_mpc83xx_spi_probe, |
924 | .remove = __exit_p(plat_mpc83xx_spi_remove), | |
ccf06998 | 925 | .driver = { |
7e38c3c4 KS |
926 | .name = "mpc83xx_spi", |
927 | .owner = THIS_MODULE, | |
ccf06998 KG |
928 | }, |
929 | }; | |
930 | ||
35b4b3c0 AV |
931 | static bool legacy_driver_failed; |
932 | ||
933 | static void __init legacy_driver_register(void) | |
934 | { | |
935 | legacy_driver_failed = platform_driver_register(&mpc83xx_spi_driver); | |
936 | } | |
937 | ||
938 | static void __exit legacy_driver_unregister(void) | |
939 | { | |
940 | if (legacy_driver_failed) | |
941 | return; | |
942 | platform_driver_unregister(&mpc83xx_spi_driver); | |
943 | } | |
944 | #else | |
945 | static void __init legacy_driver_register(void) {} | |
946 | static void __exit legacy_driver_unregister(void) {} | |
947 | #endif /* CONFIG_MPC832x_RDB */ | |
948 | ||
ccf06998 KG |
949 | static int __init mpc83xx_spi_init(void) |
950 | { | |
35b4b3c0 AV |
951 | legacy_driver_register(); |
952 | return of_register_platform_driver(&of_mpc83xx_spi_driver); | |
ccf06998 KG |
953 | } |
954 | ||
955 | static void __exit mpc83xx_spi_exit(void) | |
956 | { | |
35b4b3c0 AV |
957 | of_unregister_platform_driver(&of_mpc83xx_spi_driver); |
958 | legacy_driver_unregister(); | |
ccf06998 KG |
959 | } |
960 | ||
961 | module_init(mpc83xx_spi_init); | |
962 | module_exit(mpc83xx_spi_exit); | |
963 | ||
964 | MODULE_AUTHOR("Kumar Gala"); | |
965 | MODULE_DESCRIPTION("Simple MPC83xx SPI Driver"); | |
966 | MODULE_LICENSE("GPL"); |