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spi/imx: convert driver to use platform ids
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / spi / spi_imx.c
CommitLineData
b5f3294f
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
5a0e3ad6 33#include <linux/slab.h>
b5f3294f
SH		 34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
37
38#include <mach/spi.h>
39
40#define DRIVER_NAME "spi_imx"
41
42#define MXC_CSPIRXDATA 0x00
43#define MXC_CSPITXDATA 0x04
44#define MXC_CSPICTRL 0x08
45#define MXC_CSPIINT 0x0c
46#define MXC_RESET 0x1c
47
ce1807b2
DM		 48#define MX3_CSPISTAT 0x14
49#define MX3_CSPISTAT_RR (1 << 3)
50
b5f3294f
SH		 51/* generic defines to abstract from the different register layouts */
52#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
6cdeb002 55struct spi_imx_config {
b5f3294f
SH		 56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
59 int cs;
60};
61
f4ba6315
UKK		 62enum spi_imx_devtype {
63 SPI_IMX_VER_IMX1,
64 SPI_IMX_VER_0_0,
65 SPI_IMX_VER_0_4,
66 SPI_IMX_VER_0_5,
67 SPI_IMX_VER_0_7,
68 SPI_IMX_VER_AUTODETECT,
69};
70
71struct spi_imx_data;
72
73struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
78};
79
6cdeb002 80struct spi_imx_data {
b5f3294f
SH		 81 struct spi_bitbang bitbang;
82
83 struct completion xfer_done;
84 void *base;
85 int irq;
86 struct clk *clk;
87 unsigned long spi_clk;
88 int *chipselect;
89
90 unsigned int count;
6cdeb002
UKK		 91 void (*tx)(struct spi_imx_data *);
92 void (*rx)(struct spi_imx_data *);
b5f3294f
SH		 93 void *rx_buf;
94 const void *tx_buf;
95 unsigned int txfifo; /* number of words pushed in tx FIFO */
96
f4ba6315 97 struct spi_imx_devtype_data devtype_data;
b5f3294f
SH		 98};
99
100#define MXC_SPI_BUF_RX(type) \
6cdeb002 101static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
b5f3294f 102{ \
6cdeb002 103 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
b5f3294f 104 \
6cdeb002
UKK		 105 if (spi_imx->rx_buf) { \
106 *(type *)spi_imx->rx_buf = val; \
107 spi_imx->rx_buf += sizeof(type); \
b5f3294f
SH		 108 } \
109}
110
111#define MXC_SPI_BUF_TX(type) \
6cdeb002 112static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
b5f3294f
SH		 113{ \
114 type val = 0; \
115 \
6cdeb002
UKK		 116 if (spi_imx->tx_buf) { \
117 val = *(type *)spi_imx->tx_buf; \
118 spi_imx->tx_buf += sizeof(type); \
b5f3294f
SH		 119 } \
120 \
6cdeb002 121 spi_imx->count -= sizeof(type); \
b5f3294f 122 \
6cdeb002 123 writel(val, spi_imx->base + MXC_CSPITXDATA); \
b5f3294f
SH		 124}
125
126MXC_SPI_BUF_RX(u8)
127MXC_SPI_BUF_TX(u8)
128MXC_SPI_BUF_RX(u16)
129MXC_SPI_BUF_TX(u16)
130MXC_SPI_BUF_RX(u32)
131MXC_SPI_BUF_TX(u32)
132
133/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
134 * (which is currently not the case in this driver)
135 */
136static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
137 256, 384, 512, 768, 1024};
138
139/* MX21, MX27 */
6cdeb002 140static unsigned int spi_imx_clkdiv_1(unsigned int fin,
b5f3294f
SH		 141 unsigned int fspi)
142{
143 int i, max;
144
145 if (cpu_is_mx21())
146 max = 18;
147 else
148 max = 16;
149
150 for (i = 2; i < max; i++)
151 if (fspi * mxc_clkdivs[i] >= fin)
152 return i;
153
154 return max;
155}
156
157/* MX1, MX31, MX35 */
6cdeb002 158static unsigned int spi_imx_clkdiv_2(unsigned int fin,
b5f3294f
SH		 159 unsigned int fspi)
160{
161 int i, div = 4;
162
163 for (i = 0; i < 7; i++) {
164 if (fspi * div >= fin)
165 return i;
166 div <<= 1;
167 }
168
169 return 7;
170}
171
172#define MX31_INTREG_TEEN (1 << 0)
173#define MX31_INTREG_RREN (1 << 3)
174
175#define MX31_CSPICTRL_ENABLE (1 << 0)
176#define MX31_CSPICTRL_MASTER (1 << 1)
177#define MX31_CSPICTRL_XCH (1 << 2)
178#define MX31_CSPICTRL_POL (1 << 4)
179#define MX31_CSPICTRL_PHA (1 << 5)
180#define MX31_CSPICTRL_SSCTL (1 << 6)
181#define MX31_CSPICTRL_SSPOL (1 << 7)
182#define MX31_CSPICTRL_BC_SHIFT 8
183#define MX35_CSPICTRL_BL_SHIFT 20
184#define MX31_CSPICTRL_CS_SHIFT 24
185#define MX35_CSPICTRL_CS_SHIFT 12
186#define MX31_CSPICTRL_DR_SHIFT 16
187
188#define MX31_CSPISTATUS 0x14
189#define MX31_STATUS_RR (1 << 3)
190
191/* These functions also work for the i.MX35, but be aware that
192 * the i.MX35 has a slightly different register layout for bits
193 * we do not use here.
194 */
f4ba6315 195static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 196{
197 unsigned int val = 0;
198
199 if (enable & MXC_INT_TE)
200 val |= MX31_INTREG_TEEN;
201 if (enable & MXC_INT_RR)
202 val |= MX31_INTREG_RREN;
203
6cdeb002 204 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 205}
206
f4ba6315 207static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 208{
209 unsigned int reg;
210
6cdeb002 211 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 212 reg |= MX31_CSPICTRL_XCH;
6cdeb002 213 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 214}
215
f4ba6315 216static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
6cdeb002 217 struct spi_imx_config *config)
b5f3294f
SH		 218{
219 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
220
6cdeb002 221 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 222 MX31_CSPICTRL_DR_SHIFT;
223
224 if (cpu_is_mx31())
225 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
87f673e9 226 else if (cpu_is_mx25() || cpu_is_mx35()) {
b5f3294f
SH		 227 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
228 reg |= MX31_CSPICTRL_SSCTL;
229 }
230
231 if (config->mode & SPI_CPHA)
232 reg |= MX31_CSPICTRL_PHA;
233 if (config->mode & SPI_CPOL)
234 reg |= MX31_CSPICTRL_POL;
235 if (config->mode & SPI_CS_HIGH)
236 reg |= MX31_CSPICTRL_SSPOL;
237 if (config->cs < 0) {
238 if (cpu_is_mx31())
239 reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
87f673e9 240 else if (cpu_is_mx25() || cpu_is_mx35())
b5f3294f
SH		 241 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
242 }
243
6cdeb002 244 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 245
246 return 0;
247}
248
f4ba6315 249static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 250{
6cdeb002 251 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
b5f3294f
SH		 252}
253
254#define MX27_INTREG_RR (1 << 4)
255#define MX27_INTREG_TEEN (1 << 9)
256#define MX27_INTREG_RREN (1 << 13)
257
258#define MX27_CSPICTRL_POL (1 << 5)
259#define MX27_CSPICTRL_PHA (1 << 6)
260#define MX27_CSPICTRL_SSPOL (1 << 8)
261#define MX27_CSPICTRL_XCH (1 << 9)
262#define MX27_CSPICTRL_ENABLE (1 << 10)
263#define MX27_CSPICTRL_MASTER (1 << 11)
264#define MX27_CSPICTRL_DR_SHIFT 14
265#define MX27_CSPICTRL_CS_SHIFT 19
266
f4ba6315 267static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 268{
269 unsigned int val = 0;
270
271 if (enable & MXC_INT_TE)
272 val |= MX27_INTREG_TEEN;
273 if (enable & MXC_INT_RR)
274 val |= MX27_INTREG_RREN;
275
6cdeb002 276 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 277}
278
f4ba6315 279static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 280{
281 unsigned int reg;
282
6cdeb002 283 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 284 reg |= MX27_CSPICTRL_XCH;
6cdeb002 285 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 286}
287
f4ba6315 288static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
6cdeb002 289 struct spi_imx_config *config)
b5f3294f
SH		 290{
291 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
292
6cdeb002 293 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 294 MX27_CSPICTRL_DR_SHIFT;
295 reg |= config->bpw - 1;
296
297 if (config->mode & SPI_CPHA)
298 reg |= MX27_CSPICTRL_PHA;
299 if (config->mode & SPI_CPOL)
300 reg |= MX27_CSPICTRL_POL;
301 if (config->mode & SPI_CS_HIGH)
302 reg |= MX27_CSPICTRL_SSPOL;
303 if (config->cs < 0)
304 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
305
6cdeb002 306 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 307
308 return 0;
309}
310
f4ba6315 311static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 312{
6cdeb002 313 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
b5f3294f
SH		 314}
315
316#define MX1_INTREG_RR (1 << 3)
317#define MX1_INTREG_TEEN (1 << 8)
318#define MX1_INTREG_RREN (1 << 11)
319
320#define MX1_CSPICTRL_POL (1 << 4)
321#define MX1_CSPICTRL_PHA (1 << 5)
322#define MX1_CSPICTRL_XCH (1 << 8)
323#define MX1_CSPICTRL_ENABLE (1 << 9)
324#define MX1_CSPICTRL_MASTER (1 << 10)
325#define MX1_CSPICTRL_DR_SHIFT 13
326
f4ba6315 327static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 328{
329 unsigned int val = 0;
330
331 if (enable & MXC_INT_TE)
332 val |= MX1_INTREG_TEEN;
333 if (enable & MXC_INT_RR)
334 val |= MX1_INTREG_RREN;
335
6cdeb002 336 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 337}
338
f4ba6315 339static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 340{
341 unsigned int reg;
342
6cdeb002 343 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 344 reg |= MX1_CSPICTRL_XCH;
6cdeb002 345 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 346}
347
f4ba6315 348static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
6cdeb002 349 struct spi_imx_config *config)
b5f3294f
SH		 350{
351 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
352
6cdeb002 353 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 354 MX1_CSPICTRL_DR_SHIFT;
355 reg |= config->bpw - 1;
356
357 if (config->mode & SPI_CPHA)
358 reg |= MX1_CSPICTRL_PHA;
359 if (config->mode & SPI_CPOL)
360 reg |= MX1_CSPICTRL_POL;
361
6cdeb002 362 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 363
364 return 0;
365}
366
f4ba6315 367static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 368{
6cdeb002 369 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
b5f3294f
SH		 370}
371
f4ba6315
UKK		 372/*
373 * These version numbers are taken from the Freescale driver. Unfortunately it
374 * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
375 */
376static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
377#ifdef CONFIG_SPI_IMX_VER_IMX1
378 [SPI_IMX_VER_IMX1] = {
379 .intctrl = mx1_intctrl,
380 .config = mx1_config,
381 .trigger = mx1_trigger,
382 .rx_available = mx1_rx_available,
383 },
384#endif
385#ifdef CONFIG_SPI_IMX_VER_0_0
386 [SPI_IMX_VER_0_0] = {
387 .intctrl = mx27_intctrl,
388 .config = mx27_config,
389 .trigger = mx27_trigger,
390 .rx_available = mx27_rx_available,
391 },
392#endif
393#ifdef CONFIG_SPI_IMX_VER_0_4
394 [SPI_IMX_VER_0_4] = {
395 .intctrl = mx31_intctrl,
396 .config = mx31_config,
397 .trigger = mx31_trigger,
398 .rx_available = mx31_rx_available,
399 },
400#endif
401#ifdef CONFIG_SPI_IMX_VER_0_7
402 [SPI_IMX_VER_0_7] = {
403 .intctrl = mx31_intctrl,
404 .config = mx31_config,
405 .trigger = mx31_trigger,
406 .rx_available = mx31_rx_available,
407 },
408#endif
409};
410
6cdeb002 411static void spi_imx_chipselect(struct spi_device *spi, int is_active)
b5f3294f 412{
6cdeb002 413 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
6cdeb002 414 int gpio = spi_imx->chipselect[spi->chip_select];
e6a0a8bf
UKK		 415 int active = is_active != BITBANG_CS_INACTIVE;
416 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
b5f3294f 417
e6a0a8bf 418 if (gpio < 0)
b5f3294f 419 return;
b5f3294f 420
e6a0a8bf 421 gpio_set_value(gpio, dev_is_lowactive ^ active);
b5f3294f
SH		 422}
423
6cdeb002 424static void spi_imx_push(struct spi_imx_data *spi_imx)
b5f3294f 425{
6cdeb002
UKK		 426 while (spi_imx->txfifo < 8) {
427 if (!spi_imx->count)
b5f3294f 428 break;
6cdeb002
UKK		 429 spi_imx->tx(spi_imx);
430 spi_imx->txfifo++;
b5f3294f
SH		 431 }
432
f4ba6315 433 spi_imx->devtype_data.trigger(spi_imx);
b5f3294f
SH		 434}
435
6cdeb002 436static irqreturn_t spi_imx_isr(int irq, void *dev_id)
b5f3294f 437{
6cdeb002 438 struct spi_imx_data *spi_imx = dev_id;
b5f3294f 439
f4ba6315 440 while (spi_imx->devtype_data.rx_available(spi_imx)) {
6cdeb002
UKK		 441 spi_imx->rx(spi_imx);
442 spi_imx->txfifo--;
b5f3294f
SH		 443 }
444
6cdeb002
UKK		 445 if (spi_imx->count) {
446 spi_imx_push(spi_imx);
b5f3294f
SH		 447 return IRQ_HANDLED;
448 }
449
6cdeb002 450 if (spi_imx->txfifo) {
b5f3294f
SH		 451 /* No data left to push, but still waiting for rx data,
452 * enable receive data available interrupt.
453 */
f4ba6315
UKK		 454 spi_imx->devtype_data.intctrl(
455 spi_imx, MXC_INT_RR);
b5f3294f
SH		 456 return IRQ_HANDLED;
457 }
458
f4ba6315 459 spi_imx->devtype_data.intctrl(spi_imx, 0);
6cdeb002 460 complete(&spi_imx->xfer_done);
b5f3294f
SH		 461
462 return IRQ_HANDLED;
463}
464
6cdeb002 465static int spi_imx_setupxfer(struct spi_device *spi,
b5f3294f
SH		 466 struct spi_transfer *t)
467{
6cdeb002
UKK		 468 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
469 struct spi_imx_config config;
b5f3294f
SH		 470
471 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
472 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
473 config.mode = spi->mode;
d1c627b5 474 config.cs = spi_imx->chipselect[spi->chip_select];
b5f3294f 475
462d26b5
SH		 476 if (!config.speed_hz)
477 config.speed_hz = spi->max_speed_hz;
478 if (!config.bpw)
479 config.bpw = spi->bits_per_word;
480 if (!config.speed_hz)
481 config.speed_hz = spi->max_speed_hz;
482
e6a0a8bf
UKK		 483 /* Initialize the functions for transfer */
484 if (config.bpw <= 8) {
485 spi_imx->rx = spi_imx_buf_rx_u8;
486 spi_imx->tx = spi_imx_buf_tx_u8;
487 } else if (config.bpw <= 16) {
488 spi_imx->rx = spi_imx_buf_rx_u16;
489 spi_imx->tx = spi_imx_buf_tx_u16;
490 } else if (config.bpw <= 32) {
491 spi_imx->rx = spi_imx_buf_rx_u32;
492 spi_imx->tx = spi_imx_buf_tx_u32;
493 } else
494 BUG();
495
f4ba6315 496 spi_imx->devtype_data.config(spi_imx, &config);
b5f3294f
SH		 497
498 return 0;
499}
500
6cdeb002 501static int spi_imx_transfer(struct spi_device *spi,
b5f3294f
SH		 502 struct spi_transfer *transfer)
503{
6cdeb002 504 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
b5f3294f 505
6cdeb002
UKK		 506 spi_imx->tx_buf = transfer->tx_buf;
507 spi_imx->rx_buf = transfer->rx_buf;
508 spi_imx->count = transfer->len;
509 spi_imx->txfifo = 0;
b5f3294f 510
6cdeb002 511 init_completion(&spi_imx->xfer_done);
b5f3294f 512
6cdeb002 513 spi_imx_push(spi_imx);
b5f3294f 514
f4ba6315 515 spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
b5f3294f 516
6cdeb002 517 wait_for_completion(&spi_imx->xfer_done);
b5f3294f
SH		 518
519 return transfer->len;
520}
521
6cdeb002 522static int spi_imx_setup(struct spi_device *spi)
b5f3294f 523{
6c23e5d4
SH		 524 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
525 int gpio = spi_imx->chipselect[spi->chip_select];
526
f4d4ecfe 527 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
b5f3294f
SH		 528 spi->mode, spi->bits_per_word, spi->max_speed_hz);
529
6c23e5d4
SH		 530 if (gpio >= 0)
531 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
532
6cdeb002 533 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
b5f3294f
SH		 534
535 return 0;
536}
537
6cdeb002 538static void spi_imx_cleanup(struct spi_device *spi)
b5f3294f
SH		 539{
540}
541
f4ba6315
UKK		 542static struct platform_device_id spi_imx_devtype[] = {
543 {
544 .name = DRIVER_NAME,
545 .driver_data = SPI_IMX_VER_AUTODETECT,
546 }, {
547 .name = "imx1-cspi",
548 .driver_data = SPI_IMX_VER_IMX1,
549 }, {
550 .name = "imx21-cspi",
551 .driver_data = SPI_IMX_VER_0_0,
552 }, {
553 .name = "imx25-cspi",
554 .driver_data = SPI_IMX_VER_0_7,
555 }, {
556 .name = "imx27-cspi",
557 .driver_data = SPI_IMX_VER_0_0,
558 }, {
559 .name = "imx31-cspi",
560 .driver_data = SPI_IMX_VER_0_4,
561 }, {
562 .name = "imx35-cspi",
563 .driver_data = SPI_IMX_VER_0_7,
564 }, {
565 /* sentinel */
566 }
567};
568
965346e3 569static int __devinit spi_imx_probe(struct platform_device *pdev)
b5f3294f
SH		 570{
571 struct spi_imx_master *mxc_platform_info;
572 struct spi_master *master;
6cdeb002 573 struct spi_imx_data *spi_imx;
b5f3294f
SH		 574 struct resource *res;
575 int i, ret;
576
980f3bee 577 mxc_platform_info = dev_get_platdata(&pdev->dev);
b5f3294f
SH		 578 if (!mxc_platform_info) {
579 dev_err(&pdev->dev, "can't get the platform data\n");
580 return -EINVAL;
581 }
582
6cdeb002 583 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
b5f3294f
SH		 584 if (!master)
585 return -ENOMEM;
586
587 platform_set_drvdata(pdev, master);
588
589 master->bus_num = pdev->id;
590 master->num_chipselect = mxc_platform_info->num_chipselect;
591
6cdeb002
UKK		 592 spi_imx = spi_master_get_devdata(master);
593 spi_imx->bitbang.master = spi_master_get(master);
594 spi_imx->chipselect = mxc_platform_info->chipselect;
b5f3294f
SH		 595
596 for (i = 0; i < master->num_chipselect; i++) {
6cdeb002 597 if (spi_imx->chipselect[i] < 0)
b5f3294f 598 continue;
6cdeb002 599 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
b5f3294f 600 if (ret) {
bbd050af
JO		 601 while (i > 0) {
602 i--;
6cdeb002 603 if (spi_imx->chipselect[i] >= 0)
bbd050af
JO		 604 gpio_free(spi_imx->chipselect[i]);
605 }
606 dev_err(&pdev->dev, "can't get cs gpios\n");
b5f3294f
SH		 607 goto out_master_put;
608 }
b5f3294f
SH		 609 }
610
6cdeb002
UKK		 611 spi_imx->bitbang.chipselect = spi_imx_chipselect;
612 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
613 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
614 spi_imx->bitbang.master->setup = spi_imx_setup;
615 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
3910f2cf 616 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
b5f3294f 617
6cdeb002 618 init_completion(&spi_imx->xfer_done);
b5f3294f 619
f4ba6315
UKK		 620 if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) {
621 if (cpu_is_mx25() || cpu_is_mx35())
622 spi_imx->devtype_data =
623 spi_imx_devtype_data[SPI_IMX_VER_0_7];
624 else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
625 spi_imx->devtype_data =
626 spi_imx_devtype_data[SPI_IMX_VER_0_4];
627 else if (cpu_is_mx27() || cpu_is_mx21())
628 spi_imx->devtype_data =
629 spi_imx_devtype_data[SPI_IMX_VER_0_0];
630 else if (cpu_is_mx1())
631 spi_imx->devtype_data =
632 spi_imx_devtype_data[SPI_IMX_VER_IMX1];
633 else
634 BUG();
635 } else
636 spi_imx->devtype_data =
637 spi_imx_devtype_data[pdev->id_entry->driver_data];
638
639 if (!spi_imx->devtype_data.intctrl) {
640 dev_err(&pdev->dev, "no support for this device compiled in\n");
641 ret = -ENODEV;
642 goto out_gpio_free;
643 }
644
b5f3294f
SH		 645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646 if (!res) {
647 dev_err(&pdev->dev, "can't get platform resource\n");
648 ret = -ENOMEM;
649 goto out_gpio_free;
650 }
651
652 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
653 dev_err(&pdev->dev, "request_mem_region failed\n");
654 ret = -EBUSY;
655 goto out_gpio_free;
656 }
657
6cdeb002
UKK		 658 spi_imx->base = ioremap(res->start, resource_size(res));
659 if (!spi_imx->base) {
b5f3294f
SH		 660 ret = -EINVAL;
661 goto out_release_mem;
662 }
663
6cdeb002 664 spi_imx->irq = platform_get_irq(pdev, 0);
60f675a1 665 if (spi_imx->irq <= 0) {
b5f3294f
SH		 666 ret = -EINVAL;
667 goto out_iounmap;
668 }
669
6cdeb002 670 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
b5f3294f 671 if (ret) {
6cdeb002 672 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
b5f3294f
SH		 673 goto out_iounmap;
674 }
675
6cdeb002
UKK		 676 spi_imx->clk = clk_get(&pdev->dev, NULL);
677 if (IS_ERR(spi_imx->clk)) {
b5f3294f 678 dev_err(&pdev->dev, "unable to get clock\n");
6cdeb002 679 ret = PTR_ERR(spi_imx->clk);
b5f3294f
SH		 680 goto out_free_irq;
681 }
682
6cdeb002
UKK		 683 clk_enable(spi_imx->clk);
684 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
b5f3294f 685
f30d59c5 686 if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
6cdeb002 687 writel(1, spi_imx->base + MXC_RESET);
b5f3294f 688
ce1807b2 689 /* drain receive buffer */
87f673e9 690 if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
ce1807b2
DM		 691 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
692 readl(spi_imx->base + MXC_CSPIRXDATA);
693
f4ba6315 694 spi_imx->devtype_data.intctrl(spi_imx, 0);
b5f3294f 695
6cdeb002 696 ret = spi_bitbang_start(&spi_imx->bitbang);
b5f3294f
SH		 697 if (ret) {
698 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
699 goto out_clk_put;
700 }
701
702 dev_info(&pdev->dev, "probed\n");
703
704 return ret;
705
706out_clk_put:
6cdeb002
UKK		 707 clk_disable(spi_imx->clk);
708 clk_put(spi_imx->clk);
b5f3294f 709out_free_irq:
6cdeb002 710 free_irq(spi_imx->irq, spi_imx);
b5f3294f 711out_iounmap:
6cdeb002 712 iounmap(spi_imx->base);
b5f3294f
SH		 713out_release_mem:
714 release_mem_region(res->start, resource_size(res));
715out_gpio_free:
716 for (i = 0; i < master->num_chipselect; i++)
6cdeb002
UKK		 717 if (spi_imx->chipselect[i] >= 0)
718 gpio_free(spi_imx->chipselect[i]);
b5f3294f
SH		 719out_master_put:
720 spi_master_put(master);
721 kfree(master);
722 platform_set_drvdata(pdev, NULL);
723 return ret;
724}
725
965346e3 726static int __devexit spi_imx_remove(struct platform_device *pdev)
b5f3294f
SH		 727{
728 struct spi_master *master = platform_get_drvdata(pdev);
729 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6cdeb002 730 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
b5f3294f
SH		 731 int i;
732
6cdeb002 733 spi_bitbang_stop(&spi_imx->bitbang);
b5f3294f 734
6cdeb002
UKK		 735 writel(0, spi_imx->base + MXC_CSPICTRL);
736 clk_disable(spi_imx->clk);
737 clk_put(spi_imx->clk);
738 free_irq(spi_imx->irq, spi_imx);
739 iounmap(spi_imx->base);
b5f3294f
SH		 740
741 for (i = 0; i < master->num_chipselect; i++)
6cdeb002
UKK		 742 if (spi_imx->chipselect[i] >= 0)
743 gpio_free(spi_imx->chipselect[i]);
b5f3294f
SH		 744
745 spi_master_put(master);
746
747 release_mem_region(res->start, resource_size(res));
748
749 platform_set_drvdata(pdev, NULL);
750
751 return 0;
752}
753
6cdeb002 754static struct platform_driver spi_imx_driver = {
b5f3294f
SH		 755 .driver = {
756 .name = DRIVER_NAME,
757 .owner = THIS_MODULE,
758 },
f4ba6315 759 .id_table = spi_imx_devtype,
6cdeb002 760 .probe = spi_imx_probe,
965346e3 761 .remove = __devexit_p(spi_imx_remove),
b5f3294f
SH		 762};
763
6cdeb002 764static int __init spi_imx_init(void)
b5f3294f 765{
6cdeb002 766 return platform_driver_register(&spi_imx_driver);
b5f3294f
SH		 767}
768
6cdeb002 769static void __exit spi_imx_exit(void)
b5f3294f 770{
6cdeb002 771 platform_driver_unregister(&spi_imx_driver);
b5f3294f
SH		 772}
773
6cdeb002
UKK		 774module_init(spi_imx_init);
775module_exit(spi_imx_exit);
b5f3294f
SH		 776
777MODULE_DESCRIPTION("SPI Master Controller driver");
778MODULE_AUTHOR("Sascha Hauer, Pengutronix");
779MODULE_LICENSE("GPL");