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b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/gpio.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/spi/spi.h> | |
34 | #include <linux/spi/spi_bitbang.h> | |
35 | #include <linux/types.h> | |
36 | ||
37 | #include <mach/spi.h> | |
38 | ||
39 | #define DRIVER_NAME "spi_imx" | |
40 | ||
41 | #define MXC_CSPIRXDATA 0x00 | |
42 | #define MXC_CSPITXDATA 0x04 | |
43 | #define MXC_CSPICTRL 0x08 | |
44 | #define MXC_CSPIINT 0x0c | |
45 | #define MXC_RESET 0x1c | |
46 | ||
47 | /* generic defines to abstract from the different register layouts */ | |
48 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
49 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
50 | ||
6cdeb002 | 51 | struct spi_imx_config { |
b5f3294f SH |
52 | unsigned int speed_hz; |
53 | unsigned int bpw; | |
54 | unsigned int mode; | |
55 | int cs; | |
56 | }; | |
57 | ||
6cdeb002 | 58 | struct spi_imx_data { |
b5f3294f SH |
59 | struct spi_bitbang bitbang; |
60 | ||
61 | struct completion xfer_done; | |
62 | void *base; | |
63 | int irq; | |
64 | struct clk *clk; | |
65 | unsigned long spi_clk; | |
66 | int *chipselect; | |
67 | ||
68 | unsigned int count; | |
6cdeb002 UKK |
69 | void (*tx)(struct spi_imx_data *); |
70 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
71 | void *rx_buf; |
72 | const void *tx_buf; | |
73 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
74 | ||
75 | /* SoC specific functions */ | |
6cdeb002 UKK |
76 | void (*intctrl)(struct spi_imx_data *, int); |
77 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); | |
78 | void (*trigger)(struct spi_imx_data *); | |
79 | int (*rx_available)(struct spi_imx_data *); | |
b5f3294f SH |
80 | }; |
81 | ||
82 | #define MXC_SPI_BUF_RX(type) \ | |
6cdeb002 | 83 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 84 | { \ |
6cdeb002 | 85 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 86 | \ |
6cdeb002 UKK |
87 | if (spi_imx->rx_buf) { \ |
88 | *(type *)spi_imx->rx_buf = val; \ | |
89 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
90 | } \ |
91 | } | |
92 | ||
93 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 94 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
95 | { \ |
96 | type val = 0; \ | |
97 | \ | |
6cdeb002 UKK |
98 | if (spi_imx->tx_buf) { \ |
99 | val = *(type *)spi_imx->tx_buf; \ | |
100 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
101 | } \ |
102 | \ | |
6cdeb002 | 103 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 104 | \ |
6cdeb002 | 105 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
106 | } |
107 | ||
108 | MXC_SPI_BUF_RX(u8) | |
109 | MXC_SPI_BUF_TX(u8) | |
110 | MXC_SPI_BUF_RX(u16) | |
111 | MXC_SPI_BUF_TX(u16) | |
112 | MXC_SPI_BUF_RX(u32) | |
113 | MXC_SPI_BUF_TX(u32) | |
114 | ||
115 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
116 | * (which is currently not the case in this driver) | |
117 | */ | |
118 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
119 | 256, 384, 512, 768, 1024}; | |
120 | ||
121 | /* MX21, MX27 */ | |
6cdeb002 | 122 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
b5f3294f SH |
123 | unsigned int fspi) |
124 | { | |
125 | int i, max; | |
126 | ||
127 | if (cpu_is_mx21()) | |
128 | max = 18; | |
129 | else | |
130 | max = 16; | |
131 | ||
132 | for (i = 2; i < max; i++) | |
133 | if (fspi * mxc_clkdivs[i] >= fin) | |
134 | return i; | |
135 | ||
136 | return max; | |
137 | } | |
138 | ||
139 | /* MX1, MX31, MX35 */ | |
6cdeb002 | 140 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
b5f3294f SH |
141 | unsigned int fspi) |
142 | { | |
143 | int i, div = 4; | |
144 | ||
145 | for (i = 0; i < 7; i++) { | |
146 | if (fspi * div >= fin) | |
147 | return i; | |
148 | div <<= 1; | |
149 | } | |
150 | ||
151 | return 7; | |
152 | } | |
153 | ||
154 | #define MX31_INTREG_TEEN (1 << 0) | |
155 | #define MX31_INTREG_RREN (1 << 3) | |
156 | ||
157 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
158 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
159 | #define MX31_CSPICTRL_XCH (1 << 2) | |
160 | #define MX31_CSPICTRL_POL (1 << 4) | |
161 | #define MX31_CSPICTRL_PHA (1 << 5) | |
162 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
163 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
164 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
165 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
166 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
167 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
168 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
169 | ||
170 | #define MX31_CSPISTATUS 0x14 | |
171 | #define MX31_STATUS_RR (1 << 3) | |
172 | ||
173 | /* These functions also work for the i.MX35, but be aware that | |
174 | * the i.MX35 has a slightly different register layout for bits | |
175 | * we do not use here. | |
176 | */ | |
6cdeb002 | 177 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
178 | { |
179 | unsigned int val = 0; | |
180 | ||
181 | if (enable & MXC_INT_TE) | |
182 | val |= MX31_INTREG_TEEN; | |
183 | if (enable & MXC_INT_RR) | |
184 | val |= MX31_INTREG_RREN; | |
185 | ||
6cdeb002 | 186 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
187 | } |
188 | ||
6cdeb002 | 189 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
190 | { |
191 | unsigned int reg; | |
192 | ||
6cdeb002 | 193 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 194 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 195 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
196 | } |
197 | ||
6cdeb002 UKK |
198 | static int mx31_config(struct spi_imx_data *spi_imx, |
199 | struct spi_imx_config *config) | |
b5f3294f SH |
200 | { |
201 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
202 | ||
6cdeb002 | 203 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
204 | MX31_CSPICTRL_DR_SHIFT; |
205 | ||
206 | if (cpu_is_mx31()) | |
207 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; | |
208 | else if (cpu_is_mx35()) { | |
209 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; | |
210 | reg |= MX31_CSPICTRL_SSCTL; | |
211 | } | |
212 | ||
213 | if (config->mode & SPI_CPHA) | |
214 | reg |= MX31_CSPICTRL_PHA; | |
215 | if (config->mode & SPI_CPOL) | |
216 | reg |= MX31_CSPICTRL_POL; | |
217 | if (config->mode & SPI_CS_HIGH) | |
218 | reg |= MX31_CSPICTRL_SSPOL; | |
219 | if (config->cs < 0) { | |
220 | if (cpu_is_mx31()) | |
221 | reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT; | |
222 | else if (cpu_is_mx35()) | |
223 | reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; | |
224 | } | |
225 | ||
6cdeb002 | 226 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
6cdeb002 | 231 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 232 | { |
6cdeb002 | 233 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
234 | } |
235 | ||
236 | #define MX27_INTREG_RR (1 << 4) | |
237 | #define MX27_INTREG_TEEN (1 << 9) | |
238 | #define MX27_INTREG_RREN (1 << 13) | |
239 | ||
240 | #define MX27_CSPICTRL_POL (1 << 5) | |
241 | #define MX27_CSPICTRL_PHA (1 << 6) | |
242 | #define MX27_CSPICTRL_SSPOL (1 << 8) | |
243 | #define MX27_CSPICTRL_XCH (1 << 9) | |
244 | #define MX27_CSPICTRL_ENABLE (1 << 10) | |
245 | #define MX27_CSPICTRL_MASTER (1 << 11) | |
246 | #define MX27_CSPICTRL_DR_SHIFT 14 | |
247 | #define MX27_CSPICTRL_CS_SHIFT 19 | |
248 | ||
6cdeb002 | 249 | static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
250 | { |
251 | unsigned int val = 0; | |
252 | ||
253 | if (enable & MXC_INT_TE) | |
254 | val |= MX27_INTREG_TEEN; | |
255 | if (enable & MXC_INT_RR) | |
256 | val |= MX27_INTREG_RREN; | |
257 | ||
6cdeb002 | 258 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
259 | } |
260 | ||
6cdeb002 | 261 | static void mx27_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
262 | { |
263 | unsigned int reg; | |
264 | ||
6cdeb002 | 265 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 266 | reg |= MX27_CSPICTRL_XCH; |
6cdeb002 | 267 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
268 | } |
269 | ||
6cdeb002 UKK |
270 | static int mx27_config(struct spi_imx_data *spi_imx, |
271 | struct spi_imx_config *config) | |
b5f3294f SH |
272 | { |
273 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; | |
274 | ||
6cdeb002 | 275 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
276 | MX27_CSPICTRL_DR_SHIFT; |
277 | reg |= config->bpw - 1; | |
278 | ||
279 | if (config->mode & SPI_CPHA) | |
280 | reg |= MX27_CSPICTRL_PHA; | |
281 | if (config->mode & SPI_CPOL) | |
282 | reg |= MX27_CSPICTRL_POL; | |
283 | if (config->mode & SPI_CS_HIGH) | |
284 | reg |= MX27_CSPICTRL_SSPOL; | |
285 | if (config->cs < 0) | |
286 | reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; | |
287 | ||
6cdeb002 | 288 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
289 | |
290 | return 0; | |
291 | } | |
292 | ||
6cdeb002 | 293 | static int mx27_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 294 | { |
6cdeb002 | 295 | return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; |
b5f3294f SH |
296 | } |
297 | ||
298 | #define MX1_INTREG_RR (1 << 3) | |
299 | #define MX1_INTREG_TEEN (1 << 8) | |
300 | #define MX1_INTREG_RREN (1 << 11) | |
301 | ||
302 | #define MX1_CSPICTRL_POL (1 << 4) | |
303 | #define MX1_CSPICTRL_PHA (1 << 5) | |
304 | #define MX1_CSPICTRL_XCH (1 << 8) | |
305 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
306 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
307 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
308 | ||
6cdeb002 | 309 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
310 | { |
311 | unsigned int val = 0; | |
312 | ||
313 | if (enable & MXC_INT_TE) | |
314 | val |= MX1_INTREG_TEEN; | |
315 | if (enable & MXC_INT_RR) | |
316 | val |= MX1_INTREG_RREN; | |
317 | ||
6cdeb002 | 318 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
319 | } |
320 | ||
6cdeb002 | 321 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
322 | { |
323 | unsigned int reg; | |
324 | ||
6cdeb002 | 325 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 326 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 327 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
328 | } |
329 | ||
6cdeb002 UKK |
330 | static int mx1_config(struct spi_imx_data *spi_imx, |
331 | struct spi_imx_config *config) | |
b5f3294f SH |
332 | { |
333 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
334 | ||
6cdeb002 | 335 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
336 | MX1_CSPICTRL_DR_SHIFT; |
337 | reg |= config->bpw - 1; | |
338 | ||
339 | if (config->mode & SPI_CPHA) | |
340 | reg |= MX1_CSPICTRL_PHA; | |
341 | if (config->mode & SPI_CPOL) | |
342 | reg |= MX1_CSPICTRL_POL; | |
343 | ||
6cdeb002 | 344 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
345 | |
346 | return 0; | |
347 | } | |
348 | ||
6cdeb002 | 349 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 350 | { |
6cdeb002 | 351 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
352 | } |
353 | ||
6cdeb002 | 354 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 355 | { |
6cdeb002 | 356 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 357 | unsigned int cs = 0; |
6cdeb002 UKK |
358 | int gpio = spi_imx->chipselect[spi->chip_select]; |
359 | struct spi_imx_config config; | |
b5f3294f SH |
360 | |
361 | if (spi->mode & SPI_CS_HIGH) | |
362 | cs = 1; | |
363 | ||
364 | if (is_active == BITBANG_CS_INACTIVE) { | |
365 | if (gpio >= 0) | |
366 | gpio_set_value(gpio, !cs); | |
367 | return; | |
368 | } | |
369 | ||
370 | config.bpw = spi->bits_per_word; | |
371 | config.speed_hz = spi->max_speed_hz; | |
372 | config.mode = spi->mode; | |
6cdeb002 | 373 | config.cs = spi_imx->chipselect[spi->chip_select]; |
b5f3294f | 374 | |
6cdeb002 | 375 | spi_imx->config(spi_imx, &config); |
b5f3294f SH |
376 | |
377 | /* Initialize the functions for transfer */ | |
378 | if (config.bpw <= 8) { | |
6cdeb002 UKK |
379 | spi_imx->rx = spi_imx_buf_rx_u8; |
380 | spi_imx->tx = spi_imx_buf_tx_u8; | |
b5f3294f | 381 | } else if (config.bpw <= 16) { |
6cdeb002 UKK |
382 | spi_imx->rx = spi_imx_buf_rx_u16; |
383 | spi_imx->tx = spi_imx_buf_tx_u16; | |
b5f3294f | 384 | } else if (config.bpw <= 32) { |
6cdeb002 UKK |
385 | spi_imx->rx = spi_imx_buf_rx_u32; |
386 | spi_imx->tx = spi_imx_buf_tx_u32; | |
b5f3294f SH |
387 | } else |
388 | BUG(); | |
389 | ||
390 | if (gpio >= 0) | |
391 | gpio_set_value(gpio, cs); | |
392 | ||
393 | return; | |
394 | } | |
395 | ||
6cdeb002 | 396 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 397 | { |
6cdeb002 UKK |
398 | while (spi_imx->txfifo < 8) { |
399 | if (!spi_imx->count) | |
b5f3294f | 400 | break; |
6cdeb002 UKK |
401 | spi_imx->tx(spi_imx); |
402 | spi_imx->txfifo++; | |
b5f3294f SH |
403 | } |
404 | ||
6cdeb002 | 405 | spi_imx->trigger(spi_imx); |
b5f3294f SH |
406 | } |
407 | ||
6cdeb002 | 408 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 409 | { |
6cdeb002 | 410 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 411 | |
6cdeb002 UKK |
412 | while (spi_imx->rx_available(spi_imx)) { |
413 | spi_imx->rx(spi_imx); | |
414 | spi_imx->txfifo--; | |
b5f3294f SH |
415 | } |
416 | ||
6cdeb002 UKK |
417 | if (spi_imx->count) { |
418 | spi_imx_push(spi_imx); | |
b5f3294f SH |
419 | return IRQ_HANDLED; |
420 | } | |
421 | ||
6cdeb002 | 422 | if (spi_imx->txfifo) { |
b5f3294f SH |
423 | /* No data left to push, but still waiting for rx data, |
424 | * enable receive data available interrupt. | |
425 | */ | |
6cdeb002 | 426 | spi_imx->intctrl(spi_imx, MXC_INT_RR); |
b5f3294f SH |
427 | return IRQ_HANDLED; |
428 | } | |
429 | ||
6cdeb002 UKK |
430 | spi_imx->intctrl(spi_imx, 0); |
431 | complete(&spi_imx->xfer_done); | |
b5f3294f SH |
432 | |
433 | return IRQ_HANDLED; | |
434 | } | |
435 | ||
6cdeb002 | 436 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
437 | struct spi_transfer *t) |
438 | { | |
6cdeb002 UKK |
439 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
440 | struct spi_imx_config config; | |
b5f3294f SH |
441 | |
442 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
443 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
444 | config.mode = spi->mode; | |
445 | ||
462d26b5 SH |
446 | if (!config.speed_hz) |
447 | config.speed_hz = spi->max_speed_hz; | |
448 | if (!config.bpw) | |
449 | config.bpw = spi->bits_per_word; | |
450 | if (!config.speed_hz) | |
451 | config.speed_hz = spi->max_speed_hz; | |
452 | ||
6cdeb002 | 453 | spi_imx->config(spi_imx, &config); |
b5f3294f SH |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
6cdeb002 | 458 | static int spi_imx_transfer(struct spi_device *spi, |
b5f3294f SH |
459 | struct spi_transfer *transfer) |
460 | { | |
6cdeb002 | 461 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 462 | |
6cdeb002 UKK |
463 | spi_imx->tx_buf = transfer->tx_buf; |
464 | spi_imx->rx_buf = transfer->rx_buf; | |
465 | spi_imx->count = transfer->len; | |
466 | spi_imx->txfifo = 0; | |
b5f3294f | 467 | |
6cdeb002 | 468 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 469 | |
6cdeb002 | 470 | spi_imx_push(spi_imx); |
b5f3294f | 471 | |
6cdeb002 | 472 | spi_imx->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 473 | |
6cdeb002 | 474 | wait_for_completion(&spi_imx->xfer_done); |
b5f3294f SH |
475 | |
476 | return transfer->len; | |
477 | } | |
478 | ||
6cdeb002 | 479 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f SH |
480 | { |
481 | if (!spi->bits_per_word) | |
482 | spi->bits_per_word = 8; | |
483 | ||
484 | pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__, | |
485 | spi->mode, spi->bits_per_word, spi->max_speed_hz); | |
486 | ||
6cdeb002 | 487 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
488 | |
489 | return 0; | |
490 | } | |
491 | ||
6cdeb002 | 492 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
493 | { |
494 | } | |
495 | ||
6cdeb002 | 496 | static int __init spi_imx_probe(struct platform_device *pdev) |
b5f3294f SH |
497 | { |
498 | struct spi_imx_master *mxc_platform_info; | |
499 | struct spi_master *master; | |
6cdeb002 | 500 | struct spi_imx_data *spi_imx; |
b5f3294f SH |
501 | struct resource *res; |
502 | int i, ret; | |
503 | ||
504 | mxc_platform_info = (struct spi_imx_master *)pdev->dev.platform_data; | |
505 | if (!mxc_platform_info) { | |
506 | dev_err(&pdev->dev, "can't get the platform data\n"); | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
6cdeb002 | 510 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
b5f3294f SH |
511 | if (!master) |
512 | return -ENOMEM; | |
513 | ||
514 | platform_set_drvdata(pdev, master); | |
515 | ||
516 | master->bus_num = pdev->id; | |
517 | master->num_chipselect = mxc_platform_info->num_chipselect; | |
518 | ||
6cdeb002 UKK |
519 | spi_imx = spi_master_get_devdata(master); |
520 | spi_imx->bitbang.master = spi_master_get(master); | |
521 | spi_imx->chipselect = mxc_platform_info->chipselect; | |
b5f3294f SH |
522 | |
523 | for (i = 0; i < master->num_chipselect; i++) { | |
6cdeb002 | 524 | if (spi_imx->chipselect[i] < 0) |
b5f3294f | 525 | continue; |
6cdeb002 | 526 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
b5f3294f SH |
527 | if (ret) { |
528 | i--; | |
529 | while (i > 0) | |
6cdeb002 UKK |
530 | if (spi_imx->chipselect[i] >= 0) |
531 | gpio_free(spi_imx->chipselect[i--]); | |
b5f3294f SH |
532 | dev_err(&pdev->dev, "can't get cs gpios"); |
533 | goto out_master_put; | |
534 | } | |
6cdeb002 | 535 | gpio_direction_output(spi_imx->chipselect[i], 1); |
b5f3294f SH |
536 | } |
537 | ||
6cdeb002 UKK |
538 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
539 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
540 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
541 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
542 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
b5f3294f | 543 | |
6cdeb002 | 544 | init_completion(&spi_imx->xfer_done); |
b5f3294f SH |
545 | |
546 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
547 | if (!res) { | |
548 | dev_err(&pdev->dev, "can't get platform resource\n"); | |
549 | ret = -ENOMEM; | |
550 | goto out_gpio_free; | |
551 | } | |
552 | ||
553 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
554 | dev_err(&pdev->dev, "request_mem_region failed\n"); | |
555 | ret = -EBUSY; | |
556 | goto out_gpio_free; | |
557 | } | |
558 | ||
6cdeb002 UKK |
559 | spi_imx->base = ioremap(res->start, resource_size(res)); |
560 | if (!spi_imx->base) { | |
b5f3294f SH |
561 | ret = -EINVAL; |
562 | goto out_release_mem; | |
563 | } | |
564 | ||
6cdeb002 UKK |
565 | spi_imx->irq = platform_get_irq(pdev, 0); |
566 | if (!spi_imx->irq) { | |
b5f3294f SH |
567 | ret = -EINVAL; |
568 | goto out_iounmap; | |
569 | } | |
570 | ||
6cdeb002 | 571 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
b5f3294f | 572 | if (ret) { |
6cdeb002 | 573 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
b5f3294f SH |
574 | goto out_iounmap; |
575 | } | |
576 | ||
577 | if (cpu_is_mx31() || cpu_is_mx35()) { | |
6cdeb002 UKK |
578 | spi_imx->intctrl = mx31_intctrl; |
579 | spi_imx->config = mx31_config; | |
580 | spi_imx->trigger = mx31_trigger; | |
581 | spi_imx->rx_available = mx31_rx_available; | |
b5f3294f | 582 | } else if (cpu_is_mx27() || cpu_is_mx21()) { |
6cdeb002 UKK |
583 | spi_imx->intctrl = mx27_intctrl; |
584 | spi_imx->config = mx27_config; | |
585 | spi_imx->trigger = mx27_trigger; | |
586 | spi_imx->rx_available = mx27_rx_available; | |
b5f3294f | 587 | } else if (cpu_is_mx1()) { |
6cdeb002 UKK |
588 | spi_imx->intctrl = mx1_intctrl; |
589 | spi_imx->config = mx1_config; | |
590 | spi_imx->trigger = mx1_trigger; | |
591 | spi_imx->rx_available = mx1_rx_available; | |
b5f3294f SH |
592 | } else |
593 | BUG(); | |
594 | ||
6cdeb002 UKK |
595 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
596 | if (IS_ERR(spi_imx->clk)) { | |
b5f3294f | 597 | dev_err(&pdev->dev, "unable to get clock\n"); |
6cdeb002 | 598 | ret = PTR_ERR(spi_imx->clk); |
b5f3294f SH |
599 | goto out_free_irq; |
600 | } | |
601 | ||
6cdeb002 UKK |
602 | clk_enable(spi_imx->clk); |
603 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); | |
b5f3294f SH |
604 | |
605 | if (!cpu_is_mx31() || !cpu_is_mx35()) | |
6cdeb002 | 606 | writel(1, spi_imx->base + MXC_RESET); |
b5f3294f | 607 | |
6cdeb002 | 608 | spi_imx->intctrl(spi_imx, 0); |
b5f3294f | 609 | |
6cdeb002 | 610 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
611 | if (ret) { |
612 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
613 | goto out_clk_put; | |
614 | } | |
615 | ||
616 | dev_info(&pdev->dev, "probed\n"); | |
617 | ||
618 | return ret; | |
619 | ||
620 | out_clk_put: | |
6cdeb002 UKK |
621 | clk_disable(spi_imx->clk); |
622 | clk_put(spi_imx->clk); | |
b5f3294f | 623 | out_free_irq: |
6cdeb002 | 624 | free_irq(spi_imx->irq, spi_imx); |
b5f3294f | 625 | out_iounmap: |
6cdeb002 | 626 | iounmap(spi_imx->base); |
b5f3294f SH |
627 | out_release_mem: |
628 | release_mem_region(res->start, resource_size(res)); | |
629 | out_gpio_free: | |
630 | for (i = 0; i < master->num_chipselect; i++) | |
6cdeb002 UKK |
631 | if (spi_imx->chipselect[i] >= 0) |
632 | gpio_free(spi_imx->chipselect[i]); | |
b5f3294f SH |
633 | out_master_put: |
634 | spi_master_put(master); | |
635 | kfree(master); | |
636 | platform_set_drvdata(pdev, NULL); | |
637 | return ret; | |
638 | } | |
639 | ||
6cdeb002 | 640 | static int __exit spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
641 | { |
642 | struct spi_master *master = platform_get_drvdata(pdev); | |
643 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6cdeb002 | 644 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f SH |
645 | int i; |
646 | ||
6cdeb002 | 647 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 648 | |
6cdeb002 UKK |
649 | writel(0, spi_imx->base + MXC_CSPICTRL); |
650 | clk_disable(spi_imx->clk); | |
651 | clk_put(spi_imx->clk); | |
652 | free_irq(spi_imx->irq, spi_imx); | |
653 | iounmap(spi_imx->base); | |
b5f3294f SH |
654 | |
655 | for (i = 0; i < master->num_chipselect; i++) | |
6cdeb002 UKK |
656 | if (spi_imx->chipselect[i] >= 0) |
657 | gpio_free(spi_imx->chipselect[i]); | |
b5f3294f SH |
658 | |
659 | spi_master_put(master); | |
660 | ||
661 | release_mem_region(res->start, resource_size(res)); | |
662 | ||
663 | platform_set_drvdata(pdev, NULL); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
6cdeb002 | 668 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
669 | .driver = { |
670 | .name = DRIVER_NAME, | |
671 | .owner = THIS_MODULE, | |
672 | }, | |
6cdeb002 UKK |
673 | .probe = spi_imx_probe, |
674 | .remove = __exit_p(spi_imx_remove), | |
b5f3294f SH |
675 | }; |
676 | ||
6cdeb002 | 677 | static int __init spi_imx_init(void) |
b5f3294f | 678 | { |
6cdeb002 | 679 | return platform_driver_register(&spi_imx_driver); |
b5f3294f SH |
680 | } |
681 | ||
6cdeb002 | 682 | static void __exit spi_imx_exit(void) |
b5f3294f | 683 | { |
6cdeb002 | 684 | platform_driver_unregister(&spi_imx_driver); |
b5f3294f SH |
685 | } |
686 | ||
6cdeb002 UKK |
687 | module_init(spi_imx_init); |
688 | module_exit(spi_imx_exit); | |
b5f3294f SH |
689 | |
690 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
691 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
692 | MODULE_LICENSE("GPL"); |