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9904f22a DB |
1 | /* |
2 | * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/config.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/workqueue.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/platform_device.h> | |
27 | ||
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
30 | ||
31 | ||
32 | /*----------------------------------------------------------------------*/ | |
33 | ||
34 | /* | |
35 | * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support. | |
36 | * Use this for GPIO or shift-register level hardware APIs. | |
37 | * | |
38 | * spi_bitbang_cs is in spi_device->controller_state, which is unavailable | |
39 | * to glue code. These bitbang setup() and cleanup() routines are always | |
40 | * used, though maybe they're called from controller-aware code. | |
41 | * | |
42 | * chipselect() and friends may use use spi_device->controller_data and | |
43 | * controller registers as appropriate. | |
44 | * | |
45 | * | |
46 | * NOTE: SPI controller pins can often be used as GPIO pins instead, | |
47 | * which means you could use a bitbang driver either to get hardware | |
48 | * working quickly, or testing for differences that aren't speed related. | |
49 | */ | |
50 | ||
51 | struct spi_bitbang_cs { | |
52 | unsigned nsecs; /* (clock cycle time)/2 */ | |
53 | u32 (*txrx_word)(struct spi_device *spi, unsigned nsecs, | |
54 | u32 word, u8 bits); | |
55 | unsigned (*txrx_bufs)(struct spi_device *, | |
56 | u32 (*txrx_word)( | |
57 | struct spi_device *spi, | |
58 | unsigned nsecs, | |
59 | u32 word, u8 bits), | |
60 | unsigned, struct spi_transfer *); | |
61 | }; | |
62 | ||
63 | static unsigned bitbang_txrx_8( | |
64 | struct spi_device *spi, | |
65 | u32 (*txrx_word)(struct spi_device *spi, | |
66 | unsigned nsecs, | |
67 | u32 word, u8 bits), | |
68 | unsigned ns, | |
69 | struct spi_transfer *t | |
70 | ) { | |
71 | unsigned bits = spi->bits_per_word; | |
72 | unsigned count = t->len; | |
73 | const u8 *tx = t->tx_buf; | |
74 | u8 *rx = t->rx_buf; | |
75 | ||
76 | while (likely(count > 0)) { | |
77 | u8 word = 0; | |
78 | ||
79 | if (tx) | |
80 | word = *tx++; | |
81 | word = txrx_word(spi, ns, word, bits); | |
82 | if (rx) | |
83 | *rx++ = word; | |
84 | count -= 1; | |
85 | } | |
86 | return t->len - count; | |
87 | } | |
88 | ||
89 | static unsigned bitbang_txrx_16( | |
90 | struct spi_device *spi, | |
91 | u32 (*txrx_word)(struct spi_device *spi, | |
92 | unsigned nsecs, | |
93 | u32 word, u8 bits), | |
94 | unsigned ns, | |
95 | struct spi_transfer *t | |
96 | ) { | |
97 | unsigned bits = spi->bits_per_word; | |
98 | unsigned count = t->len; | |
99 | const u16 *tx = t->tx_buf; | |
100 | u16 *rx = t->rx_buf; | |
101 | ||
102 | while (likely(count > 1)) { | |
103 | u16 word = 0; | |
104 | ||
105 | if (tx) | |
106 | word = *tx++; | |
107 | word = txrx_word(spi, ns, word, bits); | |
108 | if (rx) | |
109 | *rx++ = word; | |
110 | count -= 2; | |
111 | } | |
112 | return t->len - count; | |
113 | } | |
114 | ||
115 | static unsigned bitbang_txrx_32( | |
116 | struct spi_device *spi, | |
117 | u32 (*txrx_word)(struct spi_device *spi, | |
118 | unsigned nsecs, | |
119 | u32 word, u8 bits), | |
120 | unsigned ns, | |
121 | struct spi_transfer *t | |
122 | ) { | |
123 | unsigned bits = spi->bits_per_word; | |
124 | unsigned count = t->len; | |
125 | const u32 *tx = t->tx_buf; | |
126 | u32 *rx = t->rx_buf; | |
127 | ||
128 | while (likely(count > 3)) { | |
129 | u32 word = 0; | |
130 | ||
131 | if (tx) | |
132 | word = *tx++; | |
133 | word = txrx_word(spi, ns, word, bits); | |
134 | if (rx) | |
135 | *rx++ = word; | |
136 | count -= 4; | |
137 | } | |
138 | return t->len - count; | |
139 | } | |
140 | ||
4cff33f9 ID |
141 | static int |
142 | bitbang_transfer_setup(struct spi_device *spi, struct spi_transfer *t) | |
143 | { | |
144 | struct spi_bitbang_cs *cs = spi->controller_state; | |
145 | u8 bits_per_word; | |
146 | u32 hz; | |
147 | ||
148 | if (t) { | |
149 | bits_per_word = t->bits_per_word; | |
150 | hz = t->speed_hz; | |
151 | } else { | |
152 | bits_per_word = 0; | |
153 | hz = 0; | |
154 | } | |
155 | ||
156 | /* spi_transfer level calls that work per-word */ | |
157 | if (!bits_per_word) | |
158 | bits_per_word = spi->bits_per_word; | |
159 | if (bits_per_word <= 8) | |
160 | cs->txrx_bufs = bitbang_txrx_8; | |
161 | else if (bits_per_word <= 16) | |
162 | cs->txrx_bufs = bitbang_txrx_16; | |
163 | else if (bits_per_word <= 32) | |
164 | cs->txrx_bufs = bitbang_txrx_32; | |
165 | else | |
166 | return -EINVAL; | |
167 | ||
168 | /* nsecs = (clock period)/2 */ | |
169 | if (!hz) | |
170 | hz = spi->max_speed_hz; | |
171 | cs->nsecs = (1000000000/2) / hz; | |
172 | if (cs->nsecs > MAX_UDELAY_MS * 1000) | |
173 | return -EINVAL; | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
9904f22a DB |
178 | /** |
179 | * spi_bitbang_setup - default setup for per-word I/O loops | |
180 | */ | |
181 | int spi_bitbang_setup(struct spi_device *spi) | |
182 | { | |
183 | struct spi_bitbang_cs *cs = spi->controller_state; | |
184 | struct spi_bitbang *bitbang; | |
4cff33f9 | 185 | int retval; |
9904f22a | 186 | |
8275c642 VW |
187 | if (!spi->max_speed_hz) |
188 | return -EINVAL; | |
189 | ||
9904f22a DB |
190 | if (!cs) { |
191 | cs = kzalloc(sizeof *cs, SLAB_KERNEL); | |
192 | if (!cs) | |
193 | return -ENOMEM; | |
194 | spi->controller_state = cs; | |
195 | } | |
196 | bitbang = spi_master_get_devdata(spi->master); | |
197 | ||
198 | if (!spi->bits_per_word) | |
199 | spi->bits_per_word = 8; | |
200 | ||
9904f22a DB |
201 | /* per-word shift register access, in hardware or bitbanging */ |
202 | cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)]; | |
203 | if (!cs->txrx_word) | |
204 | return -EINVAL; | |
205 | ||
4cff33f9 ID |
206 | retval = bitbang_transfer_setup(spi, NULL); |
207 | if (retval < 0) | |
208 | return retval; | |
9904f22a DB |
209 | |
210 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n", | |
211 | __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA), | |
212 | spi->bits_per_word, 2 * cs->nsecs); | |
213 | ||
214 | /* NOTE we _need_ to call chipselect() early, ideally with adapter | |
215 | * setup, unless the hardware defaults cooperate to avoid confusion | |
216 | * between normal (active low) and inverted chipselects. | |
217 | */ | |
218 | ||
219 | /* deselect chip (low or high) */ | |
220 | spin_lock(&bitbang->lock); | |
221 | if (!bitbang->busy) { | |
8275c642 | 222 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); |
9904f22a DB |
223 | ndelay(cs->nsecs); |
224 | } | |
225 | spin_unlock(&bitbang->lock); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | EXPORT_SYMBOL_GPL(spi_bitbang_setup); | |
230 | ||
231 | /** | |
232 | * spi_bitbang_cleanup - default cleanup for per-word I/O loops | |
233 | */ | |
234 | void spi_bitbang_cleanup(const struct spi_device *spi) | |
235 | { | |
236 | kfree(spi->controller_state); | |
237 | } | |
238 | EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); | |
239 | ||
240 | static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) | |
241 | { | |
242 | struct spi_bitbang_cs *cs = spi->controller_state; | |
243 | unsigned nsecs = cs->nsecs; | |
244 | ||
245 | return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); | |
246 | } | |
247 | ||
248 | /*----------------------------------------------------------------------*/ | |
249 | ||
250 | /* | |
251 | * SECOND PART ... simple transfer queue runner. | |
252 | * | |
253 | * This costs a task context per controller, running the queue by | |
254 | * performing each transfer in sequence. Smarter hardware can queue | |
255 | * several DMA transfers at once, and process several controller queues | |
256 | * in parallel; this driver doesn't match such hardware very well. | |
257 | * | |
258 | * Drivers can provide word-at-a-time i/o primitives, or provide | |
259 | * transfer-at-a-time ones to leverage dma or fifo hardware. | |
260 | */ | |
261 | static void bitbang_work(void *_bitbang) | |
262 | { | |
263 | struct spi_bitbang *bitbang = _bitbang; | |
264 | unsigned long flags; | |
265 | ||
266 | spin_lock_irqsave(&bitbang->lock, flags); | |
267 | bitbang->busy = 1; | |
268 | while (!list_empty(&bitbang->queue)) { | |
269 | struct spi_message *m; | |
270 | struct spi_device *spi; | |
271 | unsigned nsecs; | |
8275c642 | 272 | struct spi_transfer *t = NULL; |
9904f22a | 273 | unsigned tmp; |
8275c642 | 274 | unsigned cs_change; |
9904f22a | 275 | int status; |
4cff33f9 ID |
276 | int (*setup_transfer)(struct spi_device *, |
277 | struct spi_transfer *); | |
9904f22a DB |
278 | |
279 | m = container_of(bitbang->queue.next, struct spi_message, | |
280 | queue); | |
281 | list_del_init(&m->queue); | |
282 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
283 | ||
8275c642 VW |
284 | /* FIXME this is made-up ... the correct value is known to |
285 | * word-at-a-time bitbang code, and presumably chipselect() | |
286 | * should enforce these requirements too? | |
287 | */ | |
288 | nsecs = 100; | |
9904f22a DB |
289 | |
290 | spi = m->spi; | |
9904f22a | 291 | tmp = 0; |
8275c642 | 292 | cs_change = 1; |
9904f22a | 293 | status = 0; |
4cff33f9 | 294 | setup_transfer = NULL; |
9904f22a | 295 | |
8275c642 | 296 | list_for_each_entry (t, &m->transfers, transfer_list) { |
9904f22a DB |
297 | if (bitbang->shutdown) { |
298 | status = -ESHUTDOWN; | |
299 | break; | |
300 | } | |
301 | ||
4cff33f9 ID |
302 | /* override or restore speed and wordsize */ |
303 | if (t->speed_hz || t->bits_per_word) { | |
304 | setup_transfer = bitbang->setup_transfer; | |
305 | if (!setup_transfer) { | |
306 | status = -ENOPROTOOPT; | |
307 | break; | |
308 | } | |
309 | } | |
310 | if (setup_transfer) { | |
311 | status = setup_transfer(spi, t); | |
312 | if (status < 0) | |
313 | break; | |
314 | } | |
315 | ||
8275c642 VW |
316 | /* set up default clock polarity, and activate chip; |
317 | * this implicitly updates clock and spi modes as | |
318 | * previously recorded for this device via setup(). | |
319 | * (and also deselects any other chip that might be | |
320 | * selected ...) | |
321 | */ | |
322 | if (cs_change) { | |
323 | bitbang->chipselect(spi, BITBANG_CS_ACTIVE); | |
9904f22a DB |
324 | ndelay(nsecs); |
325 | } | |
8275c642 | 326 | cs_change = t->cs_change; |
9904f22a DB |
327 | if (!t->tx_buf && !t->rx_buf && t->len) { |
328 | status = -EINVAL; | |
329 | break; | |
330 | } | |
331 | ||
8275c642 VW |
332 | /* transfer data. the lower level code handles any |
333 | * new dma mappings it needs. our caller always gave | |
334 | * us dma-safe buffers. | |
335 | */ | |
9904f22a | 336 | if (t->len) { |
8275c642 VW |
337 | /* REVISIT dma API still needs a designated |
338 | * DMA_ADDR_INVALID; ~0 might be better. | |
9904f22a | 339 | */ |
8275c642 VW |
340 | if (!m->is_dma_mapped) |
341 | t->rx_dma = t->tx_dma = 0; | |
9904f22a DB |
342 | status = bitbang->txrx_bufs(spi, t); |
343 | } | |
344 | if (status != t->len) { | |
345 | if (status > 0) | |
346 | status = -EMSGSIZE; | |
347 | break; | |
348 | } | |
349 | m->actual_length += status; | |
350 | status = 0; | |
351 | ||
352 | /* protocol tweaks before next transfer */ | |
353 | if (t->delay_usecs) | |
354 | udelay(t->delay_usecs); | |
355 | ||
8275c642 | 356 | if (!cs_change) |
9904f22a | 357 | continue; |
8275c642 VW |
358 | if (t->transfer_list.next == &m->transfers) |
359 | break; | |
9904f22a | 360 | |
8275c642 VW |
361 | /* sometimes a short mid-message deselect of the chip |
362 | * may be needed to terminate a mode or command | |
363 | */ | |
364 | ndelay(nsecs); | |
365 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
366 | ndelay(nsecs); | |
9904f22a DB |
367 | } |
368 | ||
9904f22a DB |
369 | m->status = status; |
370 | m->complete(m->context); | |
371 | ||
4cff33f9 ID |
372 | /* restore speed and wordsize */ |
373 | if (setup_transfer) | |
374 | setup_transfer(spi, NULL); | |
375 | ||
8275c642 VW |
376 | /* normally deactivate chipselect ... unless no error and |
377 | * cs_change has hinted that the next message will probably | |
378 | * be for this chip too. | |
379 | */ | |
380 | if (!(status == 0 && cs_change)) { | |
381 | ndelay(nsecs); | |
382 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
383 | ndelay(nsecs); | |
384 | } | |
9904f22a DB |
385 | |
386 | spin_lock_irqsave(&bitbang->lock, flags); | |
387 | } | |
388 | bitbang->busy = 0; | |
389 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
390 | } | |
391 | ||
392 | /** | |
393 | * spi_bitbang_transfer - default submit to transfer queue | |
394 | */ | |
395 | int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m) | |
396 | { | |
397 | struct spi_bitbang *bitbang; | |
398 | unsigned long flags; | |
399 | ||
400 | m->actual_length = 0; | |
401 | m->status = -EINPROGRESS; | |
402 | ||
403 | bitbang = spi_master_get_devdata(spi->master); | |
404 | if (bitbang->shutdown) | |
405 | return -ESHUTDOWN; | |
406 | ||
407 | spin_lock_irqsave(&bitbang->lock, flags); | |
408 | list_add_tail(&m->queue, &bitbang->queue); | |
409 | queue_work(bitbang->workqueue, &bitbang->work); | |
410 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(spi_bitbang_transfer); | |
415 | ||
416 | /*----------------------------------------------------------------------*/ | |
417 | ||
418 | /** | |
419 | * spi_bitbang_start - start up a polled/bitbanging SPI master driver | |
420 | * @bitbang: driver handle | |
421 | * | |
422 | * Caller should have zero-initialized all parts of the structure, and then | |
423 | * provided callbacks for chip selection and I/O loops. If the master has | |
424 | * a transfer method, its final step should call spi_bitbang_transfer; or, | |
425 | * that's the default if the transfer routine is not initialized. It should | |
426 | * also set up the bus number and number of chipselects. | |
427 | * | |
428 | * For i/o loops, provide callbacks either per-word (for bitbanging, or for | |
429 | * hardware that basically exposes a shift register) or per-spi_transfer | |
430 | * (which takes better advantage of hardware like fifos or DMA engines). | |
431 | * | |
432 | * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup and | |
433 | * spi_bitbang_cleanup to handle those spi master methods. Those methods are | |
434 | * the defaults if the bitbang->txrx_bufs routine isn't initialized. | |
435 | * | |
436 | * This routine registers the spi_master, which will process requests in a | |
437 | * dedicated task, keeping IRQs unblocked most of the time. To stop | |
438 | * processing those requests, call spi_bitbang_stop(). | |
439 | */ | |
440 | int spi_bitbang_start(struct spi_bitbang *bitbang) | |
441 | { | |
442 | int status; | |
443 | ||
444 | if (!bitbang->master || !bitbang->chipselect) | |
445 | return -EINVAL; | |
446 | ||
447 | INIT_WORK(&bitbang->work, bitbang_work, bitbang); | |
448 | spin_lock_init(&bitbang->lock); | |
449 | INIT_LIST_HEAD(&bitbang->queue); | |
450 | ||
451 | if (!bitbang->master->transfer) | |
452 | bitbang->master->transfer = spi_bitbang_transfer; | |
453 | if (!bitbang->txrx_bufs) { | |
454 | bitbang->use_dma = 0; | |
455 | bitbang->txrx_bufs = spi_bitbang_bufs; | |
456 | if (!bitbang->master->setup) { | |
4cff33f9 | 457 | bitbang->setup_transfer = bitbang_transfer_setup; |
9904f22a DB |
458 | bitbang->master->setup = spi_bitbang_setup; |
459 | bitbang->master->cleanup = spi_bitbang_cleanup; | |
460 | } | |
461 | } else if (!bitbang->master->setup) | |
462 | return -EINVAL; | |
463 | ||
464 | /* this task is the only thing to touch the SPI bits */ | |
465 | bitbang->busy = 0; | |
466 | bitbang->workqueue = create_singlethread_workqueue( | |
467 | bitbang->master->cdev.dev->bus_id); | |
468 | if (bitbang->workqueue == NULL) { | |
469 | status = -EBUSY; | |
470 | goto err1; | |
471 | } | |
472 | ||
473 | /* driver may get busy before register() returns, especially | |
474 | * if someone registered boardinfo for devices | |
475 | */ | |
476 | status = spi_register_master(bitbang->master); | |
477 | if (status < 0) | |
478 | goto err2; | |
479 | ||
480 | return status; | |
481 | ||
482 | err2: | |
483 | destroy_workqueue(bitbang->workqueue); | |
484 | err1: | |
485 | return status; | |
486 | } | |
487 | EXPORT_SYMBOL_GPL(spi_bitbang_start); | |
488 | ||
489 | /** | |
490 | * spi_bitbang_stop - stops the task providing spi communication | |
491 | */ | |
492 | int spi_bitbang_stop(struct spi_bitbang *bitbang) | |
493 | { | |
494 | unsigned limit = 500; | |
495 | ||
496 | spin_lock_irq(&bitbang->lock); | |
497 | bitbang->shutdown = 0; | |
498 | while (!list_empty(&bitbang->queue) && limit--) { | |
499 | spin_unlock_irq(&bitbang->lock); | |
500 | ||
501 | dev_dbg(bitbang->master->cdev.dev, "wait for queue\n"); | |
502 | msleep(10); | |
503 | ||
504 | spin_lock_irq(&bitbang->lock); | |
505 | } | |
506 | spin_unlock_irq(&bitbang->lock); | |
507 | if (!list_empty(&bitbang->queue)) { | |
508 | dev_err(bitbang->master->cdev.dev, "queue didn't empty\n"); | |
509 | return -EBUSY; | |
510 | } | |
511 | ||
512 | destroy_workqueue(bitbang->workqueue); | |
513 | ||
514 | spi_unregister_master(bitbang->master); | |
515 | ||
516 | return 0; | |
517 | } | |
518 | EXPORT_SYMBOL_GPL(spi_bitbang_stop); | |
519 | ||
520 | MODULE_LICENSE("GPL"); | |
521 |