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SIGIO-driven I/O with inotify queues
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
131b17d4
BW		 2 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
a5f6abd4 7 *
131b17d4
BW		 8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
a5f6abd4
WB		 11 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
131b17d4 15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
a32c691d
BW		 16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
a5f6abd4 18 *
131b17d4 19 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4
WB		 20 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37#include <linux/init.h>
38#include <linux/module.h>
131b17d4 39#include <linux/delay.h>
a5f6abd4 40#include <linux/device.h>
131b17d4 41#include <linux/io.h>
a5f6abd4 42#include <linux/ioport.h>
131b17d4 43#include <linux/irq.h>
a5f6abd4
WB		 44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/spi/spi.h>
49#include <linux/workqueue.h>
a5f6abd4 50
a5f6abd4 51#include <asm/dma.h>
131b17d4 52#include <asm/portmux.h>
a5f6abd4
WB		 53#include <asm/bfin5xx_spi.h>
54
a32c691d
BW		 55#define DRV_NAME "bfin-spi"
56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 57#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 58#define DRV_VERSION "1.0"
59
60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 62MODULE_LICENSE("GPL");
63
bb90eb00 64#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 65
bb90eb00
BW		 66#define START_STATE ((void *)0)
67#define RUNNING_STATE ((void *)1)
68#define DONE_STATE ((void *)2)
69#define ERROR_STATE ((void *)-1)
70#define QUEUE_RUNNING 0
71#define QUEUE_STOPPED 1
a5f6abd4
WB		 72
73struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
bb90eb00 80 /* Regs base of SPI controller */
f452126c 81 void __iomem *regs_base;
bb90eb00 82
003d9226
BW		 83 /* Pin request list */
84 u16 *pin_req;
85
a5f6abd4
WB		 86 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info;
88
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
92 spinlock_t lock;
93 struct list_head queue;
94 int busy;
95 int run;
96
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
99
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
104 size_t len_in_bytes;
105 size_t len;
106 void *tx;
107 void *tx_end;
108 void *rx;
109 void *rx_end;
bb90eb00
BW		 110
111 /* DMA stuffs */
112 int dma_channel;
a5f6abd4 113 int dma_mapped;
bb90eb00 114 int dma_requested;
a5f6abd4
WB		 115 dma_addr_t rx_dma;
116 dma_addr_t tx_dma;
bb90eb00 117
a5f6abd4
WB		 118 size_t rx_map_len;
119 size_t tx_map_len;
120 u8 n_bytes;
fad91c89 121 int cs_change;
a5f6abd4
WB		 122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
125};
126
127struct chip_data {
128 u16 ctl_reg;
129 u16 baud;
130 u16 flag;
131
132 u8 chip_select_num;
133 u8 n_bytes;
88b40369 134 u8 width; /* 0 or 1 */
a5f6abd4
WB		 135 u8 enable_dma;
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
62310e51 138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
142};
143
bb90eb00
BW		 144#define DEFINE_SPI_REG(reg, off) \
145static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150DEFINE_SPI_REG(CTRL, 0x00)
151DEFINE_SPI_REG(FLAG, 0x04)
152DEFINE_SPI_REG(STAT, 0x08)
153DEFINE_SPI_REG(TDBR, 0x0C)
154DEFINE_SPI_REG(RDBR, 0x10)
155DEFINE_SPI_REG(BAUD, 0x14)
156DEFINE_SPI_REG(SHAW, 0x18)
157
88b40369 158static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 159{
160 u16 cr;
161
bb90eb00
BW		 162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 164}
165
88b40369 166static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 167{
168 u16 cr;
169
bb90eb00
BW		 170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 172}
173
174/* Caculate the SPI_BAUD register value based on input HZ */
175static u16 hz_to_spi_baud(u32 speed_hz)
176{
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
179
180 if ((sclk % (2 * speed_hz)) > 0)
181 spi_baud++;
182
a5f6abd4
WB		 183 return spi_baud;
184}
185
186static int flush(struct driver_data *drv_data)
187{
188 unsigned long limit = loops_per_jiffy << 1;
189
190 /* wait for stop and clear stat */
bb90eb00 191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 192 cpu_relax();
a5f6abd4 193
bb90eb00 194 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 195
196 return limit;
197}
198
fad91c89 199/* Chip select operation functions for cs_change flag */
bb90eb00 200static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 201{
bb90eb00 202 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
bb90eb00 207 write_FLAG(drv_data, flag);
fad91c89
BW		 208}
209
bb90eb00 210static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 211{
bb90eb00 212 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 213
214 flag |= (chip->flag << 8);
215
bb90eb00 216 write_FLAG(drv_data, flag);
62310e51
BW		 217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
fad91c89
BW		 221}
222
7c4ef094 223#define MAX_SPI_SSEL 7
5fec5b5a 224
a5f6abd4 225/* stop controller and re-config current chip*/
5fec5b5a 226static int restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 227{
228 struct chip_data *chip = drv_data->cur_chip;
5fec5b5a 229 int ret = 0;
12e17c42 230
a5f6abd4 231 /* Clear status and disable clock */
bb90eb00 232 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 233 bfin_spi_disable(drv_data);
88b40369 234 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 235
5fec5b5a 236 /* Load the registers */
bb90eb00 237 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 238 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 239
240 bfin_spi_enable(drv_data);
07612e5f 241 cs_active(drv_data, chip);
5fec5b5a 242
5fec5b5a
BW		 243 if (ret)
244 dev_dbg(&drv_data->pdev->dev,
245 ": request chip select number %d failed\n",
246 chip->chip_select_num);
247
248 return ret;
a5f6abd4
WB		 249}
250
251/* used to kick off transfer in rx mode */
bb90eb00 252static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 253{
254 unsigned short tmp;
bb90eb00 255 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 256 return tmp;
257}
258
259static void null_writer(struct driver_data *drv_data)
260{
261 u8 n_bytes = drv_data->n_bytes;
262
263 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 264 write_TDBR(drv_data, 0);
265 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 266 cpu_relax();
a5f6abd4
WB		 267 drv_data->tx += n_bytes;
268 }
269}
270
271static void null_reader(struct driver_data *drv_data)
272{
273 u8 n_bytes = drv_data->n_bytes;
bb90eb00 274 dummy_read(drv_data);
a5f6abd4
WB		 275
276 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 277 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 278 cpu_relax();
bb90eb00 279 dummy_read(drv_data);
a5f6abd4
WB		 280 drv_data->rx += n_bytes;
281 }
282}
283
284static void u8_writer(struct driver_data *drv_data)
285{
131b17d4 286 dev_dbg(&drv_data->pdev->dev,
bb90eb00 287 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 288
3f479a65 289 /* poll for SPI completion before start */
bb90eb00 290 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 291 cpu_relax();
3f479a65 292
a5f6abd4 293 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 294 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
295 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 296 cpu_relax();
a5f6abd4
WB		 297 ++drv_data->tx;
298 }
a5f6abd4
WB		 299}
300
301static void u8_cs_chg_writer(struct driver_data *drv_data)
302{
303 struct chip_data *chip = drv_data->cur_chip;
304
3f479a65 305 /* poll for SPI completion before start */
bb90eb00 306 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 307 cpu_relax();
3f479a65 308
a5f6abd4 309 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 310 cs_active(drv_data, chip);
a5f6abd4 311
bb90eb00
BW		 312 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
313 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 314 cpu_relax();
62310e51 315
bb90eb00 316 cs_deactive(drv_data, chip);
5fec5b5a 317
a5f6abd4
WB		 318 ++drv_data->tx;
319 }
a5f6abd4
WB		 320}
321
322static void u8_reader(struct driver_data *drv_data)
323{
131b17d4 324 dev_dbg(&drv_data->pdev->dev,
bb90eb00 325 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 326
3f479a65 327 /* poll for SPI completion before start */
bb90eb00 328 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 329 cpu_relax();
3f479a65 330
a5f6abd4 331 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 332 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 333
bb90eb00 334 dummy_read(drv_data);
cc487e73 335
a5f6abd4 336 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 337 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 338 cpu_relax();
bb90eb00 339 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 340 ++drv_data->rx;
341 }
342
bb90eb00 343 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 344 cpu_relax();
bb90eb00 345 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 346 ++drv_data->rx;
347}
348
349static void u8_cs_chg_reader(struct driver_data *drv_data)
350{
351 struct chip_data *chip = drv_data->cur_chip;
352
3f479a65 353 /* poll for SPI completion before start */
bb90eb00 354 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 355 cpu_relax();
3f479a65 356
cc487e73 357 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 358 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 359
bb90eb00
BW		 360 cs_active(drv_data, chip);
361 dummy_read(drv_data);
cc487e73
SZ		 362
363 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 364 cs_deactive(drv_data, chip);
5fec5b5a 365
bb90eb00 366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 367 cpu_relax();
bb90eb00
BW		 368 cs_active(drv_data, chip);
369 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 370 ++drv_data->rx;
371 }
bb90eb00 372 cs_deactive(drv_data, chip);
5fec5b5a 373
bb90eb00 374 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 375 cpu_relax();
bb90eb00 376 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 377 ++drv_data->rx;
a5f6abd4
WB		 378}
379
380static void u8_duplex(struct driver_data *drv_data)
381{
3f479a65 382 /* poll for SPI completion before start */
bb90eb00 383 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 384 cpu_relax();
3f479a65 385
a5f6abd4
WB		 386 /* in duplex mode, clk is triggered by writing of TDBR */
387 while (drv_data->rx < drv_data->rx_end) {
bb90eb00
BW		 388 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
389 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 390 cpu_relax();
bb90eb00 391 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 392 cpu_relax();
bb90eb00 393 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 394 ++drv_data->rx;
395 ++drv_data->tx;
396 }
397}
398
399static void u8_cs_chg_duplex(struct driver_data *drv_data)
400{
401 struct chip_data *chip = drv_data->cur_chip;
402
3f479a65 403 /* poll for SPI completion before start */
bb90eb00 404 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 405 cpu_relax();
3f479a65 406
a5f6abd4 407 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 408 cs_active(drv_data, chip);
5fec5b5a 409
bb90eb00
BW		 410 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
411 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 412 cpu_relax();
bb90eb00 413 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 414 cpu_relax();
bb90eb00 415 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 416
bb90eb00 417 cs_deactive(drv_data, chip);
5fec5b5a 418
a5f6abd4
WB		 419 ++drv_data->rx;
420 ++drv_data->tx;
421 }
a5f6abd4
WB		 422}
423
424static void u16_writer(struct driver_data *drv_data)
425{
131b17d4 426 dev_dbg(&drv_data->pdev->dev,
bb90eb00 427 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 428
3f479a65 429 /* poll for SPI completion before start */
bb90eb00 430 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 431 cpu_relax();
3f479a65 432
a5f6abd4 433 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 434 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
435 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 436 cpu_relax();
a5f6abd4
WB		 437 drv_data->tx += 2;
438 }
a5f6abd4
WB		 439}
440
441static void u16_cs_chg_writer(struct driver_data *drv_data)
442{
443 struct chip_data *chip = drv_data->cur_chip;
444
3f479a65 445 /* poll for SPI completion before start */
bb90eb00 446 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 447 cpu_relax();
3f479a65 448
a5f6abd4 449 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 450 cs_active(drv_data, chip);
a5f6abd4 451
bb90eb00
BW		 452 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
453 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 454 cpu_relax();
62310e51 455
bb90eb00 456 cs_deactive(drv_data, chip);
5fec5b5a 457
a5f6abd4
WB		 458 drv_data->tx += 2;
459 }
a5f6abd4
WB		 460}
461
462static void u16_reader(struct driver_data *drv_data)
463{
88b40369 464 dev_dbg(&drv_data->pdev->dev,
bb90eb00 465 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 466
3f479a65 467 /* poll for SPI completion before start */
bb90eb00 468 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 469 cpu_relax();
3f479a65 470
cc487e73 471 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 472 write_TDBR(drv_data, 0xFFFF);
cc487e73 473
bb90eb00 474 dummy_read(drv_data);
a5f6abd4
WB		 475
476 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 477 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 478 cpu_relax();
bb90eb00 479 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 480 drv_data->rx += 2;
481 }
482
bb90eb00 483 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 484 cpu_relax();
bb90eb00 485 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 486 drv_data->rx += 2;
487}
488
489static void u16_cs_chg_reader(struct driver_data *drv_data)
490{
491 struct chip_data *chip = drv_data->cur_chip;
492
3f479a65 493 /* poll for SPI completion before start */
bb90eb00 494 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 495 cpu_relax();
3f479a65 496
cc487e73 497 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 498 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 499
bb90eb00
BW		 500 cs_active(drv_data, chip);
501 dummy_read(drv_data);
cc487e73 502
c3061abb 503 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 504 cs_deactive(drv_data, chip);
5fec5b5a 505
bb90eb00 506 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 507 cpu_relax();
bb90eb00
BW		 508 cs_active(drv_data, chip);
509 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 510 drv_data->rx += 2;
511 }
bb90eb00 512 cs_deactive(drv_data, chip);
cc487e73 513
bb90eb00 514 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 515 cpu_relax();
bb90eb00 516 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 517 drv_data->rx += 2;
a5f6abd4
WB		 518}
519
520static void u16_duplex(struct driver_data *drv_data)
521{
3f479a65 522 /* poll for SPI completion before start */
bb90eb00 523 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 524 cpu_relax();
3f479a65 525
a5f6abd4
WB		 526 /* in duplex mode, clk is triggered by writing of TDBR */
527 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 528 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
529 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 530 cpu_relax();
bb90eb00 531 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 532 cpu_relax();
bb90eb00 533 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 534 drv_data->rx += 2;
535 drv_data->tx += 2;
536 }
537}
538
539static void u16_cs_chg_duplex(struct driver_data *drv_data)
540{
541 struct chip_data *chip = drv_data->cur_chip;
542
3f479a65 543 /* poll for SPI completion before start */
bb90eb00 544 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 545 cpu_relax();
3f479a65 546
a5f6abd4 547 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 548 cs_active(drv_data, chip);
a5f6abd4 549
bb90eb00
BW		 550 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
551 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 552 cpu_relax();
bb90eb00 553 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 554 cpu_relax();
bb90eb00 555 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 556
bb90eb00 557 cs_deactive(drv_data, chip);
5fec5b5a 558
a5f6abd4
WB		 559 drv_data->rx += 2;
560 drv_data->tx += 2;
561 }
a5f6abd4
WB		 562}
563
564/* test if ther is more transfer to be done */
565static void *next_transfer(struct driver_data *drv_data)
566{
567 struct spi_message *msg = drv_data->cur_msg;
568 struct spi_transfer *trans = drv_data->cur_transfer;
569
570 /* Move to next transfer */
571 if (trans->transfer_list.next != &msg->transfers) {
572 drv_data->cur_transfer =
573 list_entry(trans->transfer_list.next,
574 struct spi_transfer, transfer_list);
575 return RUNNING_STATE;
576 } else
577 return DONE_STATE;
578}
579
580/*
581 * caller already set message->status;
582 * dma and pio irqs are blocked give finished message back
583 */
584static void giveback(struct driver_data *drv_data)
585{
fad91c89 586 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 587 struct spi_transfer *last_transfer;
588 unsigned long flags;
589 struct spi_message *msg;
590
591 spin_lock_irqsave(&drv_data->lock, flags);
592 msg = drv_data->cur_msg;
593 drv_data->cur_msg = NULL;
594 drv_data->cur_transfer = NULL;
595 drv_data->cur_chip = NULL;
596 queue_work(drv_data->workqueue, &drv_data->pump_messages);
597 spin_unlock_irqrestore(&drv_data->lock, flags);
598
599 last_transfer = list_entry(msg->transfers.prev,
600 struct spi_transfer, transfer_list);
601
602 msg->state = NULL;
603
604 /* disable chip select signal. And not stop spi in autobuffer mode */
605 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 606 cs_deactive(drv_data, chip);
a5f6abd4
WB		 607 bfin_spi_disable(drv_data);
608 }
609
fad91c89 610 if (!drv_data->cs_change)
bb90eb00 611 cs_deactive(drv_data, chip);
fad91c89 612
a5f6abd4
WB		 613 if (msg->complete)
614 msg->complete(msg->context);
615}
616
88b40369 617static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4
WB		 618{
619 struct driver_data *drv_data = (struct driver_data *)dev_id;
fad91c89 620 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 621 struct spi_message *msg = drv_data->cur_msg;
a5f6abd4 622
88b40369 623 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 624 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 625
d6fe89b0 626 /* Wait for DMA to complete */
bb90eb00 627 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 628 cpu_relax();
d6fe89b0 629
a5f6abd4 630 /*
d6fe89b0
BW		 631 * wait for the last transaction shifted out. HRM states:
632 * at this point there may still be data in the SPI DMA FIFO waiting
633 * to be transmitted ... software needs to poll TXS in the SPI_STAT
634 * register until it goes low for 2 successive reads
a5f6abd4
WB		 635 */
636 if (drv_data->tx != NULL) {
bb90eb00
BW		 637 while ((read_STAT(drv_data) & TXS) ||
638 (read_STAT(drv_data) & TXS))
d8c05008 639 cpu_relax();
a5f6abd4
WB		 640 }
641
bb90eb00 642 while (!(read_STAT(drv_data) & SPIF))
d8c05008 643 cpu_relax();
a5f6abd4 644
a5f6abd4
WB		 645 msg->actual_length += drv_data->len_in_bytes;
646
fad91c89 647 if (drv_data->cs_change)
bb90eb00 648 cs_deactive(drv_data, chip);
fad91c89 649
a5f6abd4
WB		 650 /* Move to next transfer */
651 msg->state = next_transfer(drv_data);
652
653 /* Schedule transfer tasklet */
654 tasklet_schedule(&drv_data->pump_transfers);
655
656 /* free the irq handler before next transfer */
88b40369
BW		 657 dev_dbg(&drv_data->pdev->dev,
658 "disable dma channel irq%d\n",
bb90eb00
BW		 659 drv_data->dma_channel);
660 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 661
662 return IRQ_HANDLED;
663}
664
665static void pump_transfers(unsigned long data)
666{
667 struct driver_data *drv_data = (struct driver_data *)data;
668 struct spi_message *message = NULL;
669 struct spi_transfer *transfer = NULL;
670 struct spi_transfer *previous = NULL;
671 struct chip_data *chip = NULL;
88b40369
BW		 672 u8 width;
673 u16 cr, dma_width, dma_config;
a5f6abd4
WB		 674 u32 tranf_success = 1;
675
676 /* Get current state information */
677 message = drv_data->cur_msg;
678 transfer = drv_data->cur_transfer;
679 chip = drv_data->cur_chip;
092e1fda 680
a5f6abd4
WB		 681 /*
682 * if msg is error or done, report it back using complete() callback
683 */
684
685 /* Handle for abort */
686 if (message->state == ERROR_STATE) {
687 message->status = -EIO;
688 giveback(drv_data);
689 return;
690 }
691
692 /* Handle end of message */
693 if (message->state == DONE_STATE) {
694 message->status = 0;
695 giveback(drv_data);
696 return;
697 }
698
699 /* Delay if requested at end of transfer */
700 if (message->state == RUNNING_STATE) {
701 previous = list_entry(transfer->transfer_list.prev,
702 struct spi_transfer, transfer_list);
703 if (previous->delay_usecs)
704 udelay(previous->delay_usecs);
705 }
706
707 /* Setup the transfer state based on the type of transfer */
708 if (flush(drv_data) == 0) {
709 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
710 message->status = -EIO;
711 giveback(drv_data);
712 return;
713 }
714
715 if (transfer->tx_buf != NULL) {
716 drv_data->tx = (void *)transfer->tx_buf;
717 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 718 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
719 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 720 } else {
721 drv_data->tx = NULL;
722 }
723
724 if (transfer->rx_buf != NULL) {
725 drv_data->rx = transfer->rx_buf;
726 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 727 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
728 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 729 } else {
730 drv_data->rx = NULL;
731 }
732
733 drv_data->rx_dma = transfer->rx_dma;
734 drv_data->tx_dma = transfer->tx_dma;
735 drv_data->len_in_bytes = transfer->len;
fad91c89 736 drv_data->cs_change = transfer->cs_change;
a5f6abd4 737
092e1fda
BW		 738 /* Bits per word setup */
739 switch (transfer->bits_per_word) {
740 case 8:
741 drv_data->n_bytes = 1;
742 width = CFG_SPI_WORDSIZE8;
743 drv_data->read = chip->cs_change_per_word ?
744 u8_cs_chg_reader : u8_reader;
745 drv_data->write = chip->cs_change_per_word ?
746 u8_cs_chg_writer : u8_writer;
747 drv_data->duplex = chip->cs_change_per_word ?
748 u8_cs_chg_duplex : u8_duplex;
749 break;
750
751 case 16:
752 drv_data->n_bytes = 2;
753 width = CFG_SPI_WORDSIZE16;
754 drv_data->read = chip->cs_change_per_word ?
755 u16_cs_chg_reader : u16_reader;
756 drv_data->write = chip->cs_change_per_word ?
757 u16_cs_chg_writer : u16_writer;
758 drv_data->duplex = chip->cs_change_per_word ?
759 u16_cs_chg_duplex : u16_duplex;
760 break;
761
762 default:
763 /* No change, the same as default setting */
764 drv_data->n_bytes = chip->n_bytes;
765 width = chip->width;
766 drv_data->write = drv_data->tx ? chip->write : null_writer;
767 drv_data->read = drv_data->rx ? chip->read : null_reader;
768 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
769 break;
770 }
771 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
772 cr |= (width << 8);
773 write_CTRL(drv_data, cr);
774
a5f6abd4
WB		 775 if (width == CFG_SPI_WORDSIZE16) {
776 drv_data->len = (transfer->len) >> 1;
777 } else {
778 drv_data->len = transfer->len;
779 }
131b17d4
BW		 780 dev_dbg(&drv_data->pdev->dev, "transfer: ",
781 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
782 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 783
784 /* speed and width has been set on per message */
785 message->state = RUNNING_STATE;
786 dma_config = 0;
787
092e1fda
BW		 788 /* Speed setup (surely valid because already checked) */
789 if (transfer->speed_hz)
790 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
791 else
792 write_BAUD(drv_data, chip->baud);
793
bb90eb00
BW		 794 write_STAT(drv_data, BIT_STAT_CLR);
795 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
796 cs_active(drv_data, chip);
a5f6abd4 797
88b40369
BW		 798 dev_dbg(&drv_data->pdev->dev,
799 "now pumping a transfer: width is %d, len is %d\n",
800 width, transfer->len);
a5f6abd4
WB		 801
802 /*
803 * Try to map dma buffer and do a dma transfer if
804 * successful use different way to r/w according to
805 * drv_data->cur_chip->enable_dma
806 */
807 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
808
bb90eb00
BW		 809 disable_dma(drv_data->dma_channel);
810 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 811 bfin_spi_disable(drv_data);
a5f6abd4
WB		 812
813 /* config dma channel */
88b40369 814 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 815 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 816 set_dma_x_count(drv_data->dma_channel, drv_data->len);
817 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 818 dma_width = WDSIZE_16;
819 } else {
bb90eb00
BW		 820 set_dma_x_count(drv_data->dma_channel, drv_data->len);
821 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 822 dma_width = WDSIZE_8;
823 }
824
3f479a65 825 /* poll for SPI completion before start */
bb90eb00 826 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 827 cpu_relax();
3f479a65 828
a5f6abd4
WB		 829 /* dirty hack for autobuffer DMA mode */
830 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 831 dev_dbg(&drv_data->pdev->dev,
832 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 833
834 /* no irq in autobuffer mode */
835 dma_config =
836 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 837 set_dma_config(drv_data->dma_channel, dma_config);
838 set_dma_start_addr(drv_data->dma_channel,
a32c691d 839 (unsigned long)drv_data->tx);
bb90eb00 840 enable_dma(drv_data->dma_channel);
a5f6abd4 841
07612e5f
SZ		 842 /* start SPI transfer */
843 write_CTRL(drv_data,
844 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
845
846 /* just return here, there can only be one transfer
847 * in this mode
848 */
a5f6abd4
WB		 849 message->status = 0;
850 giveback(drv_data);
851 return;
852 }
853
854 /* In dma mode, rx or tx must be NULL in one transfer */
855 if (drv_data->rx != NULL) {
856 /* set transfer mode, and enable SPI */
88b40369 857 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 858
a5f6abd4 859 /* clear tx reg soformer data is not shifted out */
bb90eb00 860 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 861
bb90eb00 862 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 863
864 /* start dma */
bb90eb00 865 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 866 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 867 set_dma_config(drv_data->dma_channel, dma_config);
868 set_dma_start_addr(drv_data->dma_channel,
a32c691d 869 (unsigned long)drv_data->rx);
bb90eb00 870 enable_dma(drv_data->dma_channel);
a5f6abd4 871
07612e5f
SZ		 872 /* start SPI transfer */
873 write_CTRL(drv_data,
874 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
875
a5f6abd4 876 } else if (drv_data->tx != NULL) {
88b40369 877 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4
WB		 878
879 /* start dma */
bb90eb00 880 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 881 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 882 set_dma_config(drv_data->dma_channel, dma_config);
883 set_dma_start_addr(drv_data->dma_channel,
a32c691d 884 (unsigned long)drv_data->tx);
bb90eb00 885 enable_dma(drv_data->dma_channel);
07612e5f
SZ		 886
887 /* start SPI transfer */
888 write_CTRL(drv_data,
889 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
a5f6abd4
WB		 890 }
891 } else {
892 /* IO mode write then read */
88b40369 893 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 894
a5f6abd4
WB		 895 if (drv_data->tx != NULL && drv_data->rx != NULL) {
896 /* full duplex mode */
897 BUG_ON((drv_data->tx_end - drv_data->tx) !=
898 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 899 dev_dbg(&drv_data->pdev->dev,
900 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 901
cc487e73 902 /* set SPI transfer mode */
bb90eb00 903 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 904
905 drv_data->duplex(drv_data);
906
907 if (drv_data->tx != drv_data->tx_end)
908 tranf_success = 0;
909 } else if (drv_data->tx != NULL) {
910 /* write only half duplex */
131b17d4 911 dev_dbg(&drv_data->pdev->dev,
88b40369 912 "IO write: cr is 0x%x\n", cr);
a5f6abd4 913
cc487e73 914 /* set SPI transfer mode */
bb90eb00 915 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 916
917 drv_data->write(drv_data);
918
919 if (drv_data->tx != drv_data->tx_end)
920 tranf_success = 0;
921 } else if (drv_data->rx != NULL) {
922 /* read only half duplex */
131b17d4 923 dev_dbg(&drv_data->pdev->dev,
88b40369 924 "IO read: cr is 0x%x\n", cr);
a5f6abd4 925
cc487e73 926 /* set SPI transfer mode */
bb90eb00 927 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 928
929 drv_data->read(drv_data);
930 if (drv_data->rx != drv_data->rx_end)
931 tranf_success = 0;
932 }
933
934 if (!tranf_success) {
131b17d4 935 dev_dbg(&drv_data->pdev->dev,
88b40369 936 "IO write error!\n");
a5f6abd4
WB		 937 message->state = ERROR_STATE;
938 } else {
939 /* Update total byte transfered */
940 message->actual_length += drv_data->len;
941
942 /* Move to next transfer of this msg */
943 message->state = next_transfer(drv_data);
944 }
945
946 /* Schedule next transfer tasklet */
947 tasklet_schedule(&drv_data->pump_transfers);
948
949 }
950}
951
952/* pop a msg from queue and kick off real transfer */
953static void pump_messages(struct work_struct *work)
954{
131b17d4 955 struct driver_data *drv_data;
a5f6abd4
WB		 956 unsigned long flags;
957
131b17d4
BW		 958 drv_data = container_of(work, struct driver_data, pump_messages);
959
a5f6abd4
WB		 960 /* Lock queue and check for queue work */
961 spin_lock_irqsave(&drv_data->lock, flags);
962 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
963 /* pumper kicked off but no work to do */
964 drv_data->busy = 0;
965 spin_unlock_irqrestore(&drv_data->lock, flags);
966 return;
967 }
968
969 /* Make sure we are not already running a message */
970 if (drv_data->cur_msg) {
971 spin_unlock_irqrestore(&drv_data->lock, flags);
972 return;
973 }
974
975 /* Extract head of queue */
976 drv_data->cur_msg = list_entry(drv_data->queue.next,
977 struct spi_message, queue);
5fec5b5a
BW		 978
979 /* Setup the SSP using the per chip configuration */
980 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
981 if (restore_state(drv_data)) {
982 spin_unlock_irqrestore(&drv_data->lock, flags);
983 return;
984 };
985
a5f6abd4
WB		 986 list_del_init(&drv_data->cur_msg->queue);
987
988 /* Initial message state */
989 drv_data->cur_msg->state = START_STATE;
990 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
991 struct spi_transfer, transfer_list);
992
5fec5b5a
BW		 993 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
994 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
995 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
996 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 997
998 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 999 "the first transfer len is %d\n",
1000 drv_data->cur_transfer->len);
a5f6abd4
WB		 1001
1002 /* Mark as busy and launch transfers */
1003 tasklet_schedule(&drv_data->pump_transfers);
1004
1005 drv_data->busy = 1;
1006 spin_unlock_irqrestore(&drv_data->lock, flags);
1007}
1008
1009/*
1010 * got a msg to transfer, queue it in drv_data->queue.
1011 * And kick off message pumper
1012 */
1013static int transfer(struct spi_device *spi, struct spi_message *msg)
1014{
1015 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1016 unsigned long flags;
1017
1018 spin_lock_irqsave(&drv_data->lock, flags);
1019
1020 if (drv_data->run == QUEUE_STOPPED) {
1021 spin_unlock_irqrestore(&drv_data->lock, flags);
1022 return -ESHUTDOWN;
1023 }
1024
1025 msg->actual_length = 0;
1026 msg->status = -EINPROGRESS;
1027 msg->state = START_STATE;
1028
88b40369 1029 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 1030 list_add_tail(&msg->queue, &drv_data->queue);
1031
1032 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1033 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1034
1035 spin_unlock_irqrestore(&drv_data->lock, flags);
1036
1037 return 0;
1038}
1039
12e17c42
SZ		 1040#define MAX_SPI_SSEL 7
1041
1042static u16 ssel[3][MAX_SPI_SSEL] = {
1043 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1044 P_SPI0_SSEL4, P_SPI0_SSEL5,
1045 P_SPI0_SSEL6, P_SPI0_SSEL7},
1046
1047 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1048 P_SPI1_SSEL4, P_SPI1_SSEL5,
1049 P_SPI1_SSEL6, P_SPI1_SSEL7},
1050
1051 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1052 P_SPI2_SSEL4, P_SPI2_SSEL5,
1053 P_SPI2_SSEL6, P_SPI2_SSEL7},
1054};
1055
a5f6abd4
WB		 1056/* first setup for new devices */
1057static int setup(struct spi_device *spi)
1058{
1059 struct bfin5xx_spi_chip *chip_info = NULL;
1060 struct chip_data *chip;
1061 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1062 u8 spi_flg;
1063
1064 /* Abort device setup if requested features are not supported */
1065 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1066 dev_err(&spi->dev, "requested mode not fully supported\n");
1067 return -EINVAL;
1068 }
1069
1070 /* Zero (the default) here means 8 bits */
1071 if (!spi->bits_per_word)
1072 spi->bits_per_word = 8;
1073
1074 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1075 return -EINVAL;
1076
1077 /* Only alloc (or use chip_info) on first setup */
1078 chip = spi_get_ctldata(spi);
1079 if (chip == NULL) {
1080 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1081 if (!chip)
1082 return -ENOMEM;
1083
1084 chip->enable_dma = 0;
1085 chip_info = spi->controller_data;
1086 }
1087
1088 /* chip_info isn't always needed */
1089 if (chip_info) {
2ed35516
MF		 1090 /* Make sure people stop trying to set fields via ctl_reg
1091 * when they should actually be using common SPI framework.
1092 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1093 * Not sure if a user actually needs/uses any of these,
1094 * but let's assume (for now) they do.
1095 */
1096 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1097 dev_err(&spi->dev, "do not set bits in ctl_reg "
1098 "that the SPI framework manages\n");
1099 return -EINVAL;
1100 }
1101
a5f6abd4
WB		 1102 chip->enable_dma = chip_info->enable_dma != 0
1103 && drv_data->master_info->enable_dma;
1104 chip->ctl_reg = chip_info->ctl_reg;
1105 chip->bits_per_word = chip_info->bits_per_word;
1106 chip->cs_change_per_word = chip_info->cs_change_per_word;
1107 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1108 }
1109
1110 /* translate common spi framework into our register */
1111 if (spi->mode & SPI_CPOL)
1112 chip->ctl_reg |= CPOL;
1113 if (spi->mode & SPI_CPHA)
1114 chip->ctl_reg |= CPHA;
1115 if (spi->mode & SPI_LSB_FIRST)
1116 chip->ctl_reg |= LSBF;
1117 /* we dont support running in slave mode (yet?) */
1118 chip->ctl_reg |= MSTR;
1119
1120 /*
1121 * if any one SPI chip is registered and wants DMA, request the
1122 * DMA channel for it
1123 */
bb90eb00 1124 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1125 /* register dma irq handler */
bb90eb00 1126 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1127 dev_dbg(&spi->dev,
1128 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1129 return -ENODEV;
1130 }
bb90eb00
BW		 1131 if (set_dma_callback(drv_data->dma_channel,
1132 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1133 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1134 return -EPERM;
1135 }
bb90eb00
BW		 1136 dma_disable_irq(drv_data->dma_channel);
1137 drv_data->dma_requested = 1;
a5f6abd4
WB		 1138 }
1139
1140 /*
1141 * Notice: for blackfin, the speed_hz is the value of register
1142 * SPI_BAUD, not the real baudrate
1143 */
1144 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1145 spi_flg = ~(1 << (spi->chip_select));
1146 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1147 chip->chip_select_num = spi->chip_select;
1148
1149 switch (chip->bits_per_word) {
1150 case 8:
1151 chip->n_bytes = 1;
1152 chip->width = CFG_SPI_WORDSIZE8;
1153 chip->read = chip->cs_change_per_word ?
1154 u8_cs_chg_reader : u8_reader;
1155 chip->write = chip->cs_change_per_word ?
1156 u8_cs_chg_writer : u8_writer;
1157 chip->duplex = chip->cs_change_per_word ?
1158 u8_cs_chg_duplex : u8_duplex;
1159 break;
1160
1161 case 16:
1162 chip->n_bytes = 2;
1163 chip->width = CFG_SPI_WORDSIZE16;
1164 chip->read = chip->cs_change_per_word ?
1165 u16_cs_chg_reader : u16_reader;
1166 chip->write = chip->cs_change_per_word ?
1167 u16_cs_chg_writer : u16_writer;
1168 chip->duplex = chip->cs_change_per_word ?
1169 u16_cs_chg_duplex : u16_duplex;
1170 break;
1171
1172 default:
1173 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1174 chip->bits_per_word);
1175 kfree(chip);
1176 return -ENODEV;
1177 }
1178
898eb71c 1179 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1180 spi->modalias, chip->width, chip->enable_dma);
88b40369 1181 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1182 chip->ctl_reg, chip->flag);
1183
1184 spi_set_ctldata(spi, chip);
1185
12e17c42
SZ		 1186 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1187 if ((chip->chip_select_num > 0)
1188 && (chip->chip_select_num <= spi->master->num_chipselect))
1189 peripheral_request(ssel[spi->master->bus_num]
1190 [chip->chip_select_num-1], DRV_NAME);
1191
07612e5f
SZ		 1192 cs_deactive(drv_data, chip);
1193
a5f6abd4
WB		 1194 return 0;
1195}
1196
1197/*
1198 * callback for spi framework.
1199 * clean driver specific data
1200 */
88b40369 1201static void cleanup(struct spi_device *spi)
a5f6abd4 1202{
27bb9e79 1203 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1204
12e17c42
SZ		 1205 if ((chip->chip_select_num > 0)
1206 && (chip->chip_select_num <= spi->master->num_chipselect))
1207 peripheral_free(ssel[spi->master->bus_num]
1208 [chip->chip_select_num-1]);
1209
a5f6abd4
WB		 1210 kfree(chip);
1211}
1212
1213static inline int init_queue(struct driver_data *drv_data)
1214{
1215 INIT_LIST_HEAD(&drv_data->queue);
1216 spin_lock_init(&drv_data->lock);
1217
1218 drv_data->run = QUEUE_STOPPED;
1219 drv_data->busy = 0;
1220
1221 /* init transfer tasklet */
1222 tasklet_init(&drv_data->pump_transfers,
1223 pump_transfers, (unsigned long)drv_data);
1224
1225 /* init messages workqueue */
1226 INIT_WORK(&drv_data->pump_messages, pump_messages);
1227 drv_data->workqueue =
49dce689 1228 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
a5f6abd4
WB		 1229 if (drv_data->workqueue == NULL)
1230 return -EBUSY;
1231
1232 return 0;
1233}
1234
1235static inline int start_queue(struct driver_data *drv_data)
1236{
1237 unsigned long flags;
1238
1239 spin_lock_irqsave(&drv_data->lock, flags);
1240
1241 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1242 spin_unlock_irqrestore(&drv_data->lock, flags);
1243 return -EBUSY;
1244 }
1245
1246 drv_data->run = QUEUE_RUNNING;
1247 drv_data->cur_msg = NULL;
1248 drv_data->cur_transfer = NULL;
1249 drv_data->cur_chip = NULL;
1250 spin_unlock_irqrestore(&drv_data->lock, flags);
1251
1252 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1253
1254 return 0;
1255}
1256
1257static inline int stop_queue(struct driver_data *drv_data)
1258{
1259 unsigned long flags;
1260 unsigned limit = 500;
1261 int status = 0;
1262
1263 spin_lock_irqsave(&drv_data->lock, flags);
1264
1265 /*
1266 * This is a bit lame, but is optimized for the common execution path.
1267 * A wait_queue on the drv_data->busy could be used, but then the common
1268 * execution path (pump_messages) would be required to call wake_up or
1269 * friends on every SPI message. Do this instead
1270 */
1271 drv_data->run = QUEUE_STOPPED;
1272 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1273 spin_unlock_irqrestore(&drv_data->lock, flags);
1274 msleep(10);
1275 spin_lock_irqsave(&drv_data->lock, flags);
1276 }
1277
1278 if (!list_empty(&drv_data->queue) || drv_data->busy)
1279 status = -EBUSY;
1280
1281 spin_unlock_irqrestore(&drv_data->lock, flags);
1282
1283 return status;
1284}
1285
1286static inline int destroy_queue(struct driver_data *drv_data)
1287{
1288 int status;
1289
1290 status = stop_queue(drv_data);
1291 if (status != 0)
1292 return status;
1293
1294 destroy_workqueue(drv_data->workqueue);
1295
1296 return 0;
1297}
1298
1299static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1300{
1301 struct device *dev = &pdev->dev;
1302 struct bfin5xx_spi_master *platform_info;
1303 struct spi_master *master;
1304 struct driver_data *drv_data = 0;
a32c691d 1305 struct resource *res;
a5f6abd4
WB		 1306 int status = 0;
1307
1308 platform_info = dev->platform_data;
1309
1310 /* Allocate master with space for drv_data */
1311 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1312 if (!master) {
1313 dev_err(&pdev->dev, "can not alloc spi_master\n");
1314 return -ENOMEM;
1315 }
131b17d4 1316
a5f6abd4
WB		 1317 drv_data = spi_master_get_devdata(master);
1318 drv_data->master = master;
1319 drv_data->master_info = platform_info;
1320 drv_data->pdev = pdev;
003d9226 1321 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1322
1323 master->bus_num = pdev->id;
1324 master->num_chipselect = platform_info->num_chipselect;
1325 master->cleanup = cleanup;
1326 master->setup = setup;
1327 master->transfer = transfer;
1328
a32c691d
BW		 1329 /* Find and map our resources */
1330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 if (res == NULL) {
1332 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1333 status = -ENOENT;
1334 goto out_error_get_res;
1335 }
1336
f452126c
BW		 1337 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1338 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1339 dev_err(dev, "Cannot map IO\n");
1340 status = -ENXIO;
1341 goto out_error_ioremap;
1342 }
1343
bb90eb00
BW		 1344 drv_data->dma_channel = platform_get_irq(pdev, 0);
1345 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1346 dev_err(dev, "No DMA channel specified\n");
1347 status = -ENOENT;
1348 goto out_error_no_dma_ch;
1349 }
1350
a5f6abd4
WB		 1351 /* Initial and start queue */
1352 status = init_queue(drv_data);
1353 if (status != 0) {
a32c691d 1354 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1355 goto out_error_queue_alloc;
1356 }
a32c691d 1357
a5f6abd4
WB		 1358 status = start_queue(drv_data);
1359 if (status != 0) {
a32c691d 1360 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1361 goto out_error_queue_alloc;
1362 }
1363
1364 /* Register with the SPI framework */
1365 platform_set_drvdata(pdev, drv_data);
1366 status = spi_register_master(master);
1367 if (status != 0) {
a32c691d 1368 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1369 goto out_error_queue_alloc;
1370 }
a32c691d 1371
003d9226
BW		 1372 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1373 if (status != 0) {
7c4ef094
SZ		 1374 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1375 goto out_error;
1376 }
1377
f452126c 1378 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1379 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1380 drv_data->dma_channel);
a5f6abd4
WB		 1381 return status;
1382
cc2f81a6 1383out_error_queue_alloc:
a5f6abd4 1384 destroy_queue(drv_data);
a32c691d 1385out_error_no_dma_ch:
bb90eb00 1386 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1387out_error_ioremap:
1388out_error_get_res:
cc2f81a6 1389out_error:
a5f6abd4 1390 spi_master_put(master);
cc2f81a6 1391
a5f6abd4
WB		 1392 return status;
1393}
1394
1395/* stop hardware and remove the driver */
1396static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1397{
1398 struct driver_data *drv_data = platform_get_drvdata(pdev);
1399 int status = 0;
1400
1401 if (!drv_data)
1402 return 0;
1403
1404 /* Remove the queue */
1405 status = destroy_queue(drv_data);
1406 if (status != 0)
1407 return status;
1408
1409 /* Disable the SSP at the peripheral and SOC level */
1410 bfin_spi_disable(drv_data);
1411
1412 /* Release DMA */
1413 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1414 if (dma_channel_active(drv_data->dma_channel))
1415 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1416 }
1417
1418 /* Disconnect from the SPI framework */
1419 spi_unregister_master(drv_data->master);
1420
003d9226 1421 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1422
a5f6abd4
WB		 1423 /* Prevent double remove */
1424 platform_set_drvdata(pdev, NULL);
1425
1426 return 0;
1427}
1428
1429#ifdef CONFIG_PM
1430static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1431{
1432 struct driver_data *drv_data = platform_get_drvdata(pdev);
1433 int status = 0;
1434
1435 status = stop_queue(drv_data);
1436 if (status != 0)
1437 return status;
1438
1439 /* stop hardware */
1440 bfin_spi_disable(drv_data);
1441
1442 return 0;
1443}
1444
1445static int bfin5xx_spi_resume(struct platform_device *pdev)
1446{
1447 struct driver_data *drv_data = platform_get_drvdata(pdev);
1448 int status = 0;
1449
1450 /* Enable the SPI interface */
1451 bfin_spi_enable(drv_data);
1452
1453 /* Start the queue running */
1454 status = start_queue(drv_data);
1455 if (status != 0) {
1456 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1457 return status;
1458 }
1459
1460 return 0;
1461}
1462#else
1463#define bfin5xx_spi_suspend NULL
1464#define bfin5xx_spi_resume NULL
1465#endif /* CONFIG_PM */
1466
fc3ba952 1467MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
a5f6abd4 1468static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1469 .driver = {
a32c691d 1470 .name = DRV_NAME,
88b40369
BW		 1471 .owner = THIS_MODULE,
1472 },
1473 .suspend = bfin5xx_spi_suspend,
1474 .resume = bfin5xx_spi_resume,
1475 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1476};
1477
1478static int __init bfin5xx_spi_init(void)
1479{
88b40369 1480 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1481}
a5f6abd4
WB		 1482module_init(bfin5xx_spi_init);
1483
1484static void __exit bfin5xx_spi_exit(void)
1485{
1486 platform_driver_unregister(&bfin5xx_spi_driver);
1487}
a5f6abd4 1488module_exit(bfin5xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)