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spi_bfin: use more useful GPIO labels
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
131b17d4
BW		 2 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
a5f6abd4 7 *
131b17d4
BW		 8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
a5f6abd4
WB		 11 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
131b17d4 15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
a32c691d
BW		 16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
a5f6abd4 18 *
131b17d4 19 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4
WB		 20 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37#include <linux/init.h>
38#include <linux/module.h>
131b17d4 39#include <linux/delay.h>
a5f6abd4 40#include <linux/device.h>
131b17d4 41#include <linux/io.h>
a5f6abd4 42#include <linux/ioport.h>
131b17d4 43#include <linux/irq.h>
a5f6abd4
WB		 44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/spi/spi.h>
49#include <linux/workqueue.h>
a5f6abd4 50
a5f6abd4 51#include <asm/dma.h>
131b17d4 52#include <asm/portmux.h>
a5f6abd4
WB		 53#include <asm/bfin5xx_spi.h>
54
a32c691d
BW		 55#define DRV_NAME "bfin-spi"
56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 57#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 58#define DRV_VERSION "1.0"
59
60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 62MODULE_LICENSE("GPL");
63
bb90eb00 64#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 65
bb90eb00
BW		 66#define START_STATE ((void *)0)
67#define RUNNING_STATE ((void *)1)
68#define DONE_STATE ((void *)2)
69#define ERROR_STATE ((void *)-1)
70#define QUEUE_RUNNING 0
71#define QUEUE_STOPPED 1
a5f6abd4
WB		 72
73struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
bb90eb00 80 /* Regs base of SPI controller */
f452126c 81 void __iomem *regs_base;
bb90eb00 82
003d9226
BW		 83 /* Pin request list */
84 u16 *pin_req;
85
a5f6abd4
WB		 86 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info;
88
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
92 spinlock_t lock;
93 struct list_head queue;
94 int busy;
95 int run;
96
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
99
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
104 size_t len_in_bytes;
105 size_t len;
106 void *tx;
107 void *tx_end;
108 void *rx;
109 void *rx_end;
bb90eb00
BW		 110
111 /* DMA stuffs */
112 int dma_channel;
a5f6abd4 113 int dma_mapped;
bb90eb00 114 int dma_requested;
a5f6abd4
WB		 115 dma_addr_t rx_dma;
116 dma_addr_t tx_dma;
bb90eb00 117
a5f6abd4
WB		 118 size_t rx_map_len;
119 size_t tx_map_len;
120 u8 n_bytes;
fad91c89 121 int cs_change;
a5f6abd4
WB		 122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
125};
126
127struct chip_data {
128 u16 ctl_reg;
129 u16 baud;
130 u16 flag;
131
132 u8 chip_select_num;
133 u8 n_bytes;
88b40369 134 u8 width; /* 0 or 1 */
a5f6abd4
WB		 135 u8 enable_dma;
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
62310e51 138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
142};
143
bb90eb00
BW		 144#define DEFINE_SPI_REG(reg, off) \
145static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150DEFINE_SPI_REG(CTRL, 0x00)
151DEFINE_SPI_REG(FLAG, 0x04)
152DEFINE_SPI_REG(STAT, 0x08)
153DEFINE_SPI_REG(TDBR, 0x0C)
154DEFINE_SPI_REG(RDBR, 0x10)
155DEFINE_SPI_REG(BAUD, 0x14)
156DEFINE_SPI_REG(SHAW, 0x18)
157
88b40369 158static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 159{
160 u16 cr;
161
bb90eb00
BW		 162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 164}
165
88b40369 166static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 167{
168 u16 cr;
169
bb90eb00
BW		 170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 172}
173
174/* Caculate the SPI_BAUD register value based on input HZ */
175static u16 hz_to_spi_baud(u32 speed_hz)
176{
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
179
180 if ((sclk % (2 * speed_hz)) > 0)
181 spi_baud++;
182
a5f6abd4
WB		 183 return spi_baud;
184}
185
186static int flush(struct driver_data *drv_data)
187{
188 unsigned long limit = loops_per_jiffy << 1;
189
190 /* wait for stop and clear stat */
bb90eb00 191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 192 cpu_relax();
a5f6abd4 193
bb90eb00 194 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 195
196 return limit;
197}
198
fad91c89 199/* Chip select operation functions for cs_change flag */
bb90eb00 200static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 201{
bb90eb00 202 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
bb90eb00 207 write_FLAG(drv_data, flag);
fad91c89
BW		 208}
209
bb90eb00 210static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 211{
bb90eb00 212 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 213
214 flag |= (chip->flag << 8);
215
bb90eb00 216 write_FLAG(drv_data, flag);
62310e51
BW		 217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
fad91c89
BW		 221}
222
7c4ef094 223#define MAX_SPI_SSEL 7
5fec5b5a 224
a5f6abd4 225/* stop controller and re-config current chip*/
8d20d0a7 226static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 227{
228 struct chip_data *chip = drv_data->cur_chip;
12e17c42 229
a5f6abd4 230 /* Clear status and disable clock */
bb90eb00 231 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 232 bfin_spi_disable(drv_data);
88b40369 233 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 234
5fec5b5a 235 /* Load the registers */
bb90eb00 236 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 237 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 238
239 bfin_spi_enable(drv_data);
07612e5f 240 cs_active(drv_data, chip);
a5f6abd4
WB		 241}
242
243/* used to kick off transfer in rx mode */
bb90eb00 244static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 245{
246 unsigned short tmp;
bb90eb00 247 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 248 return tmp;
249}
250
251static void null_writer(struct driver_data *drv_data)
252{
253 u8 n_bytes = drv_data->n_bytes;
254
255 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 256 write_TDBR(drv_data, 0);
257 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 258 cpu_relax();
a5f6abd4
WB		 259 drv_data->tx += n_bytes;
260 }
261}
262
263static void null_reader(struct driver_data *drv_data)
264{
265 u8 n_bytes = drv_data->n_bytes;
bb90eb00 266 dummy_read(drv_data);
a5f6abd4
WB		 267
268 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 270 cpu_relax();
bb90eb00 271 dummy_read(drv_data);
a5f6abd4
WB		 272 drv_data->rx += n_bytes;
273 }
274}
275
276static void u8_writer(struct driver_data *drv_data)
277{
131b17d4 278 dev_dbg(&drv_data->pdev->dev,
bb90eb00 279 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 280
3f479a65 281 /* poll for SPI completion before start */
bb90eb00 282 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 283 cpu_relax();
3f479a65 284
a5f6abd4 285 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 286 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
287 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 288 cpu_relax();
a5f6abd4
WB		 289 ++drv_data->tx;
290 }
a5f6abd4
WB		 291}
292
293static void u8_cs_chg_writer(struct driver_data *drv_data)
294{
295 struct chip_data *chip = drv_data->cur_chip;
296
3f479a65 297 /* poll for SPI completion before start */
bb90eb00 298 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 299 cpu_relax();
3f479a65 300
a5f6abd4 301 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 302 cs_active(drv_data, chip);
a5f6abd4 303
bb90eb00
BW		 304 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
305 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 306 cpu_relax();
62310e51 307
bb90eb00 308 cs_deactive(drv_data, chip);
5fec5b5a 309
a5f6abd4
WB		 310 ++drv_data->tx;
311 }
a5f6abd4
WB		 312}
313
314static void u8_reader(struct driver_data *drv_data)
315{
131b17d4 316 dev_dbg(&drv_data->pdev->dev,
bb90eb00 317 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 318
3f479a65 319 /* poll for SPI completion before start */
bb90eb00 320 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 321 cpu_relax();
3f479a65 322
a5f6abd4 323 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 324 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 325
bb90eb00 326 dummy_read(drv_data);
cc487e73 327
a5f6abd4 328 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 329 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 330 cpu_relax();
bb90eb00 331 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 332 ++drv_data->rx;
333 }
334
bb90eb00 335 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 336 cpu_relax();
bb90eb00 337 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 338 ++drv_data->rx;
339}
340
341static void u8_cs_chg_reader(struct driver_data *drv_data)
342{
343 struct chip_data *chip = drv_data->cur_chip;
344
3f479a65 345 /* poll for SPI completion before start */
bb90eb00 346 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 347 cpu_relax();
3f479a65 348
cc487e73 349 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 350 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 351
bb90eb00
BW		 352 cs_active(drv_data, chip);
353 dummy_read(drv_data);
cc487e73
SZ		 354
355 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 356 cs_deactive(drv_data, chip);
5fec5b5a 357
bb90eb00 358 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 359 cpu_relax();
bb90eb00
BW		 360 cs_active(drv_data, chip);
361 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 362 ++drv_data->rx;
363 }
bb90eb00 364 cs_deactive(drv_data, chip);
5fec5b5a 365
bb90eb00 366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 367 cpu_relax();
bb90eb00 368 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 369 ++drv_data->rx;
a5f6abd4
WB		 370}
371
372static void u8_duplex(struct driver_data *drv_data)
373{
3f479a65 374 /* poll for SPI completion before start */
bb90eb00 375 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 376 cpu_relax();
3f479a65 377
a5f6abd4
WB		 378 /* in duplex mode, clk is triggered by writing of TDBR */
379 while (drv_data->rx < drv_data->rx_end) {
bb90eb00
BW		 380 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
381 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 382 cpu_relax();
bb90eb00 383 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 384 cpu_relax();
bb90eb00 385 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 386 ++drv_data->rx;
387 ++drv_data->tx;
388 }
389}
390
391static void u8_cs_chg_duplex(struct driver_data *drv_data)
392{
393 struct chip_data *chip = drv_data->cur_chip;
394
3f479a65 395 /* poll for SPI completion before start */
bb90eb00 396 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 397 cpu_relax();
3f479a65 398
a5f6abd4 399 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 400 cs_active(drv_data, chip);
5fec5b5a 401
bb90eb00
BW		 402 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
403 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 404 cpu_relax();
bb90eb00 405 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 406 cpu_relax();
bb90eb00 407 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 408
bb90eb00 409 cs_deactive(drv_data, chip);
5fec5b5a 410
a5f6abd4
WB		 411 ++drv_data->rx;
412 ++drv_data->tx;
413 }
a5f6abd4
WB		 414}
415
416static void u16_writer(struct driver_data *drv_data)
417{
131b17d4 418 dev_dbg(&drv_data->pdev->dev,
bb90eb00 419 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 420
3f479a65 421 /* poll for SPI completion before start */
bb90eb00 422 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 423 cpu_relax();
3f479a65 424
a5f6abd4 425 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 426 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
427 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 428 cpu_relax();
a5f6abd4
WB		 429 drv_data->tx += 2;
430 }
a5f6abd4
WB		 431}
432
433static void u16_cs_chg_writer(struct driver_data *drv_data)
434{
435 struct chip_data *chip = drv_data->cur_chip;
436
3f479a65 437 /* poll for SPI completion before start */
bb90eb00 438 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 439 cpu_relax();
3f479a65 440
a5f6abd4 441 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 442 cs_active(drv_data, chip);
a5f6abd4 443
bb90eb00
BW		 444 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
445 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 446 cpu_relax();
62310e51 447
bb90eb00 448 cs_deactive(drv_data, chip);
5fec5b5a 449
a5f6abd4
WB		 450 drv_data->tx += 2;
451 }
a5f6abd4
WB		 452}
453
454static void u16_reader(struct driver_data *drv_data)
455{
88b40369 456 dev_dbg(&drv_data->pdev->dev,
bb90eb00 457 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 458
3f479a65 459 /* poll for SPI completion before start */
bb90eb00 460 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 461 cpu_relax();
3f479a65 462
cc487e73 463 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 464 write_TDBR(drv_data, 0xFFFF);
cc487e73 465
bb90eb00 466 dummy_read(drv_data);
a5f6abd4
WB		 467
468 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 469 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 470 cpu_relax();
bb90eb00 471 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 472 drv_data->rx += 2;
473 }
474
bb90eb00 475 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 476 cpu_relax();
bb90eb00 477 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 478 drv_data->rx += 2;
479}
480
481static void u16_cs_chg_reader(struct driver_data *drv_data)
482{
483 struct chip_data *chip = drv_data->cur_chip;
484
3f479a65 485 /* poll for SPI completion before start */
bb90eb00 486 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 487 cpu_relax();
3f479a65 488
cc487e73 489 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 490 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 491
bb90eb00
BW		 492 cs_active(drv_data, chip);
493 dummy_read(drv_data);
cc487e73 494
c3061abb 495 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 496 cs_deactive(drv_data, chip);
5fec5b5a 497
bb90eb00 498 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 499 cpu_relax();
bb90eb00
BW		 500 cs_active(drv_data, chip);
501 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 502 drv_data->rx += 2;
503 }
bb90eb00 504 cs_deactive(drv_data, chip);
cc487e73 505
bb90eb00 506 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 507 cpu_relax();
bb90eb00 508 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 509 drv_data->rx += 2;
a5f6abd4
WB		 510}
511
512static void u16_duplex(struct driver_data *drv_data)
513{
3f479a65 514 /* poll for SPI completion before start */
bb90eb00 515 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 516 cpu_relax();
3f479a65 517
a5f6abd4
WB		 518 /* in duplex mode, clk is triggered by writing of TDBR */
519 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 520 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
521 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 522 cpu_relax();
bb90eb00 523 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 524 cpu_relax();
bb90eb00 525 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 526 drv_data->rx += 2;
527 drv_data->tx += 2;
528 }
529}
530
531static void u16_cs_chg_duplex(struct driver_data *drv_data)
532{
533 struct chip_data *chip = drv_data->cur_chip;
534
3f479a65 535 /* poll for SPI completion before start */
bb90eb00 536 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 537 cpu_relax();
3f479a65 538
a5f6abd4 539 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 540 cs_active(drv_data, chip);
a5f6abd4 541
bb90eb00
BW		 542 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
543 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 544 cpu_relax();
bb90eb00 545 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 546 cpu_relax();
bb90eb00 547 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 548
bb90eb00 549 cs_deactive(drv_data, chip);
5fec5b5a 550
a5f6abd4
WB		 551 drv_data->rx += 2;
552 drv_data->tx += 2;
553 }
a5f6abd4
WB		 554}
555
556/* test if ther is more transfer to be done */
557static void *next_transfer(struct driver_data *drv_data)
558{
559 struct spi_message *msg = drv_data->cur_msg;
560 struct spi_transfer *trans = drv_data->cur_transfer;
561
562 /* Move to next transfer */
563 if (trans->transfer_list.next != &msg->transfers) {
564 drv_data->cur_transfer =
565 list_entry(trans->transfer_list.next,
566 struct spi_transfer, transfer_list);
567 return RUNNING_STATE;
568 } else
569 return DONE_STATE;
570}
571
572/*
573 * caller already set message->status;
574 * dma and pio irqs are blocked give finished message back
575 */
576static void giveback(struct driver_data *drv_data)
577{
fad91c89 578 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 579 struct spi_transfer *last_transfer;
580 unsigned long flags;
581 struct spi_message *msg;
582
583 spin_lock_irqsave(&drv_data->lock, flags);
584 msg = drv_data->cur_msg;
585 drv_data->cur_msg = NULL;
586 drv_data->cur_transfer = NULL;
587 drv_data->cur_chip = NULL;
588 queue_work(drv_data->workqueue, &drv_data->pump_messages);
589 spin_unlock_irqrestore(&drv_data->lock, flags);
590
591 last_transfer = list_entry(msg->transfers.prev,
592 struct spi_transfer, transfer_list);
593
594 msg->state = NULL;
595
596 /* disable chip select signal. And not stop spi in autobuffer mode */
597 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 598 cs_deactive(drv_data, chip);
a5f6abd4
WB		 599 bfin_spi_disable(drv_data);
600 }
601
fad91c89 602 if (!drv_data->cs_change)
bb90eb00 603 cs_deactive(drv_data, chip);
fad91c89 604
a5f6abd4
WB		 605 if (msg->complete)
606 msg->complete(msg->context);
607}
608
88b40369 609static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 610{
15aafa2f 611 struct driver_data *drv_data = dev_id;
fad91c89 612 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 613 struct spi_message *msg = drv_data->cur_msg;
a5f6abd4 614
88b40369 615 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 616 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 617
d6fe89b0 618 /* Wait for DMA to complete */
bb90eb00 619 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 620 cpu_relax();
d6fe89b0 621
a5f6abd4 622 /*
d6fe89b0
BW		 623 * wait for the last transaction shifted out. HRM states:
624 * at this point there may still be data in the SPI DMA FIFO waiting
625 * to be transmitted ... software needs to poll TXS in the SPI_STAT
626 * register until it goes low for 2 successive reads
a5f6abd4
WB		 627 */
628 if (drv_data->tx != NULL) {
bb90eb00
BW		 629 while ((read_STAT(drv_data) & TXS) ||
630 (read_STAT(drv_data) & TXS))
d8c05008 631 cpu_relax();
a5f6abd4
WB		 632 }
633
bb90eb00 634 while (!(read_STAT(drv_data) & SPIF))
d8c05008 635 cpu_relax();
a5f6abd4 636
a5f6abd4
WB		 637 msg->actual_length += drv_data->len_in_bytes;
638
fad91c89 639 if (drv_data->cs_change)
bb90eb00 640 cs_deactive(drv_data, chip);
fad91c89 641
a5f6abd4
WB		 642 /* Move to next transfer */
643 msg->state = next_transfer(drv_data);
644
645 /* Schedule transfer tasklet */
646 tasklet_schedule(&drv_data->pump_transfers);
647
648 /* free the irq handler before next transfer */
88b40369
BW		 649 dev_dbg(&drv_data->pdev->dev,
650 "disable dma channel irq%d\n",
bb90eb00
BW		 651 drv_data->dma_channel);
652 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 653
654 return IRQ_HANDLED;
655}
656
657static void pump_transfers(unsigned long data)
658{
659 struct driver_data *drv_data = (struct driver_data *)data;
660 struct spi_message *message = NULL;
661 struct spi_transfer *transfer = NULL;
662 struct spi_transfer *previous = NULL;
663 struct chip_data *chip = NULL;
88b40369
BW		 664 u8 width;
665 u16 cr, dma_width, dma_config;
a5f6abd4
WB		 666 u32 tranf_success = 1;
667
668 /* Get current state information */
669 message = drv_data->cur_msg;
670 transfer = drv_data->cur_transfer;
671 chip = drv_data->cur_chip;
092e1fda 672
a5f6abd4
WB		 673 /*
674 * if msg is error or done, report it back using complete() callback
675 */
676
677 /* Handle for abort */
678 if (message->state == ERROR_STATE) {
679 message->status = -EIO;
680 giveback(drv_data);
681 return;
682 }
683
684 /* Handle end of message */
685 if (message->state == DONE_STATE) {
686 message->status = 0;
687 giveback(drv_data);
688 return;
689 }
690
691 /* Delay if requested at end of transfer */
692 if (message->state == RUNNING_STATE) {
693 previous = list_entry(transfer->transfer_list.prev,
694 struct spi_transfer, transfer_list);
695 if (previous->delay_usecs)
696 udelay(previous->delay_usecs);
697 }
698
699 /* Setup the transfer state based on the type of transfer */
700 if (flush(drv_data) == 0) {
701 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
702 message->status = -EIO;
703 giveback(drv_data);
704 return;
705 }
706
707 if (transfer->tx_buf != NULL) {
708 drv_data->tx = (void *)transfer->tx_buf;
709 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 710 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
711 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 712 } else {
713 drv_data->tx = NULL;
714 }
715
716 if (transfer->rx_buf != NULL) {
717 drv_data->rx = transfer->rx_buf;
718 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 719 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
720 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 721 } else {
722 drv_data->rx = NULL;
723 }
724
725 drv_data->rx_dma = transfer->rx_dma;
726 drv_data->tx_dma = transfer->tx_dma;
727 drv_data->len_in_bytes = transfer->len;
fad91c89 728 drv_data->cs_change = transfer->cs_change;
a5f6abd4 729
092e1fda
BW		 730 /* Bits per word setup */
731 switch (transfer->bits_per_word) {
732 case 8:
733 drv_data->n_bytes = 1;
734 width = CFG_SPI_WORDSIZE8;
735 drv_data->read = chip->cs_change_per_word ?
736 u8_cs_chg_reader : u8_reader;
737 drv_data->write = chip->cs_change_per_word ?
738 u8_cs_chg_writer : u8_writer;
739 drv_data->duplex = chip->cs_change_per_word ?
740 u8_cs_chg_duplex : u8_duplex;
741 break;
742
743 case 16:
744 drv_data->n_bytes = 2;
745 width = CFG_SPI_WORDSIZE16;
746 drv_data->read = chip->cs_change_per_word ?
747 u16_cs_chg_reader : u16_reader;
748 drv_data->write = chip->cs_change_per_word ?
749 u16_cs_chg_writer : u16_writer;
750 drv_data->duplex = chip->cs_change_per_word ?
751 u16_cs_chg_duplex : u16_duplex;
752 break;
753
754 default:
755 /* No change, the same as default setting */
756 drv_data->n_bytes = chip->n_bytes;
757 width = chip->width;
758 drv_data->write = drv_data->tx ? chip->write : null_writer;
759 drv_data->read = drv_data->rx ? chip->read : null_reader;
760 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
761 break;
762 }
763 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
764 cr |= (width << 8);
765 write_CTRL(drv_data, cr);
766
a5f6abd4
WB		 767 if (width == CFG_SPI_WORDSIZE16) {
768 drv_data->len = (transfer->len) >> 1;
769 } else {
770 drv_data->len = transfer->len;
771 }
131b17d4
BW		 772 dev_dbg(&drv_data->pdev->dev, "transfer: ",
773 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
774 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 775
776 /* speed and width has been set on per message */
777 message->state = RUNNING_STATE;
778 dma_config = 0;
779
092e1fda
BW		 780 /* Speed setup (surely valid because already checked) */
781 if (transfer->speed_hz)
782 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
783 else
784 write_BAUD(drv_data, chip->baud);
785
bb90eb00
BW		 786 write_STAT(drv_data, BIT_STAT_CLR);
787 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
788 cs_active(drv_data, chip);
a5f6abd4 789
88b40369
BW		 790 dev_dbg(&drv_data->pdev->dev,
791 "now pumping a transfer: width is %d, len is %d\n",
792 width, transfer->len);
a5f6abd4
WB		 793
794 /*
795 * Try to map dma buffer and do a dma transfer if
796 * successful use different way to r/w according to
797 * drv_data->cur_chip->enable_dma
798 */
799 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
800
bb90eb00
BW		 801 disable_dma(drv_data->dma_channel);
802 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 803 bfin_spi_disable(drv_data);
a5f6abd4
WB		 804
805 /* config dma channel */
88b40369 806 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 807 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 808 set_dma_x_count(drv_data->dma_channel, drv_data->len);
809 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 810 dma_width = WDSIZE_16;
811 } else {
bb90eb00
BW		 812 set_dma_x_count(drv_data->dma_channel, drv_data->len);
813 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 814 dma_width = WDSIZE_8;
815 }
816
3f479a65 817 /* poll for SPI completion before start */
bb90eb00 818 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 819 cpu_relax();
3f479a65 820
a5f6abd4
WB		 821 /* dirty hack for autobuffer DMA mode */
822 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 823 dev_dbg(&drv_data->pdev->dev,
824 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 825
826 /* no irq in autobuffer mode */
827 dma_config =
828 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 829 set_dma_config(drv_data->dma_channel, dma_config);
830 set_dma_start_addr(drv_data->dma_channel,
a32c691d 831 (unsigned long)drv_data->tx);
bb90eb00 832 enable_dma(drv_data->dma_channel);
a5f6abd4 833
07612e5f
SZ		 834 /* start SPI transfer */
835 write_CTRL(drv_data,
836 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
837
838 /* just return here, there can only be one transfer
839 * in this mode
840 */
a5f6abd4
WB		 841 message->status = 0;
842 giveback(drv_data);
843 return;
844 }
845
846 /* In dma mode, rx or tx must be NULL in one transfer */
847 if (drv_data->rx != NULL) {
848 /* set transfer mode, and enable SPI */
88b40369 849 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 850
a5f6abd4 851 /* clear tx reg soformer data is not shifted out */
bb90eb00 852 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 853
bb90eb00 854 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 855
856 /* start dma */
bb90eb00 857 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 858 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 859 set_dma_config(drv_data->dma_channel, dma_config);
860 set_dma_start_addr(drv_data->dma_channel,
a32c691d 861 (unsigned long)drv_data->rx);
bb90eb00 862 enable_dma(drv_data->dma_channel);
a5f6abd4 863
07612e5f
SZ		 864 /* start SPI transfer */
865 write_CTRL(drv_data,
866 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
867
a5f6abd4 868 } else if (drv_data->tx != NULL) {
88b40369 869 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4
WB		 870
871 /* start dma */
bb90eb00 872 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 873 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 874 set_dma_config(drv_data->dma_channel, dma_config);
875 set_dma_start_addr(drv_data->dma_channel,
a32c691d 876 (unsigned long)drv_data->tx);
bb90eb00 877 enable_dma(drv_data->dma_channel);
07612e5f
SZ		 878
879 /* start SPI transfer */
880 write_CTRL(drv_data,
881 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
a5f6abd4
WB		 882 }
883 } else {
884 /* IO mode write then read */
88b40369 885 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 886
a5f6abd4
WB		 887 if (drv_data->tx != NULL && drv_data->rx != NULL) {
888 /* full duplex mode */
889 BUG_ON((drv_data->tx_end - drv_data->tx) !=
890 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 891 dev_dbg(&drv_data->pdev->dev,
892 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 893
cc487e73 894 /* set SPI transfer mode */
bb90eb00 895 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 896
897 drv_data->duplex(drv_data);
898
899 if (drv_data->tx != drv_data->tx_end)
900 tranf_success = 0;
901 } else if (drv_data->tx != NULL) {
902 /* write only half duplex */
131b17d4 903 dev_dbg(&drv_data->pdev->dev,
88b40369 904 "IO write: cr is 0x%x\n", cr);
a5f6abd4 905
cc487e73 906 /* set SPI transfer mode */
bb90eb00 907 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 908
909 drv_data->write(drv_data);
910
911 if (drv_data->tx != drv_data->tx_end)
912 tranf_success = 0;
913 } else if (drv_data->rx != NULL) {
914 /* read only half duplex */
131b17d4 915 dev_dbg(&drv_data->pdev->dev,
88b40369 916 "IO read: cr is 0x%x\n", cr);
a5f6abd4 917
cc487e73 918 /* set SPI transfer mode */
bb90eb00 919 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 920
921 drv_data->read(drv_data);
922 if (drv_data->rx != drv_data->rx_end)
923 tranf_success = 0;
924 }
925
926 if (!tranf_success) {
131b17d4 927 dev_dbg(&drv_data->pdev->dev,
88b40369 928 "IO write error!\n");
a5f6abd4
WB		 929 message->state = ERROR_STATE;
930 } else {
931 /* Update total byte transfered */
932 message->actual_length += drv_data->len;
933
934 /* Move to next transfer of this msg */
935 message->state = next_transfer(drv_data);
936 }
937
938 /* Schedule next transfer tasklet */
939 tasklet_schedule(&drv_data->pump_transfers);
940
941 }
942}
943
944/* pop a msg from queue and kick off real transfer */
945static void pump_messages(struct work_struct *work)
946{
131b17d4 947 struct driver_data *drv_data;
a5f6abd4
WB		 948 unsigned long flags;
949
131b17d4
BW		 950 drv_data = container_of(work, struct driver_data, pump_messages);
951
a5f6abd4
WB		 952 /* Lock queue and check for queue work */
953 spin_lock_irqsave(&drv_data->lock, flags);
954 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
955 /* pumper kicked off but no work to do */
956 drv_data->busy = 0;
957 spin_unlock_irqrestore(&drv_data->lock, flags);
958 return;
959 }
960
961 /* Make sure we are not already running a message */
962 if (drv_data->cur_msg) {
963 spin_unlock_irqrestore(&drv_data->lock, flags);
964 return;
965 }
966
967 /* Extract head of queue */
968 drv_data->cur_msg = list_entry(drv_data->queue.next,
969 struct spi_message, queue);
5fec5b5a
BW		 970
971 /* Setup the SSP using the per chip configuration */
972 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 973 restore_state(drv_data);
5fec5b5a 974
a5f6abd4
WB		 975 list_del_init(&drv_data->cur_msg->queue);
976
977 /* Initial message state */
978 drv_data->cur_msg->state = START_STATE;
979 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
980 struct spi_transfer, transfer_list);
981
5fec5b5a
BW		 982 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
983 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
984 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
985 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 986
987 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 988 "the first transfer len is %d\n",
989 drv_data->cur_transfer->len);
a5f6abd4
WB		 990
991 /* Mark as busy and launch transfers */
992 tasklet_schedule(&drv_data->pump_transfers);
993
994 drv_data->busy = 1;
995 spin_unlock_irqrestore(&drv_data->lock, flags);
996}
997
998/*
999 * got a msg to transfer, queue it in drv_data->queue.
1000 * And kick off message pumper
1001 */
1002static int transfer(struct spi_device *spi, struct spi_message *msg)
1003{
1004 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1005 unsigned long flags;
1006
1007 spin_lock_irqsave(&drv_data->lock, flags);
1008
1009 if (drv_data->run == QUEUE_STOPPED) {
1010 spin_unlock_irqrestore(&drv_data->lock, flags);
1011 return -ESHUTDOWN;
1012 }
1013
1014 msg->actual_length = 0;
1015 msg->status = -EINPROGRESS;
1016 msg->state = START_STATE;
1017
88b40369 1018 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 1019 list_add_tail(&msg->queue, &drv_data->queue);
1020
1021 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1022 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1023
1024 spin_unlock_irqrestore(&drv_data->lock, flags);
1025
1026 return 0;
1027}
1028
12e17c42
SZ		 1029#define MAX_SPI_SSEL 7
1030
1031static u16 ssel[3][MAX_SPI_SSEL] = {
1032 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1033 P_SPI0_SSEL4, P_SPI0_SSEL5,
1034 P_SPI0_SSEL6, P_SPI0_SSEL7},
1035
1036 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1037 P_SPI1_SSEL4, P_SPI1_SSEL5,
1038 P_SPI1_SSEL6, P_SPI1_SSEL7},
1039
1040 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1041 P_SPI2_SSEL4, P_SPI2_SSEL5,
1042 P_SPI2_SSEL6, P_SPI2_SSEL7},
1043};
1044
a5f6abd4
WB		 1045/* first setup for new devices */
1046static int setup(struct spi_device *spi)
1047{
1048 struct bfin5xx_spi_chip *chip_info = NULL;
1049 struct chip_data *chip;
1050 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1051 u8 spi_flg;
1052
1053 /* Abort device setup if requested features are not supported */
1054 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1055 dev_err(&spi->dev, "requested mode not fully supported\n");
1056 return -EINVAL;
1057 }
1058
1059 /* Zero (the default) here means 8 bits */
1060 if (!spi->bits_per_word)
1061 spi->bits_per_word = 8;
1062
1063 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1064 return -EINVAL;
1065
1066 /* Only alloc (or use chip_info) on first setup */
1067 chip = spi_get_ctldata(spi);
1068 if (chip == NULL) {
1069 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1070 if (!chip)
1071 return -ENOMEM;
1072
1073 chip->enable_dma = 0;
1074 chip_info = spi->controller_data;
1075 }
1076
1077 /* chip_info isn't always needed */
1078 if (chip_info) {
2ed35516
MF		 1079 /* Make sure people stop trying to set fields via ctl_reg
1080 * when they should actually be using common SPI framework.
1081 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1082 * Not sure if a user actually needs/uses any of these,
1083 * but let's assume (for now) they do.
1084 */
1085 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1086 dev_err(&spi->dev, "do not set bits in ctl_reg "
1087 "that the SPI framework manages\n");
1088 return -EINVAL;
1089 }
1090
a5f6abd4
WB		 1091 chip->enable_dma = chip_info->enable_dma != 0
1092 && drv_data->master_info->enable_dma;
1093 chip->ctl_reg = chip_info->ctl_reg;
1094 chip->bits_per_word = chip_info->bits_per_word;
1095 chip->cs_change_per_word = chip_info->cs_change_per_word;
1096 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1097 }
1098
1099 /* translate common spi framework into our register */
1100 if (spi->mode & SPI_CPOL)
1101 chip->ctl_reg |= CPOL;
1102 if (spi->mode & SPI_CPHA)
1103 chip->ctl_reg |= CPHA;
1104 if (spi->mode & SPI_LSB_FIRST)
1105 chip->ctl_reg |= LSBF;
1106 /* we dont support running in slave mode (yet?) */
1107 chip->ctl_reg |= MSTR;
1108
1109 /*
1110 * if any one SPI chip is registered and wants DMA, request the
1111 * DMA channel for it
1112 */
bb90eb00 1113 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1114 /* register dma irq handler */
bb90eb00 1115 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1116 dev_dbg(&spi->dev,
1117 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1118 return -ENODEV;
1119 }
bb90eb00
BW		 1120 if (set_dma_callback(drv_data->dma_channel,
1121 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1122 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1123 return -EPERM;
1124 }
bb90eb00
BW		 1125 dma_disable_irq(drv_data->dma_channel);
1126 drv_data->dma_requested = 1;
a5f6abd4
WB		 1127 }
1128
1129 /*
1130 * Notice: for blackfin, the speed_hz is the value of register
1131 * SPI_BAUD, not the real baudrate
1132 */
1133 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1134 spi_flg = ~(1 << (spi->chip_select));
1135 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1136 chip->chip_select_num = spi->chip_select;
1137
1138 switch (chip->bits_per_word) {
1139 case 8:
1140 chip->n_bytes = 1;
1141 chip->width = CFG_SPI_WORDSIZE8;
1142 chip->read = chip->cs_change_per_word ?
1143 u8_cs_chg_reader : u8_reader;
1144 chip->write = chip->cs_change_per_word ?
1145 u8_cs_chg_writer : u8_writer;
1146 chip->duplex = chip->cs_change_per_word ?
1147 u8_cs_chg_duplex : u8_duplex;
1148 break;
1149
1150 case 16:
1151 chip->n_bytes = 2;
1152 chip->width = CFG_SPI_WORDSIZE16;
1153 chip->read = chip->cs_change_per_word ?
1154 u16_cs_chg_reader : u16_reader;
1155 chip->write = chip->cs_change_per_word ?
1156 u16_cs_chg_writer : u16_writer;
1157 chip->duplex = chip->cs_change_per_word ?
1158 u16_cs_chg_duplex : u16_duplex;
1159 break;
1160
1161 default:
1162 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1163 chip->bits_per_word);
1164 kfree(chip);
1165 return -ENODEV;
1166 }
1167
898eb71c 1168 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1169 spi->modalias, chip->width, chip->enable_dma);
88b40369 1170 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1171 chip->ctl_reg, chip->flag);
1172
1173 spi_set_ctldata(spi, chip);
1174
12e17c42
SZ		 1175 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1176 if ((chip->chip_select_num > 0)
1177 && (chip->chip_select_num <= spi->master->num_chipselect))
1178 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1179 [chip->chip_select_num-1], spi->modalias);
12e17c42 1180
07612e5f
SZ		 1181 cs_deactive(drv_data, chip);
1182
a5f6abd4
WB		 1183 return 0;
1184}
1185
1186/*
1187 * callback for spi framework.
1188 * clean driver specific data
1189 */
88b40369 1190static void cleanup(struct spi_device *spi)
a5f6abd4 1191{
27bb9e79 1192 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1193
12e17c42
SZ		 1194 if ((chip->chip_select_num > 0)
1195 && (chip->chip_select_num <= spi->master->num_chipselect))
1196 peripheral_free(ssel[spi->master->bus_num]
1197 [chip->chip_select_num-1]);
1198
a5f6abd4
WB		 1199 kfree(chip);
1200}
1201
1202static inline int init_queue(struct driver_data *drv_data)
1203{
1204 INIT_LIST_HEAD(&drv_data->queue);
1205 spin_lock_init(&drv_data->lock);
1206
1207 drv_data->run = QUEUE_STOPPED;
1208 drv_data->busy = 0;
1209
1210 /* init transfer tasklet */
1211 tasklet_init(&drv_data->pump_transfers,
1212 pump_transfers, (unsigned long)drv_data);
1213
1214 /* init messages workqueue */
1215 INIT_WORK(&drv_data->pump_messages, pump_messages);
1216 drv_data->workqueue =
49dce689 1217 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
a5f6abd4
WB		 1218 if (drv_data->workqueue == NULL)
1219 return -EBUSY;
1220
1221 return 0;
1222}
1223
1224static inline int start_queue(struct driver_data *drv_data)
1225{
1226 unsigned long flags;
1227
1228 spin_lock_irqsave(&drv_data->lock, flags);
1229
1230 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1231 spin_unlock_irqrestore(&drv_data->lock, flags);
1232 return -EBUSY;
1233 }
1234
1235 drv_data->run = QUEUE_RUNNING;
1236 drv_data->cur_msg = NULL;
1237 drv_data->cur_transfer = NULL;
1238 drv_data->cur_chip = NULL;
1239 spin_unlock_irqrestore(&drv_data->lock, flags);
1240
1241 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1242
1243 return 0;
1244}
1245
1246static inline int stop_queue(struct driver_data *drv_data)
1247{
1248 unsigned long flags;
1249 unsigned limit = 500;
1250 int status = 0;
1251
1252 spin_lock_irqsave(&drv_data->lock, flags);
1253
1254 /*
1255 * This is a bit lame, but is optimized for the common execution path.
1256 * A wait_queue on the drv_data->busy could be used, but then the common
1257 * execution path (pump_messages) would be required to call wake_up or
1258 * friends on every SPI message. Do this instead
1259 */
1260 drv_data->run = QUEUE_STOPPED;
1261 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1262 spin_unlock_irqrestore(&drv_data->lock, flags);
1263 msleep(10);
1264 spin_lock_irqsave(&drv_data->lock, flags);
1265 }
1266
1267 if (!list_empty(&drv_data->queue) || drv_data->busy)
1268 status = -EBUSY;
1269
1270 spin_unlock_irqrestore(&drv_data->lock, flags);
1271
1272 return status;
1273}
1274
1275static inline int destroy_queue(struct driver_data *drv_data)
1276{
1277 int status;
1278
1279 status = stop_queue(drv_data);
1280 if (status != 0)
1281 return status;
1282
1283 destroy_workqueue(drv_data->workqueue);
1284
1285 return 0;
1286}
1287
1288static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1289{
1290 struct device *dev = &pdev->dev;
1291 struct bfin5xx_spi_master *platform_info;
1292 struct spi_master *master;
1293 struct driver_data *drv_data = 0;
a32c691d 1294 struct resource *res;
a5f6abd4
WB		 1295 int status = 0;
1296
1297 platform_info = dev->platform_data;
1298
1299 /* Allocate master with space for drv_data */
1300 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1301 if (!master) {
1302 dev_err(&pdev->dev, "can not alloc spi_master\n");
1303 return -ENOMEM;
1304 }
131b17d4 1305
a5f6abd4
WB		 1306 drv_data = spi_master_get_devdata(master);
1307 drv_data->master = master;
1308 drv_data->master_info = platform_info;
1309 drv_data->pdev = pdev;
003d9226 1310 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1311
1312 master->bus_num = pdev->id;
1313 master->num_chipselect = platform_info->num_chipselect;
1314 master->cleanup = cleanup;
1315 master->setup = setup;
1316 master->transfer = transfer;
1317
a32c691d
BW		 1318 /* Find and map our resources */
1319 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1320 if (res == NULL) {
1321 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1322 status = -ENOENT;
1323 goto out_error_get_res;
1324 }
1325
f452126c
BW		 1326 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1327 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1328 dev_err(dev, "Cannot map IO\n");
1329 status = -ENXIO;
1330 goto out_error_ioremap;
1331 }
1332
bb90eb00
BW		 1333 drv_data->dma_channel = platform_get_irq(pdev, 0);
1334 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1335 dev_err(dev, "No DMA channel specified\n");
1336 status = -ENOENT;
1337 goto out_error_no_dma_ch;
1338 }
1339
a5f6abd4
WB		 1340 /* Initial and start queue */
1341 status = init_queue(drv_data);
1342 if (status != 0) {
a32c691d 1343 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1344 goto out_error_queue_alloc;
1345 }
a32c691d 1346
a5f6abd4
WB		 1347 status = start_queue(drv_data);
1348 if (status != 0) {
a32c691d 1349 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1350 goto out_error_queue_alloc;
1351 }
1352
1353 /* Register with the SPI framework */
1354 platform_set_drvdata(pdev, drv_data);
1355 status = spi_register_master(master);
1356 if (status != 0) {
a32c691d 1357 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1358 goto out_error_queue_alloc;
1359 }
a32c691d 1360
003d9226
BW		 1361 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1362 if (status != 0) {
7c4ef094
SZ		 1363 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1364 goto out_error;
1365 }
1366
f452126c 1367 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1368 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1369 drv_data->dma_channel);
a5f6abd4
WB		 1370 return status;
1371
cc2f81a6 1372out_error_queue_alloc:
a5f6abd4 1373 destroy_queue(drv_data);
a32c691d 1374out_error_no_dma_ch:
bb90eb00 1375 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1376out_error_ioremap:
1377out_error_get_res:
cc2f81a6 1378out_error:
a5f6abd4 1379 spi_master_put(master);
cc2f81a6 1380
a5f6abd4
WB		 1381 return status;
1382}
1383
1384/* stop hardware and remove the driver */
1385static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1386{
1387 struct driver_data *drv_data = platform_get_drvdata(pdev);
1388 int status = 0;
1389
1390 if (!drv_data)
1391 return 0;
1392
1393 /* Remove the queue */
1394 status = destroy_queue(drv_data);
1395 if (status != 0)
1396 return status;
1397
1398 /* Disable the SSP at the peripheral and SOC level */
1399 bfin_spi_disable(drv_data);
1400
1401 /* Release DMA */
1402 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1403 if (dma_channel_active(drv_data->dma_channel))
1404 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1405 }
1406
1407 /* Disconnect from the SPI framework */
1408 spi_unregister_master(drv_data->master);
1409
003d9226 1410 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1411
a5f6abd4
WB		 1412 /* Prevent double remove */
1413 platform_set_drvdata(pdev, NULL);
1414
1415 return 0;
1416}
1417
1418#ifdef CONFIG_PM
1419static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1420{
1421 struct driver_data *drv_data = platform_get_drvdata(pdev);
1422 int status = 0;
1423
1424 status = stop_queue(drv_data);
1425 if (status != 0)
1426 return status;
1427
1428 /* stop hardware */
1429 bfin_spi_disable(drv_data);
1430
1431 return 0;
1432}
1433
1434static int bfin5xx_spi_resume(struct platform_device *pdev)
1435{
1436 struct driver_data *drv_data = platform_get_drvdata(pdev);
1437 int status = 0;
1438
1439 /* Enable the SPI interface */
1440 bfin_spi_enable(drv_data);
1441
1442 /* Start the queue running */
1443 status = start_queue(drv_data);
1444 if (status != 0) {
1445 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1446 return status;
1447 }
1448
1449 return 0;
1450}
1451#else
1452#define bfin5xx_spi_suspend NULL
1453#define bfin5xx_spi_resume NULL
1454#endif /* CONFIG_PM */
1455
fc3ba952 1456MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
a5f6abd4 1457static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1458 .driver = {
a32c691d 1459 .name = DRV_NAME,
88b40369
BW		 1460 .owner = THIS_MODULE,
1461 },
1462 .suspend = bfin5xx_spi_suspend,
1463 .resume = bfin5xx_spi_resume,
1464 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1465};
1466
1467static int __init bfin5xx_spi_init(void)
1468{
88b40369 1469 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1470}
a5f6abd4
WB		 1471module_init(bfin5xx_spi_init);
1472
1473static void __exit bfin5xx_spi_exit(void)
1474{
1475 platform_driver_unregister(&bfin5xx_spi_driver);
1476}
a5f6abd4 1477module_exit(bfin5xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)