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spi_bfin: wait for tx to complete on write paths
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
131b17d4
BW		 2 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
a5f6abd4 7 *
131b17d4
BW		 8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
a5f6abd4
WB		 11 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
131b17d4 15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
a32c691d
BW		 16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
a5f6abd4 18 *
131b17d4 19 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4
WB		 20 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37#include <linux/init.h>
38#include <linux/module.h>
131b17d4 39#include <linux/delay.h>
a5f6abd4 40#include <linux/device.h>
131b17d4 41#include <linux/io.h>
a5f6abd4 42#include <linux/ioport.h>
131b17d4 43#include <linux/irq.h>
a5f6abd4
WB		 44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/spi/spi.h>
49#include <linux/workqueue.h>
a5f6abd4 50
a5f6abd4 51#include <asm/dma.h>
131b17d4 52#include <asm/portmux.h>
a5f6abd4
WB		 53#include <asm/bfin5xx_spi.h>
54
a32c691d
BW		 55#define DRV_NAME "bfin-spi"
56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 57#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 58#define DRV_VERSION "1.0"
59
60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 62MODULE_LICENSE("GPL");
63
bb90eb00 64#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 65
bb90eb00
BW		 66#define START_STATE ((void *)0)
67#define RUNNING_STATE ((void *)1)
68#define DONE_STATE ((void *)2)
69#define ERROR_STATE ((void *)-1)
70#define QUEUE_RUNNING 0
71#define QUEUE_STOPPED 1
a5f6abd4
WB		 72
73struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
bb90eb00 80 /* Regs base of SPI controller */
f452126c 81 void __iomem *regs_base;
bb90eb00 82
003d9226
BW		 83 /* Pin request list */
84 u16 *pin_req;
85
a5f6abd4
WB		 86 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info;
88
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
92 spinlock_t lock;
93 struct list_head queue;
94 int busy;
95 int run;
96
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
99
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
104 size_t len_in_bytes;
105 size_t len;
106 void *tx;
107 void *tx_end;
108 void *rx;
109 void *rx_end;
bb90eb00
BW		 110
111 /* DMA stuffs */
112 int dma_channel;
a5f6abd4 113 int dma_mapped;
bb90eb00 114 int dma_requested;
a5f6abd4
WB		 115 dma_addr_t rx_dma;
116 dma_addr_t tx_dma;
bb90eb00 117
a5f6abd4
WB		 118 size_t rx_map_len;
119 size_t tx_map_len;
120 u8 n_bytes;
fad91c89 121 int cs_change;
a5f6abd4
WB		 122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
125};
126
127struct chip_data {
128 u16 ctl_reg;
129 u16 baud;
130 u16 flag;
131
132 u8 chip_select_num;
133 u8 n_bytes;
88b40369 134 u8 width; /* 0 or 1 */
a5f6abd4
WB		 135 u8 enable_dma;
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
62310e51 138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
142};
143
bb90eb00
BW		 144#define DEFINE_SPI_REG(reg, off) \
145static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150DEFINE_SPI_REG(CTRL, 0x00)
151DEFINE_SPI_REG(FLAG, 0x04)
152DEFINE_SPI_REG(STAT, 0x08)
153DEFINE_SPI_REG(TDBR, 0x0C)
154DEFINE_SPI_REG(RDBR, 0x10)
155DEFINE_SPI_REG(BAUD, 0x14)
156DEFINE_SPI_REG(SHAW, 0x18)
157
88b40369 158static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 159{
160 u16 cr;
161
bb90eb00
BW		 162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 164}
165
88b40369 166static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 167{
168 u16 cr;
169
bb90eb00
BW		 170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 172}
173
174/* Caculate the SPI_BAUD register value based on input HZ */
175static u16 hz_to_spi_baud(u32 speed_hz)
176{
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
179
180 if ((sclk % (2 * speed_hz)) > 0)
181 spi_baud++;
182
a5f6abd4
WB		 183 return spi_baud;
184}
185
186static int flush(struct driver_data *drv_data)
187{
188 unsigned long limit = loops_per_jiffy << 1;
189
190 /* wait for stop and clear stat */
bb90eb00 191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 192 cpu_relax();
a5f6abd4 193
bb90eb00 194 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 195
196 return limit;
197}
198
fad91c89 199/* Chip select operation functions for cs_change flag */
bb90eb00 200static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 201{
bb90eb00 202 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
bb90eb00 207 write_FLAG(drv_data, flag);
fad91c89
BW		 208}
209
bb90eb00 210static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 211{
bb90eb00 212 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 213
214 flag |= (chip->flag << 8);
215
bb90eb00 216 write_FLAG(drv_data, flag);
62310e51
BW		 217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
fad91c89
BW		 221}
222
7c4ef094 223#define MAX_SPI_SSEL 7
5fec5b5a 224
a5f6abd4 225/* stop controller and re-config current chip*/
8d20d0a7 226static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 227{
228 struct chip_data *chip = drv_data->cur_chip;
12e17c42 229
a5f6abd4 230 /* Clear status and disable clock */
bb90eb00 231 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 232 bfin_spi_disable(drv_data);
88b40369 233 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 234
5fec5b5a 235 /* Load the registers */
bb90eb00 236 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 237 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 238
239 bfin_spi_enable(drv_data);
07612e5f 240 cs_active(drv_data, chip);
a5f6abd4
WB		 241}
242
243/* used to kick off transfer in rx mode */
bb90eb00 244static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 245{
246 unsigned short tmp;
bb90eb00 247 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 248 return tmp;
249}
250
251static void null_writer(struct driver_data *drv_data)
252{
253 u8 n_bytes = drv_data->n_bytes;
254
255 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 256 write_TDBR(drv_data, 0);
257 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 258 cpu_relax();
a5f6abd4
WB		 259 drv_data->tx += n_bytes;
260 }
261}
262
263static void null_reader(struct driver_data *drv_data)
264{
265 u8 n_bytes = drv_data->n_bytes;
bb90eb00 266 dummy_read(drv_data);
a5f6abd4
WB		 267
268 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 270 cpu_relax();
bb90eb00 271 dummy_read(drv_data);
a5f6abd4
WB		 272 drv_data->rx += n_bytes;
273 }
274}
275
276static void u8_writer(struct driver_data *drv_data)
277{
131b17d4 278 dev_dbg(&drv_data->pdev->dev,
bb90eb00 279 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 280
a5f6abd4 281 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 282 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
283 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 284 cpu_relax();
a5f6abd4
WB		 285 ++drv_data->tx;
286 }
13f3e642
SZ		 287
288 /* poll for SPI completion before return */
289 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
290 cpu_relax();
a5f6abd4
WB		 291}
292
293static void u8_cs_chg_writer(struct driver_data *drv_data)
294{
295 struct chip_data *chip = drv_data->cur_chip;
296
297 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 298 cs_active(drv_data, chip);
a5f6abd4 299
bb90eb00
BW		 300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
301 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 302 cpu_relax();
e26aa015
BW		 303 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
304 cpu_relax();
62310e51 305
bb90eb00 306 cs_deactive(drv_data, chip);
5fec5b5a 307
a5f6abd4
WB		 308 ++drv_data->tx;
309 }
a5f6abd4
WB		 310}
311
312static void u8_reader(struct driver_data *drv_data)
313{
131b17d4 314 dev_dbg(&drv_data->pdev->dev,
bb90eb00 315 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 316
3f479a65 317 /* poll for SPI completion before start */
bb90eb00 318 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 319 cpu_relax();
3f479a65 320
a5f6abd4 321 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 322 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 323
bb90eb00 324 dummy_read(drv_data);
cc487e73 325
a5f6abd4 326 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 327 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 328 cpu_relax();
bb90eb00 329 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 330 ++drv_data->rx;
331 }
332
bb90eb00 333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 334 cpu_relax();
bb90eb00 335 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 336 ++drv_data->rx;
337}
338
339static void u8_cs_chg_reader(struct driver_data *drv_data)
340{
341 struct chip_data *chip = drv_data->cur_chip;
342
e26aa015
BW		 343 while (drv_data->rx < drv_data->rx_end) {
344 cs_active(drv_data, chip);
345 read_RDBR(drv_data); /* kick off */
a5f6abd4 346
e26aa015
BW		 347 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
348 cpu_relax();
349 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
350 cpu_relax();
cc487e73 351
e26aa015 352 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 353 cs_deactive(drv_data, chip);
5fec5b5a 354
a5f6abd4
WB		 355 ++drv_data->rx;
356 }
a5f6abd4
WB		 357}
358
359static void u8_duplex(struct driver_data *drv_data)
360{
361 /* in duplex mode, clk is triggered by writing of TDBR */
362 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 363 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
4fd432d9 364 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 365 cpu_relax();
bb90eb00 366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 367 cpu_relax();
bb90eb00 368 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 369 ++drv_data->rx;
370 ++drv_data->tx;
371 }
372}
373
374static void u8_cs_chg_duplex(struct driver_data *drv_data)
375{
376 struct chip_data *chip = drv_data->cur_chip;
377
378 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 379 cs_active(drv_data, chip);
5fec5b5a 380
bb90eb00 381 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 382
383 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 384 cpu_relax();
bb90eb00 385 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 386 cpu_relax();
bb90eb00 387 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 388
bb90eb00 389 cs_deactive(drv_data, chip);
5fec5b5a 390
a5f6abd4
WB		 391 ++drv_data->rx;
392 ++drv_data->tx;
393 }
a5f6abd4
WB		 394}
395
396static void u16_writer(struct driver_data *drv_data)
397{
131b17d4 398 dev_dbg(&drv_data->pdev->dev,
bb90eb00 399 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 400
a5f6abd4 401 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 402 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
403 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 404 cpu_relax();
a5f6abd4
WB		 405 drv_data->tx += 2;
406 }
13f3e642
SZ		 407
408 /* poll for SPI completion before return */
409 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
410 cpu_relax();
a5f6abd4
WB		 411}
412
413static void u16_cs_chg_writer(struct driver_data *drv_data)
414{
415 struct chip_data *chip = drv_data->cur_chip;
416
417 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 418 cs_active(drv_data, chip);
a5f6abd4 419
bb90eb00
BW		 420 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
421 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 422 cpu_relax();
13f3e642
SZ		 423 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
424 cpu_relax();
62310e51 425
bb90eb00 426 cs_deactive(drv_data, chip);
5fec5b5a 427
a5f6abd4
WB		 428 drv_data->tx += 2;
429 }
a5f6abd4
WB		 430}
431
432static void u16_reader(struct driver_data *drv_data)
433{
88b40369 434 dev_dbg(&drv_data->pdev->dev,
bb90eb00 435 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 436
3f479a65 437 /* poll for SPI completion before start */
bb90eb00 438 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 439 cpu_relax();
3f479a65 440
cc487e73 441 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 442 write_TDBR(drv_data, 0xFFFF);
cc487e73 443
bb90eb00 444 dummy_read(drv_data);
a5f6abd4
WB		 445
446 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 447 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 448 cpu_relax();
bb90eb00 449 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 450 drv_data->rx += 2;
451 }
452
bb90eb00 453 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 454 cpu_relax();
bb90eb00 455 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 456 drv_data->rx += 2;
457}
458
459static void u16_cs_chg_reader(struct driver_data *drv_data)
460{
461 struct chip_data *chip = drv_data->cur_chip;
462
3f479a65 463 /* poll for SPI completion before start */
bb90eb00 464 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 465 cpu_relax();
3f479a65 466
cc487e73 467 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 468 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 469
bb90eb00
BW		 470 cs_active(drv_data, chip);
471 dummy_read(drv_data);
cc487e73 472
c3061abb 473 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 474 cs_deactive(drv_data, chip);
5fec5b5a 475
bb90eb00 476 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 477 cpu_relax();
bb90eb00
BW		 478 cs_active(drv_data, chip);
479 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 480 drv_data->rx += 2;
481 }
bb90eb00 482 cs_deactive(drv_data, chip);
cc487e73 483
bb90eb00 484 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 485 cpu_relax();
bb90eb00 486 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 487 drv_data->rx += 2;
a5f6abd4
WB		 488}
489
490static void u16_duplex(struct driver_data *drv_data)
491{
492 /* in duplex mode, clk is triggered by writing of TDBR */
493 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 494 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 495 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 496 cpu_relax();
bb90eb00 497 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 498 cpu_relax();
bb90eb00 499 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 500 drv_data->rx += 2;
501 drv_data->tx += 2;
502 }
503}
504
505static void u16_cs_chg_duplex(struct driver_data *drv_data)
506{
507 struct chip_data *chip = drv_data->cur_chip;
508
509 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 510 cs_active(drv_data, chip);
a5f6abd4 511
bb90eb00 512 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 513 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 514 cpu_relax();
bb90eb00 515 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 516 cpu_relax();
bb90eb00 517 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 518
bb90eb00 519 cs_deactive(drv_data, chip);
5fec5b5a 520
a5f6abd4
WB		 521 drv_data->rx += 2;
522 drv_data->tx += 2;
523 }
a5f6abd4
WB		 524}
525
526/* test if ther is more transfer to be done */
527static void *next_transfer(struct driver_data *drv_data)
528{
529 struct spi_message *msg = drv_data->cur_msg;
530 struct spi_transfer *trans = drv_data->cur_transfer;
531
532 /* Move to next transfer */
533 if (trans->transfer_list.next != &msg->transfers) {
534 drv_data->cur_transfer =
535 list_entry(trans->transfer_list.next,
536 struct spi_transfer, transfer_list);
537 return RUNNING_STATE;
538 } else
539 return DONE_STATE;
540}
541
542/*
543 * caller already set message->status;
544 * dma and pio irqs are blocked give finished message back
545 */
546static void giveback(struct driver_data *drv_data)
547{
fad91c89 548 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 549 struct spi_transfer *last_transfer;
550 unsigned long flags;
551 struct spi_message *msg;
552
553 spin_lock_irqsave(&drv_data->lock, flags);
554 msg = drv_data->cur_msg;
555 drv_data->cur_msg = NULL;
556 drv_data->cur_transfer = NULL;
557 drv_data->cur_chip = NULL;
558 queue_work(drv_data->workqueue, &drv_data->pump_messages);
559 spin_unlock_irqrestore(&drv_data->lock, flags);
560
561 last_transfer = list_entry(msg->transfers.prev,
562 struct spi_transfer, transfer_list);
563
564 msg->state = NULL;
565
566 /* disable chip select signal. And not stop spi in autobuffer mode */
567 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 568 cs_deactive(drv_data, chip);
a5f6abd4
WB		 569 bfin_spi_disable(drv_data);
570 }
571
fad91c89 572 if (!drv_data->cs_change)
bb90eb00 573 cs_deactive(drv_data, chip);
fad91c89 574
a5f6abd4
WB		 575 if (msg->complete)
576 msg->complete(msg->context);
577}
578
88b40369 579static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 580{
15aafa2f 581 struct driver_data *drv_data = dev_id;
fad91c89 582 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 583 struct spi_message *msg = drv_data->cur_msg;
a5f6abd4 584
88b40369 585 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 586 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 587
d6fe89b0 588 /* Wait for DMA to complete */
bb90eb00 589 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 590 cpu_relax();
d6fe89b0 591
a5f6abd4 592 /*
d6fe89b0
BW		 593 * wait for the last transaction shifted out. HRM states:
594 * at this point there may still be data in the SPI DMA FIFO waiting
595 * to be transmitted ... software needs to poll TXS in the SPI_STAT
596 * register until it goes low for 2 successive reads
a5f6abd4
WB		 597 */
598 if (drv_data->tx != NULL) {
bb90eb00
BW		 599 while ((read_STAT(drv_data) & TXS) ||
600 (read_STAT(drv_data) & TXS))
d8c05008 601 cpu_relax();
a5f6abd4
WB		 602 }
603
bb90eb00 604 while (!(read_STAT(drv_data) & SPIF))
d8c05008 605 cpu_relax();
a5f6abd4 606
a5f6abd4
WB		 607 msg->actual_length += drv_data->len_in_bytes;
608
fad91c89 609 if (drv_data->cs_change)
bb90eb00 610 cs_deactive(drv_data, chip);
fad91c89 611
a5f6abd4
WB		 612 /* Move to next transfer */
613 msg->state = next_transfer(drv_data);
614
615 /* Schedule transfer tasklet */
616 tasklet_schedule(&drv_data->pump_transfers);
617
618 /* free the irq handler before next transfer */
88b40369
BW		 619 dev_dbg(&drv_data->pdev->dev,
620 "disable dma channel irq%d\n",
bb90eb00
BW		 621 drv_data->dma_channel);
622 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 623
624 return IRQ_HANDLED;
625}
626
627static void pump_transfers(unsigned long data)
628{
629 struct driver_data *drv_data = (struct driver_data *)data;
630 struct spi_message *message = NULL;
631 struct spi_transfer *transfer = NULL;
632 struct spi_transfer *previous = NULL;
633 struct chip_data *chip = NULL;
88b40369
BW		 634 u8 width;
635 u16 cr, dma_width, dma_config;
a5f6abd4
WB		 636 u32 tranf_success = 1;
637
638 /* Get current state information */
639 message = drv_data->cur_msg;
640 transfer = drv_data->cur_transfer;
641 chip = drv_data->cur_chip;
092e1fda 642
a5f6abd4
WB		 643 /*
644 * if msg is error or done, report it back using complete() callback
645 */
646
647 /* Handle for abort */
648 if (message->state == ERROR_STATE) {
649 message->status = -EIO;
650 giveback(drv_data);
651 return;
652 }
653
654 /* Handle end of message */
655 if (message->state == DONE_STATE) {
656 message->status = 0;
657 giveback(drv_data);
658 return;
659 }
660
661 /* Delay if requested at end of transfer */
662 if (message->state == RUNNING_STATE) {
663 previous = list_entry(transfer->transfer_list.prev,
664 struct spi_transfer, transfer_list);
665 if (previous->delay_usecs)
666 udelay(previous->delay_usecs);
667 }
668
669 /* Setup the transfer state based on the type of transfer */
670 if (flush(drv_data) == 0) {
671 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
672 message->status = -EIO;
673 giveback(drv_data);
674 return;
675 }
676
677 if (transfer->tx_buf != NULL) {
678 drv_data->tx = (void *)transfer->tx_buf;
679 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 680 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
681 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 682 } else {
683 drv_data->tx = NULL;
684 }
685
686 if (transfer->rx_buf != NULL) {
687 drv_data->rx = transfer->rx_buf;
688 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 689 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
690 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 691 } else {
692 drv_data->rx = NULL;
693 }
694
695 drv_data->rx_dma = transfer->rx_dma;
696 drv_data->tx_dma = transfer->tx_dma;
697 drv_data->len_in_bytes = transfer->len;
fad91c89 698 drv_data->cs_change = transfer->cs_change;
a5f6abd4 699
092e1fda
BW		 700 /* Bits per word setup */
701 switch (transfer->bits_per_word) {
702 case 8:
703 drv_data->n_bytes = 1;
704 width = CFG_SPI_WORDSIZE8;
705 drv_data->read = chip->cs_change_per_word ?
706 u8_cs_chg_reader : u8_reader;
707 drv_data->write = chip->cs_change_per_word ?
708 u8_cs_chg_writer : u8_writer;
709 drv_data->duplex = chip->cs_change_per_word ?
710 u8_cs_chg_duplex : u8_duplex;
711 break;
712
713 case 16:
714 drv_data->n_bytes = 2;
715 width = CFG_SPI_WORDSIZE16;
716 drv_data->read = chip->cs_change_per_word ?
717 u16_cs_chg_reader : u16_reader;
718 drv_data->write = chip->cs_change_per_word ?
719 u16_cs_chg_writer : u16_writer;
720 drv_data->duplex = chip->cs_change_per_word ?
721 u16_cs_chg_duplex : u16_duplex;
722 break;
723
724 default:
725 /* No change, the same as default setting */
726 drv_data->n_bytes = chip->n_bytes;
727 width = chip->width;
728 drv_data->write = drv_data->tx ? chip->write : null_writer;
729 drv_data->read = drv_data->rx ? chip->read : null_reader;
730 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
731 break;
732 }
733 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
734 cr |= (width << 8);
735 write_CTRL(drv_data, cr);
736
a5f6abd4
WB		 737 if (width == CFG_SPI_WORDSIZE16) {
738 drv_data->len = (transfer->len) >> 1;
739 } else {
740 drv_data->len = transfer->len;
741 }
131b17d4
BW		 742 dev_dbg(&drv_data->pdev->dev, "transfer: ",
743 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
744 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 745
746 /* speed and width has been set on per message */
747 message->state = RUNNING_STATE;
748 dma_config = 0;
749
092e1fda
BW		 750 /* Speed setup (surely valid because already checked) */
751 if (transfer->speed_hz)
752 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
753 else
754 write_BAUD(drv_data, chip->baud);
755
bb90eb00
BW		 756 write_STAT(drv_data, BIT_STAT_CLR);
757 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
758 cs_active(drv_data, chip);
a5f6abd4 759
88b40369
BW		 760 dev_dbg(&drv_data->pdev->dev,
761 "now pumping a transfer: width is %d, len is %d\n",
762 width, transfer->len);
a5f6abd4
WB		 763
764 /*
765 * Try to map dma buffer and do a dma transfer if
766 * successful use different way to r/w according to
767 * drv_data->cur_chip->enable_dma
768 */
769 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
770
bb90eb00
BW		 771 disable_dma(drv_data->dma_channel);
772 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 773 bfin_spi_disable(drv_data);
a5f6abd4
WB		 774
775 /* config dma channel */
88b40369 776 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 777 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 778 set_dma_x_count(drv_data->dma_channel, drv_data->len);
779 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 780 dma_width = WDSIZE_16;
781 } else {
bb90eb00
BW		 782 set_dma_x_count(drv_data->dma_channel, drv_data->len);
783 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 784 dma_width = WDSIZE_8;
785 }
786
3f479a65 787 /* poll for SPI completion before start */
bb90eb00 788 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 789 cpu_relax();
3f479a65 790
a5f6abd4
WB		 791 /* dirty hack for autobuffer DMA mode */
792 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 793 dev_dbg(&drv_data->pdev->dev,
794 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 795
796 /* no irq in autobuffer mode */
797 dma_config =
798 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 799 set_dma_config(drv_data->dma_channel, dma_config);
800 set_dma_start_addr(drv_data->dma_channel,
a32c691d 801 (unsigned long)drv_data->tx);
bb90eb00 802 enable_dma(drv_data->dma_channel);
a5f6abd4 803
07612e5f
SZ		 804 /* start SPI transfer */
805 write_CTRL(drv_data,
806 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
807
808 /* just return here, there can only be one transfer
809 * in this mode
810 */
a5f6abd4
WB		 811 message->status = 0;
812 giveback(drv_data);
813 return;
814 }
815
816 /* In dma mode, rx or tx must be NULL in one transfer */
817 if (drv_data->rx != NULL) {
818 /* set transfer mode, and enable SPI */
88b40369 819 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 820
a5f6abd4 821 /* clear tx reg soformer data is not shifted out */
bb90eb00 822 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 823
bb90eb00 824 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 825
826 /* start dma */
bb90eb00 827 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 828 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 829 set_dma_config(drv_data->dma_channel, dma_config);
830 set_dma_start_addr(drv_data->dma_channel,
a32c691d 831 (unsigned long)drv_data->rx);
bb90eb00 832 enable_dma(drv_data->dma_channel);
a5f6abd4 833
07612e5f
SZ		 834 /* start SPI transfer */
835 write_CTRL(drv_data,
836 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
837
a5f6abd4 838 } else if (drv_data->tx != NULL) {
88b40369 839 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4
WB		 840
841 /* start dma */
bb90eb00 842 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 843 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 844 set_dma_config(drv_data->dma_channel, dma_config);
845 set_dma_start_addr(drv_data->dma_channel,
a32c691d 846 (unsigned long)drv_data->tx);
bb90eb00 847 enable_dma(drv_data->dma_channel);
07612e5f
SZ		 848
849 /* start SPI transfer */
850 write_CTRL(drv_data,
851 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
a5f6abd4
WB		 852 }
853 } else {
854 /* IO mode write then read */
88b40369 855 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 856
a5f6abd4
WB		 857 if (drv_data->tx != NULL && drv_data->rx != NULL) {
858 /* full duplex mode */
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 863
cc487e73 864 /* set SPI transfer mode */
bb90eb00 865 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 866
867 drv_data->duplex(drv_data);
868
869 if (drv_data->tx != drv_data->tx_end)
870 tranf_success = 0;
871 } else if (drv_data->tx != NULL) {
872 /* write only half duplex */
131b17d4 873 dev_dbg(&drv_data->pdev->dev,
88b40369 874 "IO write: cr is 0x%x\n", cr);
a5f6abd4 875
cc487e73 876 /* set SPI transfer mode */
bb90eb00 877 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 878
879 drv_data->write(drv_data);
880
881 if (drv_data->tx != drv_data->tx_end)
882 tranf_success = 0;
883 } else if (drv_data->rx != NULL) {
884 /* read only half duplex */
131b17d4 885 dev_dbg(&drv_data->pdev->dev,
88b40369 886 "IO read: cr is 0x%x\n", cr);
a5f6abd4 887
cc487e73 888 /* set SPI transfer mode */
bb90eb00 889 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 890
891 drv_data->read(drv_data);
892 if (drv_data->rx != drv_data->rx_end)
893 tranf_success = 0;
894 }
895
896 if (!tranf_success) {
131b17d4 897 dev_dbg(&drv_data->pdev->dev,
88b40369 898 "IO write error!\n");
a5f6abd4
WB		 899 message->state = ERROR_STATE;
900 } else {
901 /* Update total byte transfered */
902 message->actual_length += drv_data->len;
903
904 /* Move to next transfer of this msg */
905 message->state = next_transfer(drv_data);
906 }
907
908 /* Schedule next transfer tasklet */
909 tasklet_schedule(&drv_data->pump_transfers);
910
911 }
912}
913
914/* pop a msg from queue and kick off real transfer */
915static void pump_messages(struct work_struct *work)
916{
131b17d4 917 struct driver_data *drv_data;
a5f6abd4
WB		 918 unsigned long flags;
919
131b17d4
BW		 920 drv_data = container_of(work, struct driver_data, pump_messages);
921
a5f6abd4
WB		 922 /* Lock queue and check for queue work */
923 spin_lock_irqsave(&drv_data->lock, flags);
924 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
925 /* pumper kicked off but no work to do */
926 drv_data->busy = 0;
927 spin_unlock_irqrestore(&drv_data->lock, flags);
928 return;
929 }
930
931 /* Make sure we are not already running a message */
932 if (drv_data->cur_msg) {
933 spin_unlock_irqrestore(&drv_data->lock, flags);
934 return;
935 }
936
937 /* Extract head of queue */
938 drv_data->cur_msg = list_entry(drv_data->queue.next,
939 struct spi_message, queue);
5fec5b5a
BW		 940
941 /* Setup the SSP using the per chip configuration */
942 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 943 restore_state(drv_data);
5fec5b5a 944
a5f6abd4
WB		 945 list_del_init(&drv_data->cur_msg->queue);
946
947 /* Initial message state */
948 drv_data->cur_msg->state = START_STATE;
949 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
950 struct spi_transfer, transfer_list);
951
5fec5b5a
BW		 952 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
953 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
954 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
955 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 956
957 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 958 "the first transfer len is %d\n",
959 drv_data->cur_transfer->len);
a5f6abd4
WB		 960
961 /* Mark as busy and launch transfers */
962 tasklet_schedule(&drv_data->pump_transfers);
963
964 drv_data->busy = 1;
965 spin_unlock_irqrestore(&drv_data->lock, flags);
966}
967
968/*
969 * got a msg to transfer, queue it in drv_data->queue.
970 * And kick off message pumper
971 */
972static int transfer(struct spi_device *spi, struct spi_message *msg)
973{
974 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
975 unsigned long flags;
976
977 spin_lock_irqsave(&drv_data->lock, flags);
978
979 if (drv_data->run == QUEUE_STOPPED) {
980 spin_unlock_irqrestore(&drv_data->lock, flags);
981 return -ESHUTDOWN;
982 }
983
984 msg->actual_length = 0;
985 msg->status = -EINPROGRESS;
986 msg->state = START_STATE;
987
88b40369 988 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 989 list_add_tail(&msg->queue, &drv_data->queue);
990
991 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
992 queue_work(drv_data->workqueue, &drv_data->pump_messages);
993
994 spin_unlock_irqrestore(&drv_data->lock, flags);
995
996 return 0;
997}
998
12e17c42
SZ		 999#define MAX_SPI_SSEL 7
1000
1001static u16 ssel[3][MAX_SPI_SSEL] = {
1002 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1003 P_SPI0_SSEL4, P_SPI0_SSEL5,
1004 P_SPI0_SSEL6, P_SPI0_SSEL7},
1005
1006 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1007 P_SPI1_SSEL4, P_SPI1_SSEL5,
1008 P_SPI1_SSEL6, P_SPI1_SSEL7},
1009
1010 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1011 P_SPI2_SSEL4, P_SPI2_SSEL5,
1012 P_SPI2_SSEL6, P_SPI2_SSEL7},
1013};
1014
a5f6abd4
WB		 1015/* first setup for new devices */
1016static int setup(struct spi_device *spi)
1017{
1018 struct bfin5xx_spi_chip *chip_info = NULL;
1019 struct chip_data *chip;
1020 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1021 u8 spi_flg;
1022
1023 /* Abort device setup if requested features are not supported */
1024 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1025 dev_err(&spi->dev, "requested mode not fully supported\n");
1026 return -EINVAL;
1027 }
1028
1029 /* Zero (the default) here means 8 bits */
1030 if (!spi->bits_per_word)
1031 spi->bits_per_word = 8;
1032
1033 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1034 return -EINVAL;
1035
1036 /* Only alloc (or use chip_info) on first setup */
1037 chip = spi_get_ctldata(spi);
1038 if (chip == NULL) {
1039 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1040 if (!chip)
1041 return -ENOMEM;
1042
1043 chip->enable_dma = 0;
1044 chip_info = spi->controller_data;
1045 }
1046
1047 /* chip_info isn't always needed */
1048 if (chip_info) {
2ed35516
MF		 1049 /* Make sure people stop trying to set fields via ctl_reg
1050 * when they should actually be using common SPI framework.
1051 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1052 * Not sure if a user actually needs/uses any of these,
1053 * but let's assume (for now) they do.
1054 */
1055 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1056 dev_err(&spi->dev, "do not set bits in ctl_reg "
1057 "that the SPI framework manages\n");
1058 return -EINVAL;
1059 }
1060
a5f6abd4
WB		 1061 chip->enable_dma = chip_info->enable_dma != 0
1062 && drv_data->master_info->enable_dma;
1063 chip->ctl_reg = chip_info->ctl_reg;
1064 chip->bits_per_word = chip_info->bits_per_word;
1065 chip->cs_change_per_word = chip_info->cs_change_per_word;
1066 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1067 }
1068
1069 /* translate common spi framework into our register */
1070 if (spi->mode & SPI_CPOL)
1071 chip->ctl_reg |= CPOL;
1072 if (spi->mode & SPI_CPHA)
1073 chip->ctl_reg |= CPHA;
1074 if (spi->mode & SPI_LSB_FIRST)
1075 chip->ctl_reg |= LSBF;
1076 /* we dont support running in slave mode (yet?) */
1077 chip->ctl_reg |= MSTR;
1078
1079 /*
1080 * if any one SPI chip is registered and wants DMA, request the
1081 * DMA channel for it
1082 */
bb90eb00 1083 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1084 /* register dma irq handler */
bb90eb00 1085 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1086 dev_dbg(&spi->dev,
1087 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1088 return -ENODEV;
1089 }
bb90eb00
BW		 1090 if (set_dma_callback(drv_data->dma_channel,
1091 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1092 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1093 return -EPERM;
1094 }
bb90eb00
BW		 1095 dma_disable_irq(drv_data->dma_channel);
1096 drv_data->dma_requested = 1;
a5f6abd4
WB		 1097 }
1098
1099 /*
1100 * Notice: for blackfin, the speed_hz is the value of register
1101 * SPI_BAUD, not the real baudrate
1102 */
1103 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1104 spi_flg = ~(1 << (spi->chip_select));
1105 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1106 chip->chip_select_num = spi->chip_select;
1107
1108 switch (chip->bits_per_word) {
1109 case 8:
1110 chip->n_bytes = 1;
1111 chip->width = CFG_SPI_WORDSIZE8;
1112 chip->read = chip->cs_change_per_word ?
1113 u8_cs_chg_reader : u8_reader;
1114 chip->write = chip->cs_change_per_word ?
1115 u8_cs_chg_writer : u8_writer;
1116 chip->duplex = chip->cs_change_per_word ?
1117 u8_cs_chg_duplex : u8_duplex;
1118 break;
1119
1120 case 16:
1121 chip->n_bytes = 2;
1122 chip->width = CFG_SPI_WORDSIZE16;
1123 chip->read = chip->cs_change_per_word ?
1124 u16_cs_chg_reader : u16_reader;
1125 chip->write = chip->cs_change_per_word ?
1126 u16_cs_chg_writer : u16_writer;
1127 chip->duplex = chip->cs_change_per_word ?
1128 u16_cs_chg_duplex : u16_duplex;
1129 break;
1130
1131 default:
1132 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1133 chip->bits_per_word);
1134 kfree(chip);
1135 return -ENODEV;
1136 }
1137
898eb71c 1138 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1139 spi->modalias, chip->width, chip->enable_dma);
88b40369 1140 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1141 chip->ctl_reg, chip->flag);
1142
1143 spi_set_ctldata(spi, chip);
1144
12e17c42
SZ		 1145 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1146 if ((chip->chip_select_num > 0)
1147 && (chip->chip_select_num <= spi->master->num_chipselect))
1148 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1149 [chip->chip_select_num-1], spi->modalias);
12e17c42 1150
07612e5f
SZ		 1151 cs_deactive(drv_data, chip);
1152
a5f6abd4
WB		 1153 return 0;
1154}
1155
1156/*
1157 * callback for spi framework.
1158 * clean driver specific data
1159 */
88b40369 1160static void cleanup(struct spi_device *spi)
a5f6abd4 1161{
27bb9e79 1162 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1163
12e17c42
SZ		 1164 if ((chip->chip_select_num > 0)
1165 && (chip->chip_select_num <= spi->master->num_chipselect))
1166 peripheral_free(ssel[spi->master->bus_num]
1167 [chip->chip_select_num-1]);
1168
a5f6abd4
WB		 1169 kfree(chip);
1170}
1171
1172static inline int init_queue(struct driver_data *drv_data)
1173{
1174 INIT_LIST_HEAD(&drv_data->queue);
1175 spin_lock_init(&drv_data->lock);
1176
1177 drv_data->run = QUEUE_STOPPED;
1178 drv_data->busy = 0;
1179
1180 /* init transfer tasklet */
1181 tasklet_init(&drv_data->pump_transfers,
1182 pump_transfers, (unsigned long)drv_data);
1183
1184 /* init messages workqueue */
1185 INIT_WORK(&drv_data->pump_messages, pump_messages);
1186 drv_data->workqueue =
49dce689 1187 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
a5f6abd4
WB		 1188 if (drv_data->workqueue == NULL)
1189 return -EBUSY;
1190
1191 return 0;
1192}
1193
1194static inline int start_queue(struct driver_data *drv_data)
1195{
1196 unsigned long flags;
1197
1198 spin_lock_irqsave(&drv_data->lock, flags);
1199
1200 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1201 spin_unlock_irqrestore(&drv_data->lock, flags);
1202 return -EBUSY;
1203 }
1204
1205 drv_data->run = QUEUE_RUNNING;
1206 drv_data->cur_msg = NULL;
1207 drv_data->cur_transfer = NULL;
1208 drv_data->cur_chip = NULL;
1209 spin_unlock_irqrestore(&drv_data->lock, flags);
1210
1211 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1212
1213 return 0;
1214}
1215
1216static inline int stop_queue(struct driver_data *drv_data)
1217{
1218 unsigned long flags;
1219 unsigned limit = 500;
1220 int status = 0;
1221
1222 spin_lock_irqsave(&drv_data->lock, flags);
1223
1224 /*
1225 * This is a bit lame, but is optimized for the common execution path.
1226 * A wait_queue on the drv_data->busy could be used, but then the common
1227 * execution path (pump_messages) would be required to call wake_up or
1228 * friends on every SPI message. Do this instead
1229 */
1230 drv_data->run = QUEUE_STOPPED;
1231 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1232 spin_unlock_irqrestore(&drv_data->lock, flags);
1233 msleep(10);
1234 spin_lock_irqsave(&drv_data->lock, flags);
1235 }
1236
1237 if (!list_empty(&drv_data->queue) || drv_data->busy)
1238 status = -EBUSY;
1239
1240 spin_unlock_irqrestore(&drv_data->lock, flags);
1241
1242 return status;
1243}
1244
1245static inline int destroy_queue(struct driver_data *drv_data)
1246{
1247 int status;
1248
1249 status = stop_queue(drv_data);
1250 if (status != 0)
1251 return status;
1252
1253 destroy_workqueue(drv_data->workqueue);
1254
1255 return 0;
1256}
1257
1258static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1259{
1260 struct device *dev = &pdev->dev;
1261 struct bfin5xx_spi_master *platform_info;
1262 struct spi_master *master;
1263 struct driver_data *drv_data = 0;
a32c691d 1264 struct resource *res;
a5f6abd4
WB		 1265 int status = 0;
1266
1267 platform_info = dev->platform_data;
1268
1269 /* Allocate master with space for drv_data */
1270 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1271 if (!master) {
1272 dev_err(&pdev->dev, "can not alloc spi_master\n");
1273 return -ENOMEM;
1274 }
131b17d4 1275
a5f6abd4
WB		 1276 drv_data = spi_master_get_devdata(master);
1277 drv_data->master = master;
1278 drv_data->master_info = platform_info;
1279 drv_data->pdev = pdev;
003d9226 1280 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1281
1282 master->bus_num = pdev->id;
1283 master->num_chipselect = platform_info->num_chipselect;
1284 master->cleanup = cleanup;
1285 master->setup = setup;
1286 master->transfer = transfer;
1287
a32c691d
BW		 1288 /* Find and map our resources */
1289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1290 if (res == NULL) {
1291 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1292 status = -ENOENT;
1293 goto out_error_get_res;
1294 }
1295
f452126c
BW		 1296 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1297 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1298 dev_err(dev, "Cannot map IO\n");
1299 status = -ENXIO;
1300 goto out_error_ioremap;
1301 }
1302
bb90eb00
BW		 1303 drv_data->dma_channel = platform_get_irq(pdev, 0);
1304 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1305 dev_err(dev, "No DMA channel specified\n");
1306 status = -ENOENT;
1307 goto out_error_no_dma_ch;
1308 }
1309
a5f6abd4
WB		 1310 /* Initial and start queue */
1311 status = init_queue(drv_data);
1312 if (status != 0) {
a32c691d 1313 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1314 goto out_error_queue_alloc;
1315 }
a32c691d 1316
a5f6abd4
WB		 1317 status = start_queue(drv_data);
1318 if (status != 0) {
a32c691d 1319 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1320 goto out_error_queue_alloc;
1321 }
1322
1323 /* Register with the SPI framework */
1324 platform_set_drvdata(pdev, drv_data);
1325 status = spi_register_master(master);
1326 if (status != 0) {
a32c691d 1327 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1328 goto out_error_queue_alloc;
1329 }
a32c691d 1330
003d9226
BW		 1331 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1332 if (status != 0) {
7c4ef094
SZ		 1333 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1334 goto out_error;
1335 }
1336
f452126c 1337 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1338 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1339 drv_data->dma_channel);
a5f6abd4
WB		 1340 return status;
1341
cc2f81a6 1342out_error_queue_alloc:
a5f6abd4 1343 destroy_queue(drv_data);
a32c691d 1344out_error_no_dma_ch:
bb90eb00 1345 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1346out_error_ioremap:
1347out_error_get_res:
cc2f81a6 1348out_error:
a5f6abd4 1349 spi_master_put(master);
cc2f81a6 1350
a5f6abd4
WB		 1351 return status;
1352}
1353
1354/* stop hardware and remove the driver */
1355static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1356{
1357 struct driver_data *drv_data = platform_get_drvdata(pdev);
1358 int status = 0;
1359
1360 if (!drv_data)
1361 return 0;
1362
1363 /* Remove the queue */
1364 status = destroy_queue(drv_data);
1365 if (status != 0)
1366 return status;
1367
1368 /* Disable the SSP at the peripheral and SOC level */
1369 bfin_spi_disable(drv_data);
1370
1371 /* Release DMA */
1372 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1373 if (dma_channel_active(drv_data->dma_channel))
1374 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1375 }
1376
1377 /* Disconnect from the SPI framework */
1378 spi_unregister_master(drv_data->master);
1379
003d9226 1380 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1381
a5f6abd4
WB		 1382 /* Prevent double remove */
1383 platform_set_drvdata(pdev, NULL);
1384
1385 return 0;
1386}
1387
1388#ifdef CONFIG_PM
1389static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1390{
1391 struct driver_data *drv_data = platform_get_drvdata(pdev);
1392 int status = 0;
1393
1394 status = stop_queue(drv_data);
1395 if (status != 0)
1396 return status;
1397
1398 /* stop hardware */
1399 bfin_spi_disable(drv_data);
1400
1401 return 0;
1402}
1403
1404static int bfin5xx_spi_resume(struct platform_device *pdev)
1405{
1406 struct driver_data *drv_data = platform_get_drvdata(pdev);
1407 int status = 0;
1408
1409 /* Enable the SPI interface */
1410 bfin_spi_enable(drv_data);
1411
1412 /* Start the queue running */
1413 status = start_queue(drv_data);
1414 if (status != 0) {
1415 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1416 return status;
1417 }
1418
1419 return 0;
1420}
1421#else
1422#define bfin5xx_spi_suspend NULL
1423#define bfin5xx_spi_resume NULL
1424#endif /* CONFIG_PM */
1425
fc3ba952 1426MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
a5f6abd4 1427static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1428 .driver = {
a32c691d 1429 .name = DRV_NAME,
88b40369
BW		 1430 .owner = THIS_MODULE,
1431 },
1432 .suspend = bfin5xx_spi_suspend,
1433 .resume = bfin5xx_spi_resume,
1434 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1435};
1436
1437static int __init bfin5xx_spi_init(void)
1438{
88b40369 1439 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1440}
a5f6abd4
WB		 1441module_init(bfin5xx_spi_init);
1442
1443static void __exit bfin5xx_spi_exit(void)
1444{
1445 platform_driver_unregister(&bfin5xx_spi_driver);
1446}
a5f6abd4 1447module_exit(bfin5xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)