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Blackfin SPI Driver: get dma working for SPI flashes
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
26fdc1f0 2 * Blackfin On-Chip SPI Driver
a5f6abd4 3 *
131b17d4 4 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4 5 *
26fdc1f0 6 * Enter bugs at http://blackfin.uclinux.org/
a5f6abd4 7 *
26fdc1f0 8 * Licensed under the GPL-2 or later.
a5f6abd4
WB		 9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
131b17d4 13#include <linux/delay.h>
a5f6abd4 14#include <linux/device.h>
131b17d4 15#include <linux/io.h>
a5f6abd4 16#include <linux/ioport.h>
131b17d4 17#include <linux/irq.h>
a5f6abd4
WB		 18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
a5f6abd4 24
a5f6abd4 25#include <asm/dma.h>
131b17d4 26#include <asm/portmux.h>
a5f6abd4 27#include <asm/bfin5xx_spi.h>
8cf5858c
VM		 28#include <asm/cacheflush.h>
29
a32c691d
BW		 30#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 32#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 33#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 37MODULE_LICENSE("GPL");
38
bb90eb00 39#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 40
bb90eb00
BW		 41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45#define QUEUE_RUNNING 0
46#define QUEUE_STOPPED 1
a5f6abd4
WB		 47
48struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
bb90eb00 55 /* Regs base of SPI controller */
f452126c 56 void __iomem *regs_base;
bb90eb00 57
003d9226
BW		 58 /* Pin request list */
59 u16 *pin_req;
60
a5f6abd4
WB		 61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
bb90eb00
BW		 85
86 /* DMA stuffs */
87 int dma_channel;
a5f6abd4 88 int dma_mapped;
bb90eb00 89 int dma_requested;
a5f6abd4
WB		 90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
bb90eb00 92
a5f6abd4
WB		 93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
fad91c89 96 int cs_change;
a5f6abd4
WB		 97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100};
101
102struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
88b40369 109 u8 width; /* 0 or 1 */
a5f6abd4
WB		 110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
62310e51 113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117};
118
bb90eb00
BW		 119#define DEFINE_SPI_REG(reg, off) \
120static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125DEFINE_SPI_REG(CTRL, 0x00)
126DEFINE_SPI_REG(FLAG, 0x04)
127DEFINE_SPI_REG(STAT, 0x08)
128DEFINE_SPI_REG(TDBR, 0x0C)
129DEFINE_SPI_REG(RDBR, 0x10)
130DEFINE_SPI_REG(BAUD, 0x14)
131DEFINE_SPI_REG(SHAW, 0x18)
132
88b40369 133static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 134{
135 u16 cr;
136
bb90eb00
BW		 137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 139}
140
88b40369 141static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 142{
143 u16 cr;
144
bb90eb00
BW		 145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 147}
148
149/* Caculate the SPI_BAUD register value based on input HZ */
150static u16 hz_to_spi_baud(u32 speed_hz)
151{
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
7513e006
MH		 158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
a5f6abd4
WB		 161 return spi_baud;
162}
163
164static int flush(struct driver_data *drv_data)
165{
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
bb90eb00 169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 170 cpu_relax();
a5f6abd4 171
bb90eb00 172 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 173
174 return limit;
175}
176
fad91c89 177/* Chip select operation functions for cs_change flag */
bb90eb00 178static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 179{
bb90eb00 180 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
bb90eb00 185 write_FLAG(drv_data, flag);
fad91c89
BW		 186}
187
bb90eb00 188static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 189{
bb90eb00 190 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 191
192 flag |= (chip->flag << 8);
193
bb90eb00 194 write_FLAG(drv_data, flag);
62310e51
BW		 195
196 /* Move delay here for consistency */
197 if (chip->cs_chg_udelay)
198 udelay(chip->cs_chg_udelay);
fad91c89
BW		 199}
200
a5f6abd4 201/* stop controller and re-config current chip*/
8d20d0a7 202static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 203{
204 struct chip_data *chip = drv_data->cur_chip;
12e17c42 205
a5f6abd4 206 /* Clear status and disable clock */
bb90eb00 207 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 208 bfin_spi_disable(drv_data);
88b40369 209 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 210
5fec5b5a 211 /* Load the registers */
bb90eb00 212 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 213 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 214
215 bfin_spi_enable(drv_data);
07612e5f 216 cs_active(drv_data, chip);
a5f6abd4
WB		 217}
218
219/* used to kick off transfer in rx mode */
bb90eb00 220static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 221{
222 unsigned short tmp;
bb90eb00 223 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 224 return tmp;
225}
226
227static void null_writer(struct driver_data *drv_data)
228{
229 u8 n_bytes = drv_data->n_bytes;
230
231 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 232 write_TDBR(drv_data, 0);
233 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 234 cpu_relax();
a5f6abd4
WB		 235 drv_data->tx += n_bytes;
236 }
237}
238
239static void null_reader(struct driver_data *drv_data)
240{
241 u8 n_bytes = drv_data->n_bytes;
bb90eb00 242 dummy_read(drv_data);
a5f6abd4
WB		 243
244 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 245 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 246 cpu_relax();
bb90eb00 247 dummy_read(drv_data);
a5f6abd4
WB		 248 drv_data->rx += n_bytes;
249 }
250}
251
252static void u8_writer(struct driver_data *drv_data)
253{
131b17d4 254 dev_dbg(&drv_data->pdev->dev,
bb90eb00 255 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 256
a5f6abd4 257 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 258 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
259 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 260 cpu_relax();
a5f6abd4
WB		 261 ++drv_data->tx;
262 }
13f3e642
SZ		 263
264 /* poll for SPI completion before return */
265 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
266 cpu_relax();
a5f6abd4
WB		 267}
268
269static void u8_cs_chg_writer(struct driver_data *drv_data)
270{
271 struct chip_data *chip = drv_data->cur_chip;
272
273 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 274 cs_active(drv_data, chip);
a5f6abd4 275
bb90eb00
BW		 276 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
277 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 278 cpu_relax();
e26aa015
BW		 279 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
280 cpu_relax();
62310e51 281
bb90eb00 282 cs_deactive(drv_data, chip);
5fec5b5a 283
a5f6abd4
WB		 284 ++drv_data->tx;
285 }
a5f6abd4
WB		 286}
287
288static void u8_reader(struct driver_data *drv_data)
289{
131b17d4 290 dev_dbg(&drv_data->pdev->dev,
bb90eb00 291 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 292
3f479a65 293 /* poll for SPI completion before start */
bb90eb00 294 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 295 cpu_relax();
3f479a65 296
a5f6abd4 297 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 298 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 299
bb90eb00 300 dummy_read(drv_data);
cc487e73 301
a5f6abd4 302 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 303 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 304 cpu_relax();
bb90eb00 305 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 306 ++drv_data->rx;
307 }
308
bb90eb00 309 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 310 cpu_relax();
bb90eb00 311 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 312 ++drv_data->rx;
313}
314
315static void u8_cs_chg_reader(struct driver_data *drv_data)
316{
317 struct chip_data *chip = drv_data->cur_chip;
318
e26aa015
BW		 319 while (drv_data->rx < drv_data->rx_end) {
320 cs_active(drv_data, chip);
321 read_RDBR(drv_data); /* kick off */
a5f6abd4 322
e26aa015
BW		 323 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
324 cpu_relax();
325 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
326 cpu_relax();
cc487e73 327
e26aa015 328 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 329 cs_deactive(drv_data, chip);
5fec5b5a 330
a5f6abd4
WB		 331 ++drv_data->rx;
332 }
a5f6abd4
WB		 333}
334
335static void u8_duplex(struct driver_data *drv_data)
336{
337 /* in duplex mode, clk is triggered by writing of TDBR */
338 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 339 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
4fd432d9 340 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 341 cpu_relax();
bb90eb00 342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 343 cpu_relax();
bb90eb00 344 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 345 ++drv_data->rx;
346 ++drv_data->tx;
347 }
348}
349
350static void u8_cs_chg_duplex(struct driver_data *drv_data)
351{
352 struct chip_data *chip = drv_data->cur_chip;
353
354 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 355 cs_active(drv_data, chip);
5fec5b5a 356
bb90eb00 357 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 358
359 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 360 cpu_relax();
bb90eb00 361 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 362 cpu_relax();
bb90eb00 363 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 364
bb90eb00 365 cs_deactive(drv_data, chip);
5fec5b5a 366
a5f6abd4
WB		 367 ++drv_data->rx;
368 ++drv_data->tx;
369 }
a5f6abd4
WB		 370}
371
372static void u16_writer(struct driver_data *drv_data)
373{
131b17d4 374 dev_dbg(&drv_data->pdev->dev,
bb90eb00 375 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 376
a5f6abd4 377 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 378 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
379 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 380 cpu_relax();
a5f6abd4
WB		 381 drv_data->tx += 2;
382 }
13f3e642
SZ		 383
384 /* poll for SPI completion before return */
385 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
386 cpu_relax();
a5f6abd4
WB		 387}
388
389static void u16_cs_chg_writer(struct driver_data *drv_data)
390{
391 struct chip_data *chip = drv_data->cur_chip;
392
393 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 394 cs_active(drv_data, chip);
a5f6abd4 395
bb90eb00
BW		 396 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
397 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 398 cpu_relax();
13f3e642
SZ		 399 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
400 cpu_relax();
62310e51 401
bb90eb00 402 cs_deactive(drv_data, chip);
5fec5b5a 403
a5f6abd4
WB		 404 drv_data->tx += 2;
405 }
a5f6abd4
WB		 406}
407
408static void u16_reader(struct driver_data *drv_data)
409{
88b40369 410 dev_dbg(&drv_data->pdev->dev,
bb90eb00 411 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 412
3f479a65 413 /* poll for SPI completion before start */
bb90eb00 414 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 415 cpu_relax();
3f479a65 416
cc487e73 417 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 418 write_TDBR(drv_data, 0xFFFF);
cc487e73 419
bb90eb00 420 dummy_read(drv_data);
a5f6abd4
WB		 421
422 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 423 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 424 cpu_relax();
bb90eb00 425 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 426 drv_data->rx += 2;
427 }
428
bb90eb00 429 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 430 cpu_relax();
bb90eb00 431 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 432 drv_data->rx += 2;
433}
434
435static void u16_cs_chg_reader(struct driver_data *drv_data)
436{
437 struct chip_data *chip = drv_data->cur_chip;
438
3f479a65 439 /* poll for SPI completion before start */
bb90eb00 440 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 441 cpu_relax();
3f479a65 442
cc487e73 443 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 444 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 445
bb90eb00
BW		 446 cs_active(drv_data, chip);
447 dummy_read(drv_data);
cc487e73 448
c3061abb 449 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 450 cs_deactive(drv_data, chip);
5fec5b5a 451
bb90eb00 452 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 453 cpu_relax();
bb90eb00
BW		 454 cs_active(drv_data, chip);
455 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 456 drv_data->rx += 2;
457 }
bb90eb00 458 cs_deactive(drv_data, chip);
cc487e73 459
bb90eb00 460 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 461 cpu_relax();
bb90eb00 462 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 463 drv_data->rx += 2;
a5f6abd4
WB		 464}
465
466static void u16_duplex(struct driver_data *drv_data)
467{
468 /* in duplex mode, clk is triggered by writing of TDBR */
469 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 470 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 471 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 472 cpu_relax();
bb90eb00 473 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 474 cpu_relax();
bb90eb00 475 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 476 drv_data->rx += 2;
477 drv_data->tx += 2;
478 }
479}
480
481static void u16_cs_chg_duplex(struct driver_data *drv_data)
482{
483 struct chip_data *chip = drv_data->cur_chip;
484
485 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 486 cs_active(drv_data, chip);
a5f6abd4 487
bb90eb00 488 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 489 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 490 cpu_relax();
bb90eb00 491 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 492 cpu_relax();
bb90eb00 493 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 494
bb90eb00 495 cs_deactive(drv_data, chip);
5fec5b5a 496
a5f6abd4
WB		 497 drv_data->rx += 2;
498 drv_data->tx += 2;
499 }
a5f6abd4
WB		 500}
501
502/* test if ther is more transfer to be done */
503static void *next_transfer(struct driver_data *drv_data)
504{
505 struct spi_message *msg = drv_data->cur_msg;
506 struct spi_transfer *trans = drv_data->cur_transfer;
507
508 /* Move to next transfer */
509 if (trans->transfer_list.next != &msg->transfers) {
510 drv_data->cur_transfer =
511 list_entry(trans->transfer_list.next,
512 struct spi_transfer, transfer_list);
513 return RUNNING_STATE;
514 } else
515 return DONE_STATE;
516}
517
518/*
519 * caller already set message->status;
520 * dma and pio irqs are blocked give finished message back
521 */
522static void giveback(struct driver_data *drv_data)
523{
fad91c89 524 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 525 struct spi_transfer *last_transfer;
526 unsigned long flags;
527 struct spi_message *msg;
528
529 spin_lock_irqsave(&drv_data->lock, flags);
530 msg = drv_data->cur_msg;
531 drv_data->cur_msg = NULL;
532 drv_data->cur_transfer = NULL;
533 drv_data->cur_chip = NULL;
534 queue_work(drv_data->workqueue, &drv_data->pump_messages);
535 spin_unlock_irqrestore(&drv_data->lock, flags);
536
537 last_transfer = list_entry(msg->transfers.prev,
538 struct spi_transfer, transfer_list);
539
540 msg->state = NULL;
541
542 /* disable chip select signal. And not stop spi in autobuffer mode */
543 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 544 cs_deactive(drv_data, chip);
a5f6abd4
WB		 545 bfin_spi_disable(drv_data);
546 }
547
fad91c89 548 if (!drv_data->cs_change)
bb90eb00 549 cs_deactive(drv_data, chip);
fad91c89 550
a5f6abd4
WB		 551 if (msg->complete)
552 msg->complete(msg->context);
553}
554
88b40369 555static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 556{
15aafa2f 557 struct driver_data *drv_data = dev_id;
fad91c89 558 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 559 struct spi_message *msg = drv_data->cur_msg;
d24bd1d0 560 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
04b95d2f 561 u16 spistat = read_STAT(drv_data);
a5f6abd4 562
d24bd1d0
MF		 563 dev_dbg(&drv_data->pdev->dev,
564 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
565 dmastat, spistat);
566
bb90eb00 567 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 568
d6fe89b0 569 /* Wait for DMA to complete */
bb90eb00 570 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 571 cpu_relax();
d6fe89b0 572
a5f6abd4 573 /*
d6fe89b0
BW		 574 * wait for the last transaction shifted out. HRM states:
575 * at this point there may still be data in the SPI DMA FIFO waiting
576 * to be transmitted ... software needs to poll TXS in the SPI_STAT
577 * register until it goes low for 2 successive reads
a5f6abd4
WB		 578 */
579 if (drv_data->tx != NULL) {
bb90eb00
BW		 580 while ((read_STAT(drv_data) & TXS) ||
581 (read_STAT(drv_data) & TXS))
d8c05008 582 cpu_relax();
a5f6abd4
WB		 583 }
584
bb90eb00 585 while (!(read_STAT(drv_data) & SPIF))
d8c05008 586 cpu_relax();
a5f6abd4 587
40a2945b 588 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
04b95d2f
MF		 589 msg->state = ERROR_STATE;
590 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
591 } else {
592 msg->actual_length += drv_data->len_in_bytes;
a5f6abd4 593
04b95d2f
MF		 594 if (drv_data->cs_change)
595 cs_deactive(drv_data, chip);
fad91c89 596
04b95d2f
MF		 597 /* Move to next transfer */
598 msg->state = next_transfer(drv_data);
599 }
a5f6abd4
WB		 600
601 /* Schedule transfer tasklet */
602 tasklet_schedule(&drv_data->pump_transfers);
603
604 /* free the irq handler before next transfer */
88b40369
BW		 605 dev_dbg(&drv_data->pdev->dev,
606 "disable dma channel irq%d\n",
bb90eb00
BW		 607 drv_data->dma_channel);
608 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 609
610 return IRQ_HANDLED;
611}
612
613static void pump_transfers(unsigned long data)
614{
615 struct driver_data *drv_data = (struct driver_data *)data;
616 struct spi_message *message = NULL;
617 struct spi_transfer *transfer = NULL;
618 struct spi_transfer *previous = NULL;
619 struct chip_data *chip = NULL;
88b40369
BW		 620 u8 width;
621 u16 cr, dma_width, dma_config;
a5f6abd4 622 u32 tranf_success = 1;
8eeb12e5 623 u8 full_duplex = 0;
a5f6abd4
WB		 624
625 /* Get current state information */
626 message = drv_data->cur_msg;
627 transfer = drv_data->cur_transfer;
628 chip = drv_data->cur_chip;
092e1fda 629
a5f6abd4
WB		 630 /*
631 * if msg is error or done, report it back using complete() callback
632 */
633
634 /* Handle for abort */
635 if (message->state == ERROR_STATE) {
d24bd1d0 636 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
a5f6abd4
WB		 637 message->status = -EIO;
638 giveback(drv_data);
639 return;
640 }
641
642 /* Handle end of message */
643 if (message->state == DONE_STATE) {
d24bd1d0 644 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
a5f6abd4
WB		 645 message->status = 0;
646 giveback(drv_data);
647 return;
648 }
649
650 /* Delay if requested at end of transfer */
651 if (message->state == RUNNING_STATE) {
d24bd1d0 652 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
a5f6abd4
WB		 653 previous = list_entry(transfer->transfer_list.prev,
654 struct spi_transfer, transfer_list);
655 if (previous->delay_usecs)
656 udelay(previous->delay_usecs);
657 }
658
659 /* Setup the transfer state based on the type of transfer */
660 if (flush(drv_data) == 0) {
661 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
662 message->status = -EIO;
663 giveback(drv_data);
664 return;
665 }
666
667 if (transfer->tx_buf != NULL) {
668 drv_data->tx = (void *)transfer->tx_buf;
669 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 670 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
671 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 672 } else {
673 drv_data->tx = NULL;
674 }
675
676 if (transfer->rx_buf != NULL) {
8eeb12e5 677 full_duplex = transfer->tx_buf != NULL;
a5f6abd4
WB		 678 drv_data->rx = transfer->rx_buf;
679 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 680 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
681 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 682 } else {
683 drv_data->rx = NULL;
684 }
685
686 drv_data->rx_dma = transfer->rx_dma;
687 drv_data->tx_dma = transfer->tx_dma;
688 drv_data->len_in_bytes = transfer->len;
fad91c89 689 drv_data->cs_change = transfer->cs_change;
a5f6abd4 690
092e1fda
BW		 691 /* Bits per word setup */
692 switch (transfer->bits_per_word) {
693 case 8:
694 drv_data->n_bytes = 1;
695 width = CFG_SPI_WORDSIZE8;
696 drv_data->read = chip->cs_change_per_word ?
697 u8_cs_chg_reader : u8_reader;
698 drv_data->write = chip->cs_change_per_word ?
699 u8_cs_chg_writer : u8_writer;
700 drv_data->duplex = chip->cs_change_per_word ?
701 u8_cs_chg_duplex : u8_duplex;
702 break;
703
704 case 16:
705 drv_data->n_bytes = 2;
706 width = CFG_SPI_WORDSIZE16;
707 drv_data->read = chip->cs_change_per_word ?
708 u16_cs_chg_reader : u16_reader;
709 drv_data->write = chip->cs_change_per_word ?
710 u16_cs_chg_writer : u16_writer;
711 drv_data->duplex = chip->cs_change_per_word ?
712 u16_cs_chg_duplex : u16_duplex;
713 break;
714
715 default:
716 /* No change, the same as default setting */
717 drv_data->n_bytes = chip->n_bytes;
718 width = chip->width;
719 drv_data->write = drv_data->tx ? chip->write : null_writer;
720 drv_data->read = drv_data->rx ? chip->read : null_reader;
721 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
722 break;
723 }
724 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
725 cr |= (width << 8);
726 write_CTRL(drv_data, cr);
727
a5f6abd4
WB		 728 if (width == CFG_SPI_WORDSIZE16) {
729 drv_data->len = (transfer->len) >> 1;
730 } else {
731 drv_data->len = transfer->len;
732 }
4fb98efa
MF		 733 dev_dbg(&drv_data->pdev->dev,
734 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
131b17d4 735 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 736
737 /* speed and width has been set on per message */
738 message->state = RUNNING_STATE;
739 dma_config = 0;
740
092e1fda
BW		 741 /* Speed setup (surely valid because already checked) */
742 if (transfer->speed_hz)
743 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
744 else
745 write_BAUD(drv_data, chip->baud);
746
bb90eb00
BW		 747 write_STAT(drv_data, BIT_STAT_CLR);
748 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
749 cs_active(drv_data, chip);
a5f6abd4 750
88b40369
BW		 751 dev_dbg(&drv_data->pdev->dev,
752 "now pumping a transfer: width is %d, len is %d\n",
753 width, transfer->len);
a5f6abd4
WB		 754
755 /*
8cf5858c
VM		 756 * Try to map dma buffer and do a dma transfer. If successful use,
757 * different way to r/w according to the enable_dma settings and if
758 * we are not doing a full duplex transfer (since the hardware does
759 * not support full duplex DMA transfers).
a5f6abd4 760 */
8eeb12e5
VM		 761 if (!full_duplex && drv_data->cur_chip->enable_dma
762 && drv_data->len > 6) {
a5f6abd4 763
11d6f599 764 unsigned long dma_start_addr, flags;
7aec3566 765
bb90eb00
BW		 766 disable_dma(drv_data->dma_channel);
767 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4
WB		 768
769 /* config dma channel */
88b40369 770 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
7aec3566 771 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4 772 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00 773 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 774 dma_width = WDSIZE_16;
775 } else {
bb90eb00 776 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 777 dma_width = WDSIZE_8;
778 }
779
3f479a65 780 /* poll for SPI completion before start */
bb90eb00 781 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 782 cpu_relax();
3f479a65 783
a5f6abd4
WB		 784 /* dirty hack for autobuffer DMA mode */
785 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 786 dev_dbg(&drv_data->pdev->dev,
787 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 788
789 /* no irq in autobuffer mode */
790 dma_config =
791 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 792 set_dma_config(drv_data->dma_channel, dma_config);
793 set_dma_start_addr(drv_data->dma_channel,
a32c691d 794 (unsigned long)drv_data->tx);
bb90eb00 795 enable_dma(drv_data->dma_channel);
a5f6abd4 796
07612e5f 797 /* start SPI transfer */
11d6f599 798 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
07612e5f
SZ		 799
800 /* just return here, there can only be one transfer
801 * in this mode
802 */
a5f6abd4
WB		 803 message->status = 0;
804 giveback(drv_data);
805 return;
806 }
807
808 /* In dma mode, rx or tx must be NULL in one transfer */
7aec3566 809 dma_config = (RESTART | dma_width | DI_EN);
a5f6abd4
WB		 810 if (drv_data->rx != NULL) {
811 /* set transfer mode, and enable SPI */
d24bd1d0
MF		 812 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
813 drv_data->rx, drv_data->len_in_bytes);
a5f6abd4 814
8cf5858c
VM		 815 /* invalidate caches, if needed */
816 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
817 invalidate_dcache_range((unsigned long) drv_data->rx,
818 (unsigned long) (drv_data->rx +
ace32865 819 drv_data->len_in_bytes));
8cf5858c 820
a5f6abd4 821 /* clear tx reg soformer data is not shifted out */
bb90eb00 822 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 823
7aec3566
MF		 824 dma_config |= WNR;
825 dma_start_addr = (unsigned long)drv_data->rx;
b31e27a6 826 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
07612e5f 827
a5f6abd4 828 } else if (drv_data->tx != NULL) {
88b40369 829 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4 830
8cf5858c
VM		 831 /* flush caches, if needed */
832 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
833 flush_dcache_range((unsigned long) drv_data->tx,
834 (unsigned long) (drv_data->tx +
ace32865 835 drv_data->len_in_bytes));
8cf5858c 836
7aec3566 837 dma_start_addr = (unsigned long)drv_data->tx;
b31e27a6 838 cr |= BIT_CTL_TIMOD_DMA_TX;
7aec3566
MF		 839
840 } else
841 BUG();
842
11d6f599
MF		 843 /* oh man, here there be monsters ... and i dont mean the
844 * fluffy cute ones from pixar, i mean the kind that'll eat
845 * your data, kick your dog, and love it all. do *not* try
846 * and change these lines unless you (1) heavily test DMA
847 * with SPI flashes on a loaded system (e.g. ping floods),
848 * (2) know just how broken the DMA engine interaction with
849 * the SPI peripheral is, and (3) have someone else to blame
850 * when you screw it all up anyways.
851 */
7aec3566 852 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
11d6f599
MF		 853 set_dma_config(drv_data->dma_channel, dma_config);
854 local_irq_save(flags);
7aec3566 855 enable_dma(drv_data->dma_channel);
11d6f599
MF		 856 write_CTRL(drv_data, cr);
857 dma_enable_irq(drv_data->dma_channel);
858 local_irq_restore(flags);
07612e5f 859
a5f6abd4
WB		 860 } else {
861 /* IO mode write then read */
88b40369 862 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 863
8eeb12e5 864 if (full_duplex) {
a5f6abd4
WB		 865 /* full duplex mode */
866 BUG_ON((drv_data->tx_end - drv_data->tx) !=
867 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 868 dev_dbg(&drv_data->pdev->dev,
869 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 870
cc487e73 871 /* set SPI transfer mode */
bb90eb00 872 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 873
874 drv_data->duplex(drv_data);
875
876 if (drv_data->tx != drv_data->tx_end)
877 tranf_success = 0;
878 } else if (drv_data->tx != NULL) {
879 /* write only half duplex */
131b17d4 880 dev_dbg(&drv_data->pdev->dev,
88b40369 881 "IO write: cr is 0x%x\n", cr);
a5f6abd4 882
cc487e73 883 /* set SPI transfer mode */
bb90eb00 884 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 885
886 drv_data->write(drv_data);
887
888 if (drv_data->tx != drv_data->tx_end)
889 tranf_success = 0;
890 } else if (drv_data->rx != NULL) {
891 /* read only half duplex */
131b17d4 892 dev_dbg(&drv_data->pdev->dev,
88b40369 893 "IO read: cr is 0x%x\n", cr);
a5f6abd4 894
cc487e73 895 /* set SPI transfer mode */
bb90eb00 896 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 897
898 drv_data->read(drv_data);
899 if (drv_data->rx != drv_data->rx_end)
900 tranf_success = 0;
901 }
902
903 if (!tranf_success) {
131b17d4 904 dev_dbg(&drv_data->pdev->dev,
88b40369 905 "IO write error!\n");
a5f6abd4
WB		 906 message->state = ERROR_STATE;
907 } else {
908 /* Update total byte transfered */
ace32865 909 message->actual_length += drv_data->len_in_bytes;
a5f6abd4
WB		 910
911 /* Move to next transfer of this msg */
912 message->state = next_transfer(drv_data);
913 }
914
915 /* Schedule next transfer tasklet */
916 tasklet_schedule(&drv_data->pump_transfers);
917
918 }
919}
920
921/* pop a msg from queue and kick off real transfer */
922static void pump_messages(struct work_struct *work)
923{
131b17d4 924 struct driver_data *drv_data;
a5f6abd4
WB		 925 unsigned long flags;
926
131b17d4
BW		 927 drv_data = container_of(work, struct driver_data, pump_messages);
928
a5f6abd4
WB		 929 /* Lock queue and check for queue work */
930 spin_lock_irqsave(&drv_data->lock, flags);
931 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
932 /* pumper kicked off but no work to do */
933 drv_data->busy = 0;
934 spin_unlock_irqrestore(&drv_data->lock, flags);
935 return;
936 }
937
938 /* Make sure we are not already running a message */
939 if (drv_data->cur_msg) {
940 spin_unlock_irqrestore(&drv_data->lock, flags);
941 return;
942 }
943
944 /* Extract head of queue */
945 drv_data->cur_msg = list_entry(drv_data->queue.next,
946 struct spi_message, queue);
5fec5b5a
BW		 947
948 /* Setup the SSP using the per chip configuration */
949 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 950 restore_state(drv_data);
5fec5b5a 951
a5f6abd4
WB		 952 list_del_init(&drv_data->cur_msg->queue);
953
954 /* Initial message state */
955 drv_data->cur_msg->state = START_STATE;
956 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
957 struct spi_transfer, transfer_list);
958
5fec5b5a
BW		 959 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
960 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
961 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
962 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 963
964 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 965 "the first transfer len is %d\n",
966 drv_data->cur_transfer->len);
a5f6abd4
WB		 967
968 /* Mark as busy and launch transfers */
969 tasklet_schedule(&drv_data->pump_transfers);
970
971 drv_data->busy = 1;
972 spin_unlock_irqrestore(&drv_data->lock, flags);
973}
974
975/*
976 * got a msg to transfer, queue it in drv_data->queue.
977 * And kick off message pumper
978 */
979static int transfer(struct spi_device *spi, struct spi_message *msg)
980{
981 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
982 unsigned long flags;
983
984 spin_lock_irqsave(&drv_data->lock, flags);
985
986 if (drv_data->run == QUEUE_STOPPED) {
987 spin_unlock_irqrestore(&drv_data->lock, flags);
988 return -ESHUTDOWN;
989 }
990
991 msg->actual_length = 0;
992 msg->status = -EINPROGRESS;
993 msg->state = START_STATE;
994
88b40369 995 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 996 list_add_tail(&msg->queue, &drv_data->queue);
997
998 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
999 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1000
1001 spin_unlock_irqrestore(&drv_data->lock, flags);
1002
1003 return 0;
1004}
1005
12e17c42
SZ		 1006#define MAX_SPI_SSEL 7
1007
4160bde2 1008static u16 ssel[][MAX_SPI_SSEL] = {
12e17c42
SZ		 1009 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1010 P_SPI0_SSEL4, P_SPI0_SSEL5,
1011 P_SPI0_SSEL6, P_SPI0_SSEL7},
1012
1013 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1014 P_SPI1_SSEL4, P_SPI1_SSEL5,
1015 P_SPI1_SSEL6, P_SPI1_SSEL7},
1016
1017 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1018 P_SPI2_SSEL4, P_SPI2_SSEL5,
1019 P_SPI2_SSEL6, P_SPI2_SSEL7},
1020};
1021
a5f6abd4
WB		 1022/* first setup for new devices */
1023static int setup(struct spi_device *spi)
1024{
1025 struct bfin5xx_spi_chip *chip_info = NULL;
1026 struct chip_data *chip;
1027 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1028 u8 spi_flg;
1029
1030 /* Abort device setup if requested features are not supported */
1031 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1032 dev_err(&spi->dev, "requested mode not fully supported\n");
1033 return -EINVAL;
1034 }
1035
1036 /* Zero (the default) here means 8 bits */
1037 if (!spi->bits_per_word)
1038 spi->bits_per_word = 8;
1039
1040 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1041 return -EINVAL;
1042
1043 /* Only alloc (or use chip_info) on first setup */
1044 chip = spi_get_ctldata(spi);
1045 if (chip == NULL) {
1046 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1047 if (!chip)
1048 return -ENOMEM;
1049
1050 chip->enable_dma = 0;
1051 chip_info = spi->controller_data;
1052 }
1053
1054 /* chip_info isn't always needed */
1055 if (chip_info) {
2ed35516
MF		 1056 /* Make sure people stop trying to set fields via ctl_reg
1057 * when they should actually be using common SPI framework.
1058 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1059 * Not sure if a user actually needs/uses any of these,
1060 * but let's assume (for now) they do.
1061 */
1062 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1063 dev_err(&spi->dev, "do not set bits in ctl_reg "
1064 "that the SPI framework manages\n");
1065 return -EINVAL;
1066 }
1067
a5f6abd4
WB		 1068 chip->enable_dma = chip_info->enable_dma != 0
1069 && drv_data->master_info->enable_dma;
1070 chip->ctl_reg = chip_info->ctl_reg;
1071 chip->bits_per_word = chip_info->bits_per_word;
1072 chip->cs_change_per_word = chip_info->cs_change_per_word;
1073 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1074 }
1075
1076 /* translate common spi framework into our register */
1077 if (spi->mode & SPI_CPOL)
1078 chip->ctl_reg |= CPOL;
1079 if (spi->mode & SPI_CPHA)
1080 chip->ctl_reg |= CPHA;
1081 if (spi->mode & SPI_LSB_FIRST)
1082 chip->ctl_reg |= LSBF;
1083 /* we dont support running in slave mode (yet?) */
1084 chip->ctl_reg |= MSTR;
1085
1086 /*
1087 * if any one SPI chip is registered and wants DMA, request the
1088 * DMA channel for it
1089 */
bb90eb00 1090 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1091 /* register dma irq handler */
59bfcc66 1092 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
88b40369
BW		 1093 dev_dbg(&spi->dev,
1094 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1095 return -ENODEV;
1096 }
bb90eb00 1097 if (set_dma_callback(drv_data->dma_channel,
59bfcc66 1098 dma_irq_handler, drv_data) < 0) {
88b40369 1099 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1100 return -EPERM;
1101 }
bb90eb00
BW		 1102 dma_disable_irq(drv_data->dma_channel);
1103 drv_data->dma_requested = 1;
a5f6abd4
WB		 1104 }
1105
1106 /*
1107 * Notice: for blackfin, the speed_hz is the value of register
1108 * SPI_BAUD, not the real baudrate
1109 */
1110 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1111 spi_flg = ~(1 << (spi->chip_select));
1112 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1113 chip->chip_select_num = spi->chip_select;
1114
1115 switch (chip->bits_per_word) {
1116 case 8:
1117 chip->n_bytes = 1;
1118 chip->width = CFG_SPI_WORDSIZE8;
1119 chip->read = chip->cs_change_per_word ?
1120 u8_cs_chg_reader : u8_reader;
1121 chip->write = chip->cs_change_per_word ?
1122 u8_cs_chg_writer : u8_writer;
1123 chip->duplex = chip->cs_change_per_word ?
1124 u8_cs_chg_duplex : u8_duplex;
1125 break;
1126
1127 case 16:
1128 chip->n_bytes = 2;
1129 chip->width = CFG_SPI_WORDSIZE16;
1130 chip->read = chip->cs_change_per_word ?
1131 u16_cs_chg_reader : u16_reader;
1132 chip->write = chip->cs_change_per_word ?
1133 u16_cs_chg_writer : u16_writer;
1134 chip->duplex = chip->cs_change_per_word ?
1135 u16_cs_chg_duplex : u16_duplex;
1136 break;
1137
1138 default:
1139 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1140 chip->bits_per_word);
1141 kfree(chip);
1142 return -ENODEV;
1143 }
1144
898eb71c 1145 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1146 spi->modalias, chip->width, chip->enable_dma);
88b40369 1147 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1148 chip->ctl_reg, chip->flag);
1149
1150 spi_set_ctldata(spi, chip);
1151
12e17c42
SZ		 1152 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1153 if ((chip->chip_select_num > 0)
1154 && (chip->chip_select_num <= spi->master->num_chipselect))
1155 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1156 [chip->chip_select_num-1], spi->modalias);
12e17c42 1157
07612e5f
SZ		 1158 cs_deactive(drv_data, chip);
1159
a5f6abd4
WB		 1160 return 0;
1161}
1162
1163/*
1164 * callback for spi framework.
1165 * clean driver specific data
1166 */
88b40369 1167static void cleanup(struct spi_device *spi)
a5f6abd4 1168{
27bb9e79 1169 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1170
12e17c42
SZ		 1171 if ((chip->chip_select_num > 0)
1172 && (chip->chip_select_num <= spi->master->num_chipselect))
1173 peripheral_free(ssel[spi->master->bus_num]
1174 [chip->chip_select_num-1]);
1175
a5f6abd4
WB		 1176 kfree(chip);
1177}
1178
1179static inline int init_queue(struct driver_data *drv_data)
1180{
1181 INIT_LIST_HEAD(&drv_data->queue);
1182 spin_lock_init(&drv_data->lock);
1183
1184 drv_data->run = QUEUE_STOPPED;
1185 drv_data->busy = 0;
1186
1187 /* init transfer tasklet */
1188 tasklet_init(&drv_data->pump_transfers,
1189 pump_transfers, (unsigned long)drv_data);
1190
1191 /* init messages workqueue */
1192 INIT_WORK(&drv_data->pump_messages, pump_messages);
6c7377ab
KS		 1193 drv_data->workqueue = create_singlethread_workqueue(
1194 dev_name(drv_data->master->dev.parent));
a5f6abd4
WB		 1195 if (drv_data->workqueue == NULL)
1196 return -EBUSY;
1197
1198 return 0;
1199}
1200
1201static inline int start_queue(struct driver_data *drv_data)
1202{
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&drv_data->lock, flags);
1206
1207 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1208 spin_unlock_irqrestore(&drv_data->lock, flags);
1209 return -EBUSY;
1210 }
1211
1212 drv_data->run = QUEUE_RUNNING;
1213 drv_data->cur_msg = NULL;
1214 drv_data->cur_transfer = NULL;
1215 drv_data->cur_chip = NULL;
1216 spin_unlock_irqrestore(&drv_data->lock, flags);
1217
1218 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1219
1220 return 0;
1221}
1222
1223static inline int stop_queue(struct driver_data *drv_data)
1224{
1225 unsigned long flags;
1226 unsigned limit = 500;
1227 int status = 0;
1228
1229 spin_lock_irqsave(&drv_data->lock, flags);
1230
1231 /*
1232 * This is a bit lame, but is optimized for the common execution path.
1233 * A wait_queue on the drv_data->busy could be used, but then the common
1234 * execution path (pump_messages) would be required to call wake_up or
1235 * friends on every SPI message. Do this instead
1236 */
1237 drv_data->run = QUEUE_STOPPED;
1238 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1239 spin_unlock_irqrestore(&drv_data->lock, flags);
1240 msleep(10);
1241 spin_lock_irqsave(&drv_data->lock, flags);
1242 }
1243
1244 if (!list_empty(&drv_data->queue) || drv_data->busy)
1245 status = -EBUSY;
1246
1247 spin_unlock_irqrestore(&drv_data->lock, flags);
1248
1249 return status;
1250}
1251
1252static inline int destroy_queue(struct driver_data *drv_data)
1253{
1254 int status;
1255
1256 status = stop_queue(drv_data);
1257 if (status != 0)
1258 return status;
1259
1260 destroy_workqueue(drv_data->workqueue);
1261
1262 return 0;
1263}
1264
1265static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1266{
1267 struct device *dev = &pdev->dev;
1268 struct bfin5xx_spi_master *platform_info;
1269 struct spi_master *master;
1270 struct driver_data *drv_data = 0;
a32c691d 1271 struct resource *res;
a5f6abd4
WB		 1272 int status = 0;
1273
1274 platform_info = dev->platform_data;
1275
1276 /* Allocate master with space for drv_data */
1277 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1278 if (!master) {
1279 dev_err(&pdev->dev, "can not alloc spi_master\n");
1280 return -ENOMEM;
1281 }
131b17d4 1282
a5f6abd4
WB		 1283 drv_data = spi_master_get_devdata(master);
1284 drv_data->master = master;
1285 drv_data->master_info = platform_info;
1286 drv_data->pdev = pdev;
003d9226 1287 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1288
1289 master->bus_num = pdev->id;
1290 master->num_chipselect = platform_info->num_chipselect;
1291 master->cleanup = cleanup;
1292 master->setup = setup;
1293 master->transfer = transfer;
1294
a32c691d
BW		 1295 /* Find and map our resources */
1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 if (res == NULL) {
1298 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1299 status = -ENOENT;
1300 goto out_error_get_res;
1301 }
1302
f452126c
BW		 1303 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1304 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1305 dev_err(dev, "Cannot map IO\n");
1306 status = -ENXIO;
1307 goto out_error_ioremap;
1308 }
1309
bb90eb00
BW		 1310 drv_data->dma_channel = platform_get_irq(pdev, 0);
1311 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1312 dev_err(dev, "No DMA channel specified\n");
1313 status = -ENOENT;
1314 goto out_error_no_dma_ch;
1315 }
1316
a5f6abd4
WB		 1317 /* Initial and start queue */
1318 status = init_queue(drv_data);
1319 if (status != 0) {
a32c691d 1320 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1321 goto out_error_queue_alloc;
1322 }
a32c691d 1323
a5f6abd4
WB		 1324 status = start_queue(drv_data);
1325 if (status != 0) {
a32c691d 1326 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1327 goto out_error_queue_alloc;
1328 }
1329
f9e522ca
VM		 1330 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1331 if (status != 0) {
1332 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1333 goto out_error_queue_alloc;
1334 }
1335
a5f6abd4
WB		 1336 /* Register with the SPI framework */
1337 platform_set_drvdata(pdev, drv_data);
1338 status = spi_register_master(master);
1339 if (status != 0) {
a32c691d 1340 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1341 goto out_error_queue_alloc;
1342 }
a32c691d 1343
f452126c 1344 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1345 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1346 drv_data->dma_channel);
a5f6abd4
WB		 1347 return status;
1348
cc2f81a6 1349out_error_queue_alloc:
a5f6abd4 1350 destroy_queue(drv_data);
a32c691d 1351out_error_no_dma_ch:
bb90eb00 1352 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1353out_error_ioremap:
1354out_error_get_res:
a5f6abd4 1355 spi_master_put(master);
cc2f81a6 1356
a5f6abd4
WB		 1357 return status;
1358}
1359
1360/* stop hardware and remove the driver */
1361static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1362{
1363 struct driver_data *drv_data = platform_get_drvdata(pdev);
1364 int status = 0;
1365
1366 if (!drv_data)
1367 return 0;
1368
1369 /* Remove the queue */
1370 status = destroy_queue(drv_data);
1371 if (status != 0)
1372 return status;
1373
1374 /* Disable the SSP at the peripheral and SOC level */
1375 bfin_spi_disable(drv_data);
1376
1377 /* Release DMA */
1378 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1379 if (dma_channel_active(drv_data->dma_channel))
1380 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1381 }
1382
1383 /* Disconnect from the SPI framework */
1384 spi_unregister_master(drv_data->master);
1385
003d9226 1386 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1387
a5f6abd4
WB		 1388 /* Prevent double remove */
1389 platform_set_drvdata(pdev, NULL);
1390
1391 return 0;
1392}
1393
1394#ifdef CONFIG_PM
1395static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1396{
1397 struct driver_data *drv_data = platform_get_drvdata(pdev);
1398 int status = 0;
1399
1400 status = stop_queue(drv_data);
1401 if (status != 0)
1402 return status;
1403
1404 /* stop hardware */
1405 bfin_spi_disable(drv_data);
1406
1407 return 0;
1408}
1409
1410static int bfin5xx_spi_resume(struct platform_device *pdev)
1411{
1412 struct driver_data *drv_data = platform_get_drvdata(pdev);
1413 int status = 0;
1414
1415 /* Enable the SPI interface */
1416 bfin_spi_enable(drv_data);
1417
1418 /* Start the queue running */
1419 status = start_queue(drv_data);
1420 if (status != 0) {
1421 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1422 return status;
1423 }
1424
1425 return 0;
1426}
1427#else
1428#define bfin5xx_spi_suspend NULL
1429#define bfin5xx_spi_resume NULL
1430#endif /* CONFIG_PM */
1431
7e38c3c4 1432MODULE_ALIAS("platform:bfin-spi");
a5f6abd4 1433static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1434 .driver = {
a32c691d 1435 .name = DRV_NAME,
88b40369
BW		 1436 .owner = THIS_MODULE,
1437 },
1438 .suspend = bfin5xx_spi_suspend,
1439 .resume = bfin5xx_spi_resume,
1440 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1441};
1442
1443static int __init bfin5xx_spi_init(void)
1444{
88b40369 1445 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1446}
a5f6abd4
WB		 1447module_init(bfin5xx_spi_init);
1448
1449static void __exit bfin5xx_spi_exit(void)
1450{
1451 platform_driver_unregister(&bfin5xx_spi_driver);
1452}
a5f6abd4 1453module_exit(bfin5xx_spi_exit);