[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-txx9.c

/*
 * TXx9 SPI controller driver.
 *
 * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
 *
 * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
 */
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <asm/gpio.h>


#define SPI_FIFO_SIZE 4
#define SPI_MAX_DIVIDER 0xff	/* Max. value for SPCR1.SER */
#define SPI_MIN_DIVIDER 1	/* Min. value for SPCR1.SER */

#define TXx9_SPMCR		0x00
#define TXx9_SPCR0		0x04
#define TXx9_SPCR1		0x08
#define TXx9_SPFS		0x0c
#define TXx9_SPSR		0x14
#define TXx9_SPDR		0x18

/* SPMCR : SPI Master Control */
#define TXx9_SPMCR_OPMODE	0xc0
#define TXx9_SPMCR_CONFIG	0x40
#define TXx9_SPMCR_ACTIVE	0x80
#define TXx9_SPMCR_SPSTP	0x02
#define TXx9_SPMCR_BCLR		0x01

/* SPCR0 : SPI Control 0 */
#define TXx9_SPCR0_TXIFL_MASK	0xc000
#define TXx9_SPCR0_RXIFL_MASK	0x3000
#define TXx9_SPCR0_SIDIE	0x0800
#define TXx9_SPCR0_SOEIE	0x0400
#define TXx9_SPCR0_RBSIE	0x0200
#define TXx9_SPCR0_TBSIE	0x0100
#define TXx9_SPCR0_IFSPSE	0x0010
#define TXx9_SPCR0_SBOS		0x0004
#define TXx9_SPCR0_SPHA		0x0002
#define TXx9_SPCR0_SPOL		0x0001

/* SPSR : SPI Status */
#define TXx9_SPSR_TBSI		0x8000
#define TXx9_SPSR_RBSI		0x4000
#define TXx9_SPSR_TBS_MASK	0x3800
#define TXx9_SPSR_RBS_MASK	0x0700
#define TXx9_SPSR_SPOE		0x0080
#define TXx9_SPSR_IFSD		0x0008
#define TXx9_SPSR_SIDLE		0x0004
#define TXx9_SPSR_STRDY		0x0002
#define TXx9_SPSR_SRRDY		0x0001


struct txx9spi {
	struct workqueue_struct	*workqueue;
	struct work_struct work;
	spinlock_t lock;	/* protect 'queue' */
	struct list_head queue;
	wait_queue_head_t waitq;
	void __iomem *membase;
	int baseclk;
	struct clk *clk;
	u32 max_speed_hz, min_speed_hz;
	int last_chipselect;
	int last_chipselect_val;
};

static u32 txx9spi_rd(struct txx9spi *c, int reg)
{
	return __raw_readl(c->membase + reg);
}
static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
{
	__raw_writel(val, c->membase + reg);
}

static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
		int on, unsigned int cs_delay)
{
	int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
	if (on) {
		/* deselect the chip with cs_change hint in last transfer */
		if (c->last_chipselect >= 0)
			gpio_set_value(c->last_chipselect,
					!c->last_chipselect_val);
		c->last_chipselect = spi->chip_select;
		c->last_chipselect_val = val;
	} else {
		c->last_chipselect = -1;
		ndelay(cs_delay);	/* CS Hold Time */
	}
	gpio_set_value(spi->chip_select, val);
	ndelay(cs_delay);	/* CS Setup Time / CS Recovery Time */
}

static int txx9spi_setup(struct spi_device *spi)
{
	struct txx9spi *c = spi_master_get_devdata(spi->master);
	u8 bits_per_word;

	if (!spi->max_speed_hz
			|| spi->max_speed_hz > c->max_speed_hz
			|| spi->max_speed_hz < c->min_speed_hz)
		return -EINVAL;

	bits_per_word = spi->bits_per_word;
	if (bits_per_word != 8 && bits_per_word != 16)
		return -EINVAL;

	if (gpio_direction_output(spi->chip_select,
			!(spi->mode & SPI_CS_HIGH))) {
		dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
		return -EINVAL;
	}

	/* deselect chip */
	spin_lock(&c->lock);
	txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
	spin_unlock(&c->lock);

	return 0;
}

static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
{
	struct txx9spi *c = dev_id;

	/* disable rx intr */
	txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
			TXx9_SPCR0);
	wake_up(&c->waitq);
	return IRQ_HANDLED;
}

static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
{
	struct spi_device *spi = m->spi;
	struct spi_transfer *t;
	unsigned int cs_delay;
	unsigned int cs_change = 1;
	int status = 0;
	u32 mcr;
	u32 prev_speed_hz = 0;
	u8 prev_bits_per_word = 0;

	/* CS setup/hold/recovery time in nsec */
	cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;

	mcr = txx9spi_rd(c, TXx9_SPMCR);
	if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
		dev_err(&spi->dev, "Bad mode.\n");
		status = -EIO;
		goto exit;
	}
	mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);

	/* enter config mode */
	txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
	txx9spi_wr(c, TXx9_SPCR0_SBOS
			| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
			| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
			| 0x08,
			TXx9_SPCR0);

	list_for_each_entry (t, &m->transfers, transfer_list) {
		const void *txbuf = t->tx_buf;
		void *rxbuf = t->rx_buf;
		u32 data;
		unsigned int len = t->len;
		unsigned int wsize;
		u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
		u8 bits_per_word = t->bits_per_word;

		wsize = bits_per_word >> 3; /* in bytes */

		if (prev_speed_hz != speed_hz
				|| prev_bits_per_word != bits_per_word) {
			int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
			n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
			/* enter config mode */
			txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
					TXx9_SPMCR);
			txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
			/* enter active mode */
			txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);

			prev_speed_hz = speed_hz;
			prev_bits_per_word = bits_per_word;
		}

		if (cs_change)
			txx9spi_cs_func(spi, c, 1, cs_delay);
		cs_change = t->cs_change;
		while (len) {
			unsigned int count = SPI_FIFO_SIZE;
			int i;
			u32 cr0;

			if (len < count * wsize)
				count = len / wsize;
			/* now tx must be idle... */
			while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
				cpu_relax();
			cr0 = txx9spi_rd(c, TXx9_SPCR0);
			cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
			cr0 |= (count - 1) << 12;
			/* enable rx intr */
			cr0 |= TXx9_SPCR0_RBSIE;
			txx9spi_wr(c, cr0, TXx9_SPCR0);
			/* send */
			for (i = 0; i < count; i++) {
				if (txbuf) {
					data = (wsize == 1)
						? *(const u8 *)txbuf
						: *(const u16 *)txbuf;
					txx9spi_wr(c, data, TXx9_SPDR);
					txbuf += wsize;
				} else
					txx9spi_wr(c, 0, TXx9_SPDR);
			}
			/* wait all rx data */
			wait_event(c->waitq,
				txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
			/* receive */
			for (i = 0; i < count; i++) {
				data = txx9spi_rd(c, TXx9_SPDR);
				if (rxbuf) {
					if (wsize == 1)
						*(u8 *)rxbuf = data;
					else
						*(u16 *)rxbuf = data;
					rxbuf += wsize;
				}
			}
			len -= count * wsize;
		}
		m->actual_length += t->len;
		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (!cs_change)
			continue;
		if (t->transfer_list.next == &m->transfers)
			break;
		/* sometimes a short mid-message deselect of the chip
		 * may be needed to terminate a mode or command
		 */
		txx9spi_cs_func(spi, c, 0, cs_delay);
	}

exit:
	m->status = status;
	m->complete(m->context);

	/* normally deactivate chipselect ... unless no error and
	 * cs_change has hinted that the next message will probably
	 * be for this chip too.
	 */
	if (!(status == 0 && cs_change))
		txx9spi_cs_func(spi, c, 0, cs_delay);

	/* enter config mode */
	txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
}

static void txx9spi_work(struct work_struct *work)
{
	struct txx9spi *c = container_of(work, struct txx9spi, work);
	unsigned long flags;

	spin_lock_irqsave(&c->lock, flags);
	while (!list_empty(&c->queue)) {
		struct spi_message *m;

		m = container_of(c->queue.next, struct spi_message, queue);
		list_del_init(&m->queue);
		spin_unlock_irqrestore(&c->lock, flags);

		txx9spi_work_one(c, m);

		spin_lock_irqsave(&c->lock, flags);
	}
	spin_unlock_irqrestore(&c->lock, flags);
}

static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct spi_master *master = spi->master;
	struct txx9spi *c = spi_master_get_devdata(master);
	struct spi_transfer *t;
	unsigned long flags;

	m->actual_length = 0;

	/* check each transfer's parameters */
	list_for_each_entry (t, &m->transfers, transfer_list) {
		u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
		u8 bits_per_word = t->bits_per_word;

		if (!t->tx_buf && !t->rx_buf && t->len)
			return -EINVAL;
		if (bits_per_word != 8 && bits_per_word != 16)
			return -EINVAL;
		if (t->len & ((bits_per_word >> 3) - 1))
			return -EINVAL;
		if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz)
			return -EINVAL;
	}

	spin_lock_irqsave(&c->lock, flags);
	list_add_tail(&m->queue, &c->queue);
	queue_work(c->workqueue, &c->work);
	spin_unlock_irqrestore(&c->lock, flags);

	return 0;
}

static int txx9spi_probe(struct platform_device *dev)
{
	struct spi_master *master;
	struct txx9spi *c;
	struct resource *res;
	int ret = -ENODEV;
	u32 mcr;
	int irq;

	master = spi_alloc_master(&dev->dev, sizeof(*c));
	if (!master)
		return ret;
	c = spi_master_get_devdata(master);
	platform_set_drvdata(dev, master);

	INIT_WORK(&c->work, txx9spi_work);
	spin_lock_init(&c->lock);
	INIT_LIST_HEAD(&c->queue);
	init_waitqueue_head(&c->waitq);

	c->clk = clk_get(&dev->dev, "spi-baseclk");
	if (IS_ERR(c->clk)) {
		ret = PTR_ERR(c->clk);
		c->clk = NULL;
		goto exit;
	}
	ret = clk_enable(c->clk);
	if (ret) {
		clk_put(c->clk);
		c->clk = NULL;
		goto exit;
	}
	c->baseclk = clk_get_rate(c->clk);
	c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
	c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		goto exit_busy;
	if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
				     "spi_txx9"))
		goto exit_busy;
	c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
	if (!c->membase)
		goto exit_busy;

	/* enter config mode */
	mcr = txx9spi_rd(c, TXx9_SPMCR);
	mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
	txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);

	irq = platform_get_irq(dev, 0);
	if (irq < 0)
		goto exit_busy;
	ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
			       "spi_txx9", c);
	if (ret)
		goto exit;

	c->workqueue = create_singlethread_workqueue(
				dev_name(master->dev.parent));
	if (!c->workqueue)
		goto exit_busy;
	c->last_chipselect = -1;

	dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
		 (unsigned long long)res->start, irq,
		 (c->baseclk + 500000) / 1000000);

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;

	master->bus_num = dev->id;
	master->setup = txx9spi_setup;
	master->transfer = txx9spi_transfer;
	master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */

	ret = spi_register_master(master);
	if (ret)
		goto exit;
	return 0;
exit_busy:
	ret = -EBUSY;
exit:
	if (c->workqueue)
		destroy_workqueue(c->workqueue);
	if (c->clk) {
		clk_disable(c->clk);
		clk_put(c->clk);
	}
	platform_set_drvdata(dev, NULL);
	spi_master_put(master);
	return ret;
}

static int txx9spi_remove(struct platform_device *dev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(dev));
	struct txx9spi *c = spi_master_get_devdata(master);

	spi_unregister_master(master);
	platform_set_drvdata(dev, NULL);
	destroy_workqueue(c->workqueue);
	clk_disable(c->clk);
	clk_put(c->clk);
	spi_master_put(master);
	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:spi_txx9");

static struct platform_driver txx9spi_driver = {
	.remove = txx9spi_remove,
	.driver = {
		.name = "spi_txx9",
		.owner = THIS_MODULE,
	},
};

static int __init txx9spi_init(void)
{
	return platform_driver_probe(&txx9spi_driver, txx9spi_probe);
}
subsys_initcall(txx9spi_init);

static void __exit txx9spi_exit(void)
{
	platform_driver_unregister(&txx9spi_driver);
}
module_exit(txx9spi_exit);

MODULE_DESCRIPTION("TXx9 SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
f2cac67d	1	/*
ca632f55	2	* TXx9 SPI controller driver.
f2cac67d AN	3	*
	4	* Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
	5	* Copyright (C) 2000-2001 Toshiba Corporation
	6	*
	7	* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
	13	*
	14	* Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
	15	*/
	16	#include <linux/init.h>
	17	#include <linux/delay.h>
	18	#include <linux/errno.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/sched.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/workqueue.h>
	24	#include <linux/spi/spi.h>
	25	#include <linux/err.h>
	26	#include <linux/clk.h>
ba0a7f39	27	#include <linux/io.h>
d7614de4	28	#include <linux/module.h>
f2cac67d AN	29	#include <asm/gpio.h>
	30
	31
	32	#define SPI_FIFO_SIZE 4
dbf763a2 AN	33	#define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
dbf763a2 AN	34	#define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
f2cac67d AN	35
	36	#define TXx9_SPMCR 0x00
	37	#define TXx9_SPCR0 0x04
	38	#define TXx9_SPCR1 0x08
	39	#define TXx9_SPFS 0x0c
	40	#define TXx9_SPSR 0x14
	41	#define TXx9_SPDR 0x18
	42
	43	/* SPMCR : SPI Master Control */
	44	#define TXx9_SPMCR_OPMODE 0xc0
	45	#define TXx9_SPMCR_CONFIG 0x40
	46	#define TXx9_SPMCR_ACTIVE 0x80
	47	#define TXx9_SPMCR_SPSTP 0x02
	48	#define TXx9_SPMCR_BCLR 0x01
	49
	50	/* SPCR0 : SPI Control 0 */
	51	#define TXx9_SPCR0_TXIFL_MASK 0xc000
	52	#define TXx9_SPCR0_RXIFL_MASK 0x3000
	53	#define TXx9_SPCR0_SIDIE 0x0800
	54	#define TXx9_SPCR0_SOEIE 0x0400
	55	#define TXx9_SPCR0_RBSIE 0x0200
	56	#define TXx9_SPCR0_TBSIE 0x0100
	57	#define TXx9_SPCR0_IFSPSE 0x0010
	58	#define TXx9_SPCR0_SBOS 0x0004
	59	#define TXx9_SPCR0_SPHA 0x0002
	60	#define TXx9_SPCR0_SPOL 0x0001
	61
	62	/* SPSR : SPI Status */
	63	#define TXx9_SPSR_TBSI 0x8000
	64	#define TXx9_SPSR_RBSI 0x4000
	65	#define TXx9_SPSR_TBS_MASK 0x3800
	66	#define TXx9_SPSR_RBS_MASK 0x0700
	67	#define TXx9_SPSR_SPOE 0x0080
	68	#define TXx9_SPSR_IFSD 0x0008
	69	#define TXx9_SPSR_SIDLE 0x0004
	70	#define TXx9_SPSR_STRDY 0x0002
	71	#define TXx9_SPSR_SRRDY 0x0001
	72
	73
	74	struct txx9spi {
	75	struct workqueue_struct *workqueue;
	76	struct work_struct work;
	77	spinlock_t lock; /* protect 'queue' */
	78	struct list_head queue;
	79	wait_queue_head_t waitq;
	80	void __iomem *membase;
f2cac67d AN	81	int baseclk;
	82	struct clk *clk;
	83	u32 max_speed_hz, min_speed_hz;
	84	int last_chipselect;
	85	int last_chipselect_val;
	86	};
	87
	88	static u32 txx9spi_rd(struct txx9spi *c, int reg)
	89	{
	90	return __raw_readl(c->membase + reg);
	91	}
	92	static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
	93	{
	94	__raw_writel(val, c->membase + reg);
	95	}
	96
	97	static void txx9spi_cs_func(struct spi_device spi, struct txx9spi c,
	98	int on, unsigned int cs_delay)
	99	{
	100	int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
	101	if (on) {
	102	/* deselect the chip with cs_change hint in last transfer */
	103	if (c->last_chipselect >= 0)
	104	gpio_set_value(c->last_chipselect,
	105	!c->last_chipselect_val);
	106	c->last_chipselect = spi->chip_select;
	107	c->last_chipselect_val = val;
	108	} else {
	109	c->last_chipselect = -1;
	110	ndelay(cs_delay); /* CS Hold Time */
	111	}
	112	gpio_set_value(spi->chip_select, val);
	113	ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
	114	}
	115
f2cac67d AN	116	static int txx9spi_setup(struct spi_device *spi)
	117	{
	118	struct txx9spi *c = spi_master_get_devdata(spi->master);
	119	u8 bits_per_word;
	120
f2cac67d AN	121	if (!spi->max_speed_hz
	122	\|\| spi->max_speed_hz > c->max_speed_hz
	123	\|\| spi->max_speed_hz < c->min_speed_hz)
	124	return -EINVAL;
	125
7d077197	126	bits_per_word = spi->bits_per_word;
f2cac67d AN	127	if (bits_per_word != 8 && bits_per_word != 16)
	128	return -EINVAL;
	129
	130	if (gpio_direction_output(spi->chip_select,
	131	!(spi->mode & SPI_CS_HIGH))) {
	132	dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
	133	return -EINVAL;
	134	}
	135
	136	/* deselect chip */
	137	spin_lock(&c->lock);
	138	txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
	139	spin_unlock(&c->lock);
	140
	141	return 0;
	142	}
	143
	144	static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
	145	{
	146	struct txx9spi *c = dev_id;
	147
	148	/* disable rx intr */
	149	txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
	150	TXx9_SPCR0);
	151	wake_up(&c->waitq);
	152	return IRQ_HANDLED;
	153	}
	154
	155	static void txx9spi_work_one(struct txx9spi c, struct spi_message m)
	156	{
	157	struct spi_device *spi = m->spi;
	158	struct spi_transfer *t;
	159	unsigned int cs_delay;
	160	unsigned int cs_change = 1;
	161	int status = 0;
	162	u32 mcr;
	163	u32 prev_speed_hz = 0;
	164	u8 prev_bits_per_word = 0;
	165
	166	/* CS setup/hold/recovery time in nsec */
	167	cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
	168
	169	mcr = txx9spi_rd(c, TXx9_SPMCR);
	170	if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
	171	dev_err(&spi->dev, "Bad mode.\n");
	172	status = -EIO;
	173	goto exit;
	174	}
	175	mcr &= ~(TXx9_SPMCR_OPMODE \| TXx9_SPMCR_SPSTP \| TXx9_SPMCR_BCLR);
	176
	177	/* enter config mode */
	178	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
	179	txx9spi_wr(c, TXx9_SPCR0_SBOS
	180	\| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
	181	\| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
	182	\| 0x08,
	183	TXx9_SPCR0);
	184
	185	list_for_each_entry (t, &m->transfers, transfer_list) {
	186	const void *txbuf = t->tx_buf;
	187	void *rxbuf = t->rx_buf;
	188	u32 data;
	189	unsigned int len = t->len;
	190	unsigned int wsize;
191	u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
766ed704	192	u8 bits_per_word = t->bits_per_word;
f2cac67d	193
f2cac67d AN	194	wsize = bits_per_word >> 3; /* in bytes */
	195
	196	if (prev_speed_hz != speed_hz
	197	\|\| prev_bits_per_word != bits_per_word) {
dbf763a2 AN	198	int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
dbf763a2 AN	199	n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
f2cac67d AN	200	/* enter config mode */
	201	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR,
	202	TXx9_SPMCR);
	203	txx9spi_wr(c, (n << 8) \| bits_per_word, TXx9_SPCR1);
	204	/* enter active mode */
	205	txx9spi_wr(c, mcr \| TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
	206
	207	prev_speed_hz = speed_hz;
	208	prev_bits_per_word = bits_per_word;
	209	}
	210
	211	if (cs_change)
	212	txx9spi_cs_func(spi, c, 1, cs_delay);
	213	cs_change = t->cs_change;
	214	while (len) {
	215	unsigned int count = SPI_FIFO_SIZE;
	216	int i;
	217	u32 cr0;
	218
	219	if (len < count * wsize)
	220	count = len / wsize;
	221	/* now tx must be idle... */
	222	while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
	223	cpu_relax();
	224	cr0 = txx9spi_rd(c, TXx9_SPCR0);
	225	cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
	226	cr0 \|= (count - 1) << 12;
	227	/* enable rx intr */
	228	cr0 \|= TXx9_SPCR0_RBSIE;
	229	txx9spi_wr(c, cr0, TXx9_SPCR0);
	230	/* send */
	231	for (i = 0; i < count; i++) {
	232	if (txbuf) {
	233	data = (wsize == 1)
	234	? (const u8 )txbuf
	235	: (const u16 )txbuf;
	236	txx9spi_wr(c, data, TXx9_SPDR);
	237	txbuf += wsize;
	238	} else
	239	txx9spi_wr(c, 0, TXx9_SPDR);
	240	}
	241	/* wait all rx data */
	242	wait_event(c->waitq,
	243	txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
	244	/* receive */
	245	for (i = 0; i < count; i++) {
	246	data = txx9spi_rd(c, TXx9_SPDR);
	247	if (rxbuf) {
	248	if (wsize == 1)
	249	(u8 )rxbuf = data;
	250	else
	251	(u16 )rxbuf = data;
	252	rxbuf += wsize;
	253	}
	254	}
	255	len -= count * wsize;
	256	}
	257	m->actual_length += t->len;
	258	if (t->delay_usecs)
	259	udelay(t->delay_usecs);
	260
	261	if (!cs_change)
	262	continue;
	263	if (t->transfer_list.next == &m->transfers)
264	break;
265	/* sometimes a short mid-message deselect of the chip
266	* may be needed to terminate a mode or command
267	*/
268	txx9spi_cs_func(spi, c, 0, cs_delay);
269	}
270
271	exit:
272	m->status = status;
273	m->complete(m->context);
274
275	/* normally deactivate chipselect ... unless no error and
276	* cs_change has hinted that the next message will probably
277	* be for this chip too.
278	*/
279	if (!(status == 0 && cs_change))
280	txx9spi_cs_func(spi, c, 0, cs_delay);
281
282	/* enter config mode */
283	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
284	}
285
286	static void txx9spi_work(struct work_struct *work)
287	{
288	struct txx9spi *c = container_of(work, struct txx9spi, work);
289	unsigned long flags;
290
291	spin_lock_irqsave(&c->lock, flags);
292	while (!list_empty(&c->queue)) {
293	struct spi_message *m;
294
295	m = container_of(c->queue.next, struct spi_message, queue);
296	list_del_init(&m->queue);
297	spin_unlock_irqrestore(&c->lock, flags);
298
299	txx9spi_work_one(c, m);
300
301	spin_lock_irqsave(&c->lock, flags);
302	}
303	spin_unlock_irqrestore(&c->lock, flags);
304	}
305
306	static int txx9spi_transfer(struct spi_device spi, struct spi_message m)
307	{
308	struct spi_master *master = spi->master;
309	struct txx9spi *c = spi_master_get_devdata(master);
310	struct spi_transfer *t;
311	unsigned long flags;
312
313	m->actual_length = 0;
314
315	/* check each transfer's parameters */
316	list_for_each_entry (t, &m->transfers, transfer_list) {
317	u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
766ed704	318	u8 bits_per_word = t->bits_per_word;
f2cac67d	319
f2cac67d AN	320	if (!t->tx_buf && !t->rx_buf && t->len)
	321	return -EINVAL;
	322	if (bits_per_word != 8 && bits_per_word != 16)
	323	return -EINVAL;
	324	if (t->len & ((bits_per_word >> 3) - 1))
	325	return -EINVAL;
	326	if (speed_hz < c->min_speed_hz \|\| speed_hz > c->max_speed_hz)
	327	return -EINVAL;
	328	}
	329
	330	spin_lock_irqsave(&c->lock, flags);
	331	list_add_tail(&m->queue, &c->queue);
	332	queue_work(c->workqueue, &c->work);
	333	spin_unlock_irqrestore(&c->lock, flags);
	334
	335	return 0;
	336	}
	337
2deff8d6	338	static int txx9spi_probe(struct platform_device *dev)
f2cac67d AN	339	{
	340	struct spi_master *master;
	341	struct txx9spi *c;
	342	struct resource *res;
	343	int ret = -ENODEV;
	344	u32 mcr;
ba0a7f39	345	int irq;
f2cac67d AN	346
	347	master = spi_alloc_master(&dev->dev, sizeof(*c));
	348	if (!master)
	349	return ret;
	350	c = spi_master_get_devdata(master);
f2cac67d AN	351	platform_set_drvdata(dev, master);
	352
	353	INIT_WORK(&c->work, txx9spi_work);
	354	spin_lock_init(&c->lock);
	355	INIT_LIST_HEAD(&c->queue);
	356	init_waitqueue_head(&c->waitq);
	357
	358	c->clk = clk_get(&dev->dev, "spi-baseclk");
	359	if (IS_ERR(c->clk)) {
	360	ret = PTR_ERR(c->clk);
	361	c->clk = NULL;
	362	goto exit;
	363	}
	364	ret = clk_enable(c->clk);
	365	if (ret) {
	366	clk_put(c->clk);
	367	c->clk = NULL;
	368	goto exit;
	369	}
	370	c->baseclk = clk_get_rate(c->clk);
dbf763a2 AN	371	c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
dbf763a2 AN	372	c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
f2cac67d AN	373
	374	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	375	if (!res)
ba0a7f39	376	goto exit_busy;
d53342bf	377	if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
ba0a7f39 AN	378	"spi_txx9"))
ba0a7f39 AN	379	goto exit_busy;
d53342bf	380	c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
f2cac67d	381	if (!c->membase)
ba0a7f39	382	goto exit_busy;
f2cac67d AN	383
	384	/* enter config mode */
	385	mcr = txx9spi_rd(c, TXx9_SPMCR);
	386	mcr &= ~(TXx9_SPMCR_OPMODE \| TXx9_SPMCR_SPSTP \| TXx9_SPMCR_BCLR);
	387	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
	388
ba0a7f39 AN	389	irq = platform_get_irq(dev, 0);
	390	if (irq < 0)
	391	goto exit_busy;
	392	ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
	393	"spi_txx9", c);
	394	if (ret)
f2cac67d	395	goto exit;
f2cac67d	396
6c7377ab KS	397	c->workqueue = create_singlethread_workqueue(
6c7377ab KS	398	dev_name(master->dev.parent));
f2cac67d	399	if (!c->workqueue)
ba0a7f39	400	goto exit_busy;
f2cac67d AN	401	c->last_chipselect = -1;
	402
	403	dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
ba0a7f39	404	(unsigned long long)res->start, irq,
f2cac67d AN	405	(c->baseclk + 500000) / 1000000);
f2cac67d AN	406
e7db06b5 DB	407	/* the spi->mode bits understood by this driver: */
	408	master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
	409
f2cac67d AN	410	master->bus_num = dev->id;
	411	master->setup = txx9spi_setup;
	412	master->transfer = txx9spi_transfer;
	413	master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
	414
	415	ret = spi_register_master(master);
	416	if (ret)
	417	goto exit;
	418	return 0;
ba0a7f39 AN	419	exit_busy:
ba0a7f39 AN	420	ret = -EBUSY;
f2cac67d AN	421	exit:
	422	if (c->workqueue)
	423	destroy_workqueue(c->workqueue);
f2cac67d AN	424	if (c->clk) {
	425	clk_disable(c->clk);
	426	clk_put(c->clk);
	427	}
	428	platform_set_drvdata(dev, NULL);
	429	spi_master_put(master);
	430	return ret;
	431	}
	432
2deff8d6	433	static int txx9spi_remove(struct platform_device *dev)
f2cac67d AN	434	{
	435	struct spi_master *master = spi_master_get(platform_get_drvdata(dev));
	436	struct txx9spi *c = spi_master_get_devdata(master);
	437
	438	spi_unregister_master(master);
	439	platform_set_drvdata(dev, NULL);
	440	destroy_workqueue(c->workqueue);
f2cac67d AN	441	clk_disable(c->clk);
	442	clk_put(c->clk);
	443	spi_master_put(master);
	444	return 0;
	445	}
	446
7e38c3c4 KS	447	/* work with hotplug and coldplug */
	448	MODULE_ALIAS("platform:spi_txx9");
	449
f2cac67d	450	static struct platform_driver txx9spi_driver = {
2deff8d6	451	.remove = txx9spi_remove,
f2cac67d	452	.driver = {
4ccdb4c8	453	.name = "spi_txx9",
f2cac67d AN	454	.owner = THIS_MODULE,
	455	},
	456	};
	457
	458	static int __init txx9spi_init(void)
	459	{
	460	return platform_driver_probe(&txx9spi_driver, txx9spi_probe);
	461	}
	462	subsys_initcall(txx9spi_init);
	463
	464	static void __exit txx9spi_exit(void)
	465	{
	466	platform_driver_unregister(&txx9spi_driver);
	467	}
	468	module_exit(txx9spi_exit);
	469
	470	MODULE_DESCRIPTION("TXx9 SPI Driver");
	471	MODULE_LICENSE("GPL");