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spi/gpio: Fix stub for spi_gpio_probe_dt()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-omap2-mcspi.c
CommitLineData
ccdc7bf9
SO		 1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
1a5d8190 6 * Juha Yrj�l� <juha.yrjola@nokia.com>
ccdc7bf9
SO		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
53741ed8
RK		 31#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
ccdc7bf9
SO		 33#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
36#include <linux/io.h>
5a0e3ad6 37#include <linux/slab.h>
1f1a4384 38#include <linux/pm_runtime.h>
d5a80031
BC		 39#include <linux/of.h>
40#include <linux/of_device.h>
ccdc7bf9
SO		 41
42#include <linux/spi/spi.h>
43
ce491cf8 44#include <plat/clock.h>
4743a0f8 45#include <plat/mcspi.h>
ccdc7bf9
SO		 46
47#define OMAP2_MCSPI_MAX_FREQ 48000000
27b5284c 48#define SPI_AUTOSUSPEND_TIMEOUT 2000
ccdc7bf9
SO		 49
50#define OMAP2_MCSPI_REVISION 0x00
ccdc7bf9
SO		 51#define OMAP2_MCSPI_SYSSTATUS 0x14
52#define OMAP2_MCSPI_IRQSTATUS 0x18
53#define OMAP2_MCSPI_IRQENABLE 0x1c
54#define OMAP2_MCSPI_WAKEUPENABLE 0x20
55#define OMAP2_MCSPI_SYST 0x24
56#define OMAP2_MCSPI_MODULCTRL 0x28
57
58/* per-channel banks, 0x14 bytes each, first is: */
59#define OMAP2_MCSPI_CHCONF0 0x2c
60#define OMAP2_MCSPI_CHSTAT0 0x30
61#define OMAP2_MCSPI_CHCTRL0 0x34
62#define OMAP2_MCSPI_TX0 0x38
63#define OMAP2_MCSPI_RX0 0x3c
64
65/* per-register bitmasks: */
66
7a8fa725
JH		 67#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
ccdc7bf9 70
7a8fa725
JH		 71#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72#define OMAP2_MCSPI_CHCONF_POL BIT(1)
ccdc7bf9 73#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
7a8fa725 74#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
ccdc7bf9 75#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
7a8fa725
JH		 76#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
ccdc7bf9 78#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
7a8fa725
JH		 79#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83#define OMAP2_MCSPI_CHCONF_IS BIT(18)
84#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
ccdc7bf9 86
7a8fa725
JH		 87#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
88#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
89#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
ccdc7bf9 90
7a8fa725 91#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
ccdc7bf9 92
7a8fa725 93#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
ccdc7bf9
SO		 94
95/* We have 2 DMA channels per CS, one for RX and one for TX */
96struct omap2_mcspi_dma {
53741ed8
RK		 97 struct dma_chan *dma_tx;
98 struct dma_chan *dma_rx;
ccdc7bf9
SO		 99
100 int dma_tx_sync_dev;
101 int dma_rx_sync_dev;
102
103 struct completion dma_tx_completion;
104 struct completion dma_rx_completion;
105};
106
107/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
108 * cache operations; better heuristics consider wordsize and bitrate.
109 */
8b66c134 110#define DMA_MIN_BYTES 160
ccdc7bf9
SO		 111
112
1bd897f8
BC		 113/*
114 * Used for context save and restore, structure members to be updated whenever
115 * corresponding registers are modified.
116 */
117struct omap2_mcspi_regs {
118 u32 modulctrl;
119 u32 wakeupenable;
120 struct list_head cs;
121};
122
ccdc7bf9 123struct omap2_mcspi {
ccdc7bf9 124 struct spi_master *master;
ccdc7bf9
SO		 125 /* Virtual base address of the controller */
126 void __iomem *base;
e5480b73 127 unsigned long phys;
ccdc7bf9
SO		 128 /* SPI1 has 4 channels, while SPI2 has 2 */
129 struct omap2_mcspi_dma *dma_channels;
1bd897f8 130 struct device *dev;
1bd897f8 131 struct omap2_mcspi_regs ctx;
ccdc7bf9
SO		 132};
133
134struct omap2_mcspi_cs {
135 void __iomem *base;
e5480b73 136 unsigned long phys;
ccdc7bf9 137 int word_len;
89c05372 138 struct list_head node;
a41ae1ad
H		 139 /* Context save and restore shadow register */
140 u32 chconf0;
141};
142
ccdc7bf9
SO		 143static inline void mcspi_write_reg(struct spi_master *master,
144 int idx, u32 val)
145{
146 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
147
148 __raw_writel(val, mcspi->base + idx);
149}
150
151static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
152{
153 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
154
155 return __raw_readl(mcspi->base + idx);
156}
157
158static inline void mcspi_write_cs_reg(const struct spi_device *spi,
159 int idx, u32 val)
160{
161 struct omap2_mcspi_cs *cs = spi->controller_state;
162
163 __raw_writel(val, cs->base + idx);
164}
165
166static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
167{
168 struct omap2_mcspi_cs *cs = spi->controller_state;
169
170 return __raw_readl(cs->base + idx);
171}
172
a41ae1ad
H		 173static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
174{
175 struct omap2_mcspi_cs *cs = spi->controller_state;
176
177 return cs->chconf0;
178}
179
180static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
181{
182 struct omap2_mcspi_cs *cs = spi->controller_state;
183
184 cs->chconf0 = val;
185 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
a330ce20 186 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
a41ae1ad
H		 187}
188
ccdc7bf9
SO		 189static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
190 int is_read, int enable)
191{
192 u32 l, rw;
193
a41ae1ad 194 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 195
196 if (is_read) /* 1 is read, 0 write */
197 rw = OMAP2_MCSPI_CHCONF_DMAR;
198 else
199 rw = OMAP2_MCSPI_CHCONF_DMAW;
200
af4e944d
S		 201 if (enable)
202 l |= rw;
203 else
204 l &= ~rw;
205
a41ae1ad 206 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 207}
208
209static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
210{
211 u32 l;
212
213 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
214 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
4743a0f8
RT		 215 /* Flash post-writes */
216 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
ccdc7bf9
SO		 217}
218
219static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
220{
221 u32 l;
222
a41ae1ad 223 l = mcspi_cached_chconf0(spi);
af4e944d
S		 224 if (cs_active)
225 l |= OMAP2_MCSPI_CHCONF_FORCE;
226 else
227 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
228
a41ae1ad 229 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 230}
231
232static void omap2_mcspi_set_master_mode(struct spi_master *master)
233{
1bd897f8
BC		 234 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
235 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 236 u32 l;
237
1bd897f8
BC		 238 /*
239 * Setup when switching from (reset default) slave mode
ccdc7bf9
SO		 240 * to single-channel master mode
241 */
242 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
af4e944d
S		 243 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
244 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
ccdc7bf9 245 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
a41ae1ad 246
1bd897f8 247 ctx->modulctrl = l;
a41ae1ad
H		 248}
249
250static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
251{
1bd897f8
BC		 252 struct spi_master *spi_cntrl = mcspi->master;
253 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
254 struct omap2_mcspi_cs *cs;
a41ae1ad
H		 255
256 /* McSPI: context restore */
1bd897f8
BC		 257 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
258 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
a41ae1ad 259
1bd897f8 260 list_for_each_entry(cs, &ctx->cs, node)
89c05372 261 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
a41ae1ad 262}
ccdc7bf9 263
5fda88f5
S		 264static int omap2_prepare_transfer(struct spi_master *master)
265{
266 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
267
268 pm_runtime_get_sync(mcspi->dev);
269 return 0;
270}
271
272static int omap2_unprepare_transfer(struct spi_master *master)
273{
274 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
275
276 pm_runtime_mark_last_busy(mcspi->dev);
277 pm_runtime_put_autosuspend(mcspi->dev);
278 return 0;
279}
280
2764c500
IK		 281static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
282{
283 unsigned long timeout;
284
285 timeout = jiffies + msecs_to_jiffies(1000);
286 while (!(__raw_readl(reg) & bit)) {
287 if (time_after(jiffies, timeout))
288 return -1;
289 cpu_relax();
290 }
291 return 0;
292}
293
53741ed8
RK		 294static void omap2_mcspi_rx_callback(void *data)
295{
296 struct spi_device *spi = data;
297 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
298 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
299
300 complete(&mcspi_dma->dma_rx_completion);
301
302 /* We must disable the DMA RX request */
303 omap2_mcspi_set_dma_req(spi, 1, 0);
304}
305
306static void omap2_mcspi_tx_callback(void *data)
307{
308 struct spi_device *spi = data;
309 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
310 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
311
312 complete(&mcspi_dma->dma_tx_completion);
313
314 /* We must disable the DMA TX request */
315 omap2_mcspi_set_dma_req(spi, 0, 0);
316}
317
ccdc7bf9
SO		 318static unsigned
319omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
320{
321 struct omap2_mcspi *mcspi;
322 struct omap2_mcspi_cs *cs = spi->controller_state;
323 struct omap2_mcspi_dma *mcspi_dma;
8c7494a5
RK		 324 unsigned int count;
325 int word_len, element_count;
8b20c8cb 326 int elements = 0;
4743a0f8 327 u32 l;
ccdc7bf9
SO		 328 u8 * rx;
329 const u8 * tx;
2764c500 330 void __iomem *chstat_reg;
53741ed8
RK		 331 struct dma_slave_config cfg;
332 enum dma_slave_buswidth width;
333 unsigned es;
ccdc7bf9
SO		 334
335 mcspi = spi_master_get_devdata(spi->master);
336 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
4743a0f8 337 l = mcspi_cached_chconf0(spi);
ccdc7bf9 338
2764c500
IK		 339 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
340
53741ed8
RK		 341 if (cs->word_len <= 8) {
342 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
343 es = 1;
344 } else if (cs->word_len <= 16) {
345 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
346 es = 2;
347 } else {
348 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
349 es = 4;
350 }
351
352 memset(&cfg, 0, sizeof(cfg));
353 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
354 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
355 cfg.src_addr_width = width;
356 cfg.dst_addr_width = width;
357 cfg.src_maxburst = 1;
358 cfg.dst_maxburst = 1;
359
360 if (xfer->tx_buf && mcspi_dma->dma_tx) {
361 struct dma_async_tx_descriptor *tx;
362 struct scatterlist sg;
363
364 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
365
366 sg_init_table(&sg, 1);
367 sg_dma_address(&sg) = xfer->tx_dma;
368 sg_dma_len(&sg) = xfer->len;
369
370 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
371 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
372 if (tx) {
373 tx->callback = omap2_mcspi_tx_callback;
374 tx->callback_param = spi;
375 dmaengine_submit(tx);
376 } else {
377 /* FIXME: fall back to PIO? */
378 }
379 }
380
381 if (xfer->rx_buf && mcspi_dma->dma_rx) {
382 struct dma_async_tx_descriptor *tx;
383 struct scatterlist sg;
384 size_t len = xfer->len - es;
385
386 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
387
388 if (l & OMAP2_MCSPI_CHCONF_TURBO)
389 len -= es;
390
391 sg_init_table(&sg, 1);
392 sg_dma_address(&sg) = xfer->rx_dma;
393 sg_dma_len(&sg) = len;
394
395 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
396 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
397 if (tx) {
398 tx->callback = omap2_mcspi_rx_callback;
399 tx->callback_param = spi;
400 dmaengine_submit(tx);
401 } else {
402 /* FIXME: fall back to PIO? */
403 }
404 }
405
ccdc7bf9 406 count = xfer->len;
ccdc7bf9
SO		 407 word_len = cs->word_len;
408
ccdc7bf9
SO		 409 rx = xfer->rx_buf;
410 tx = xfer->tx_buf;
411
412 if (word_len <= 8) {
ccdc7bf9
SO		 413 element_count = count;
414 } else if (word_len <= 16) {
ccdc7bf9
SO		 415 element_count = count >> 1;
416 } else /* word_len <= 32 */ {
ccdc7bf9
SO		 417 element_count = count >> 2;
418 }
419
420 if (tx != NULL) {
8c7494a5 421 dma_async_issue_pending(mcspi_dma->dma_tx);
ccdc7bf9
SO		 422 omap2_mcspi_set_dma_req(spi, 0, 1);
423 }
424
425 if (rx != NULL) {
8c7494a5 426 dma_async_issue_pending(mcspi_dma->dma_rx);
ccdc7bf9
SO		 427 omap2_mcspi_set_dma_req(spi, 1, 1);
428 }
429
430 if (tx != NULL) {
431 wait_for_completion(&mcspi_dma->dma_tx_completion);
a3ce9a80
S		 432 dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
433 DMA_TO_DEVICE);
2764c500
IK		 434
435 /* for TX_ONLY mode, be sure all words have shifted out */
436 if (rx == NULL) {
437 if (mcspi_wait_for_reg_bit(chstat_reg,
438 OMAP2_MCSPI_CHSTAT_TXS) < 0)
439 dev_err(&spi->dev, "TXS timed out\n");
440 else if (mcspi_wait_for_reg_bit(chstat_reg,
441 OMAP2_MCSPI_CHSTAT_EOT) < 0)
442 dev_err(&spi->dev, "EOT timed out\n");
443 }
ccdc7bf9
SO		 444 }
445
446 if (rx != NULL) {
447 wait_for_completion(&mcspi_dma->dma_rx_completion);
a3ce9a80
S		 448 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
449 DMA_FROM_DEVICE);
57c5c28d 450 omap2_mcspi_set_enable(spi, 0);
4743a0f8 451
53741ed8
RK		 452 elements = element_count - 1;
453
4743a0f8 454 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
53741ed8 455 elements--;
4743a0f8
RT		 456
457 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
458 & OMAP2_MCSPI_CHSTAT_RXS)) {
459 u32 w;
460
461 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
462 if (word_len <= 8)
463 ((u8 *)xfer->rx_buf)[elements++] = w;
464 else if (word_len <= 16)
465 ((u16 *)xfer->rx_buf)[elements++] = w;
466 else /* word_len <= 32 */
467 ((u32 *)xfer->rx_buf)[elements++] = w;
468 } else {
469 dev_err(&spi->dev,
470 "DMA RX penultimate word empty");
471 count -= (word_len <= 8) ? 2 :
472 (word_len <= 16) ? 4 :
473 /* word_len <= 32 */ 8;
474 omap2_mcspi_set_enable(spi, 1);
475 return count;
476 }
477 }
478
57c5c28d
EN		 479 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
480 & OMAP2_MCSPI_CHSTAT_RXS)) {
481 u32 w;
482
483 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
484 if (word_len <= 8)
4743a0f8 485 ((u8 *)xfer->rx_buf)[elements] = w;
57c5c28d 486 else if (word_len <= 16)
4743a0f8 487 ((u16 *)xfer->rx_buf)[elements] = w;
57c5c28d 488 else /* word_len <= 32 */
4743a0f8 489 ((u32 *)xfer->rx_buf)[elements] = w;
57c5c28d
EN		 490 } else {
491 dev_err(&spi->dev, "DMA RX last word empty");
492 count -= (word_len <= 8) ? 1 :
493 (word_len <= 16) ? 2 :
494 /* word_len <= 32 */ 4;
495 }
496 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 497 }
498 return count;
499}
500
ccdc7bf9
SO		 501static unsigned
502omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
503{
504 struct omap2_mcspi *mcspi;
505 struct omap2_mcspi_cs *cs = spi->controller_state;
506 unsigned int count, c;
507 u32 l;
508 void __iomem *base = cs->base;
509 void __iomem *tx_reg;
510 void __iomem *rx_reg;
511 void __iomem *chstat_reg;
512 int word_len;
513
514 mcspi = spi_master_get_devdata(spi->master);
515 count = xfer->len;
516 c = count;
517 word_len = cs->word_len;
518
a41ae1ad 519 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 520
521 /* We store the pre-calculated register addresses on stack to speed
522 * up the transfer loop. */
523 tx_reg = base + OMAP2_MCSPI_TX0;
524 rx_reg = base + OMAP2_MCSPI_RX0;
525 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
526
adef658d
MJ		 527 if (c < (word_len>>3))
528 return 0;
529
ccdc7bf9
SO		 530 if (word_len <= 8) {
531 u8 *rx;
532 const u8 *tx;
533
534 rx = xfer->rx_buf;
535 tx = xfer->tx_buf;
536
537 do {
feed9bab 538 c -= 1;
ccdc7bf9
SO		 539 if (tx != NULL) {
540 if (mcspi_wait_for_reg_bit(chstat_reg,
541 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
542 dev_err(&spi->dev, "TXS timed out\n");
543 goto out;
544 }
079a176d 545 dev_vdbg(&spi->dev, "write-%d %02x\n",
ccdc7bf9 546 word_len, *tx);
ccdc7bf9
SO		 547 __raw_writel(*tx++, tx_reg);
548 }
549 if (rx != NULL) {
550 if (mcspi_wait_for_reg_bit(chstat_reg,
551 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
552 dev_err(&spi->dev, "RXS timed out\n");
553 goto out;
554 }
4743a0f8
RT		 555
556 if (c == 1 && tx == NULL &&
557 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
558 omap2_mcspi_set_enable(spi, 0);
559 *rx++ = __raw_readl(rx_reg);
079a176d 560 dev_vdbg(&spi->dev, "read-%d %02x\n",
4743a0f8 561 word_len, *(rx - 1));
4743a0f8
RT		 562 if (mcspi_wait_for_reg_bit(chstat_reg,
563 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
564 dev_err(&spi->dev,
565 "RXS timed out\n");
566 goto out;
567 }
568 c = 0;
569 } else if (c == 0 && tx == NULL) {
570 omap2_mcspi_set_enable(spi, 0);
571 }
572
ccdc7bf9 573 *rx++ = __raw_readl(rx_reg);
079a176d 574 dev_vdbg(&spi->dev, "read-%d %02x\n",
ccdc7bf9 575 word_len, *(rx - 1));
ccdc7bf9 576 }
95c5c3ab 577 } while (c);
ccdc7bf9
SO		 578 } else if (word_len <= 16) {
579 u16 *rx;
580 const u16 *tx;
581
582 rx = xfer->rx_buf;
583 tx = xfer->tx_buf;
584 do {
feed9bab 585 c -= 2;
ccdc7bf9
SO		 586 if (tx != NULL) {
587 if (mcspi_wait_for_reg_bit(chstat_reg,
588 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
589 dev_err(&spi->dev, "TXS timed out\n");
590 goto out;
591 }
079a176d 592 dev_vdbg(&spi->dev, "write-%d %04x\n",
ccdc7bf9 593 word_len, *tx);
ccdc7bf9
SO		 594 __raw_writel(*tx++, tx_reg);
595 }
596 if (rx != NULL) {
597 if (mcspi_wait_for_reg_bit(chstat_reg,
598 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
599 dev_err(&spi->dev, "RXS timed out\n");
600 goto out;
601 }
4743a0f8
RT		 602
603 if (c == 2 && tx == NULL &&
604 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
605 omap2_mcspi_set_enable(spi, 0);
606 *rx++ = __raw_readl(rx_reg);
079a176d 607 dev_vdbg(&spi->dev, "read-%d %04x\n",
4743a0f8 608 word_len, *(rx - 1));
4743a0f8
RT		 609 if (mcspi_wait_for_reg_bit(chstat_reg,
610 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
611 dev_err(&spi->dev,
612 "RXS timed out\n");
613 goto out;
614 }
615 c = 0;
616 } else if (c == 0 && tx == NULL) {
617 omap2_mcspi_set_enable(spi, 0);
618 }
619
ccdc7bf9 620 *rx++ = __raw_readl(rx_reg);
079a176d 621 dev_vdbg(&spi->dev, "read-%d %04x\n",
ccdc7bf9 622 word_len, *(rx - 1));
ccdc7bf9 623 }
95c5c3ab 624 } while (c >= 2);
ccdc7bf9
SO		 625 } else if (word_len <= 32) {
626 u32 *rx;
627 const u32 *tx;
628
629 rx = xfer->rx_buf;
630 tx = xfer->tx_buf;
631 do {
feed9bab 632 c -= 4;
ccdc7bf9
SO		 633 if (tx != NULL) {
634 if (mcspi_wait_for_reg_bit(chstat_reg,
635 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
636 dev_err(&spi->dev, "TXS timed out\n");
637 goto out;
638 }
079a176d 639 dev_vdbg(&spi->dev, "write-%d %08x\n",
ccdc7bf9 640 word_len, *tx);
ccdc7bf9
SO		 641 __raw_writel(*tx++, tx_reg);
642 }
643 if (rx != NULL) {
644 if (mcspi_wait_for_reg_bit(chstat_reg,
645 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
646 dev_err(&spi->dev, "RXS timed out\n");
647 goto out;
648 }
4743a0f8
RT		 649
650 if (c == 4 && tx == NULL &&
651 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
652 omap2_mcspi_set_enable(spi, 0);
653 *rx++ = __raw_readl(rx_reg);
079a176d 654 dev_vdbg(&spi->dev, "read-%d %08x\n",
4743a0f8 655 word_len, *(rx - 1));
4743a0f8
RT		 656 if (mcspi_wait_for_reg_bit(chstat_reg,
657 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
658 dev_err(&spi->dev,
659 "RXS timed out\n");
660 goto out;
661 }
662 c = 0;
663 } else if (c == 0 && tx == NULL) {
664 omap2_mcspi_set_enable(spi, 0);
665 }
666
ccdc7bf9 667 *rx++ = __raw_readl(rx_reg);
079a176d 668 dev_vdbg(&spi->dev, "read-%d %08x\n",
ccdc7bf9 669 word_len, *(rx - 1));
ccdc7bf9 670 }
95c5c3ab 671 } while (c >= 4);
ccdc7bf9
SO		 672 }
673
674 /* for TX_ONLY mode, be sure all words have shifted out */
675 if (xfer->rx_buf == NULL) {
676 if (mcspi_wait_for_reg_bit(chstat_reg,
677 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
678 dev_err(&spi->dev, "TXS timed out\n");
679 } else if (mcspi_wait_for_reg_bit(chstat_reg,
680 OMAP2_MCSPI_CHSTAT_EOT) < 0)
681 dev_err(&spi->dev, "EOT timed out\n");
e1993ed6
JW		 682
683 /* disable chan to purge rx datas received in TX_ONLY transfer,
684 * otherwise these rx datas will affect the direct following
685 * RX_ONLY transfer.
686 */
687 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9
SO		 688 }
689out:
4743a0f8 690 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 691 return count - c;
692}
693
57d9c10d
HH		 694static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
695{
696 u32 div;
697
698 for (div = 0; div < 15; div++)
699 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
700 return div;
701
702 return 15;
703}
704
ccdc7bf9
SO		 705/* called only when no transfer is active to this device */
706static int omap2_mcspi_setup_transfer(struct spi_device *spi,
707 struct spi_transfer *t)
708{
709 struct omap2_mcspi_cs *cs = spi->controller_state;
710 struct omap2_mcspi *mcspi;
a41ae1ad 711 struct spi_master *spi_cntrl;
ccdc7bf9
SO		 712 u32 l = 0, div = 0;
713 u8 word_len = spi->bits_per_word;
9bd4517d 714 u32 speed_hz = spi->max_speed_hz;
ccdc7bf9
SO		 715
716 mcspi = spi_master_get_devdata(spi->master);
a41ae1ad 717 spi_cntrl = mcspi->master;
ccdc7bf9
SO		 718
719 if (t != NULL && t->bits_per_word)
720 word_len = t->bits_per_word;
721
722 cs->word_len = word_len;
723
9bd4517d
SE		 724 if (t && t->speed_hz)
725 speed_hz = t->speed_hz;
726
57d9c10d
HH		 727 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
728 div = omap2_mcspi_calc_divisor(speed_hz);
ccdc7bf9 729
a41ae1ad 730 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 731
732 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
733 * REVISIT: this controller could support SPI_3WIRE mode.
734 */
735 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
736 l |= OMAP2_MCSPI_CHCONF_DPE0;
737
738 /* wordlength */
739 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
740 l |= (word_len - 1) << 7;
741
742 /* set chipselect polarity; manage with FORCE */
743 if (!(spi->mode & SPI_CS_HIGH))
744 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
745 else
746 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
747
748 /* set clock divisor */
749 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
750 l |= div << 2;
751
752 /* set SPI mode 0..3 */
753 if (spi->mode & SPI_CPOL)
754 l |= OMAP2_MCSPI_CHCONF_POL;
755 else
756 l &= ~OMAP2_MCSPI_CHCONF_POL;
757 if (spi->mode & SPI_CPHA)
758 l |= OMAP2_MCSPI_CHCONF_PHA;
759 else
760 l &= ~OMAP2_MCSPI_CHCONF_PHA;
761
a41ae1ad 762 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 763
764 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
57d9c10d 765 OMAP2_MCSPI_MAX_FREQ >> div,
ccdc7bf9
SO		 766 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
767 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
768
769 return 0;
770}
771
ccdc7bf9
SO		 772static int omap2_mcspi_request_dma(struct spi_device *spi)
773{
774 struct spi_master *master = spi->master;
775 struct omap2_mcspi *mcspi;
776 struct omap2_mcspi_dma *mcspi_dma;
53741ed8
RK		 777 dma_cap_mask_t mask;
778 unsigned sig;
ccdc7bf9
SO		 779
780 mcspi = spi_master_get_devdata(master);
781 mcspi_dma = mcspi->dma_channels + spi->chip_select;
782
53741ed8
RK		 783 init_completion(&mcspi_dma->dma_rx_completion);
784 init_completion(&mcspi_dma->dma_tx_completion);
785
786 dma_cap_zero(mask);
787 dma_cap_set(DMA_SLAVE, mask);
53741ed8
RK		 788 sig = mcspi_dma->dma_rx_sync_dev;
789 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
790 if (!mcspi_dma->dma_rx) {
791 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
ccdc7bf9
SO		 792 return -EAGAIN;
793 }
794
53741ed8
RK		 795 sig = mcspi_dma->dma_tx_sync_dev;
796 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
797 if (!mcspi_dma->dma_tx) {
798 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
799 dma_release_channel(mcspi_dma->dma_rx);
800 mcspi_dma->dma_rx = NULL;
ccdc7bf9
SO		 801 return -EAGAIN;
802 }
803
ccdc7bf9
SO		 804 return 0;
805}
806
ccdc7bf9
SO		 807static int omap2_mcspi_setup(struct spi_device *spi)
808{
809 int ret;
1bd897f8
BC		 810 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
811 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
ccdc7bf9
SO		 812 struct omap2_mcspi_dma *mcspi_dma;
813 struct omap2_mcspi_cs *cs = spi->controller_state;
814
7d077197 815 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
ccdc7bf9
SO		 816 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
817 spi->bits_per_word);
818 return -EINVAL;
819 }
820
ccdc7bf9
SO		 821 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
822
823 if (!cs) {
10aa5a35 824 cs = kzalloc(sizeof *cs, GFP_KERNEL);
ccdc7bf9
SO		 825 if (!cs)
826 return -ENOMEM;
827 cs->base = mcspi->base + spi->chip_select * 0x14;
e5480b73 828 cs->phys = mcspi->phys + spi->chip_select * 0x14;
a41ae1ad 829 cs->chconf0 = 0;
ccdc7bf9 830 spi->controller_state = cs;
89c05372 831 /* Link this to context save list */
1bd897f8 832 list_add_tail(&cs->node, &ctx->cs);
ccdc7bf9
SO		 833 }
834
8c7494a5 835 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
ccdc7bf9
SO		 836 ret = omap2_mcspi_request_dma(spi);
837 if (ret < 0)
838 return ret;
839 }
840
034d3dc9 841 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 842 if (ret < 0)
843 return ret;
a41ae1ad 844
86eeb6fe 845 ret = omap2_mcspi_setup_transfer(spi, NULL);
034d3dc9
S		 846 pm_runtime_mark_last_busy(mcspi->dev);
847 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 848
849 return ret;
850}
851
852static void omap2_mcspi_cleanup(struct spi_device *spi)
853{
854 struct omap2_mcspi *mcspi;
855 struct omap2_mcspi_dma *mcspi_dma;
89c05372 856 struct omap2_mcspi_cs *cs;
ccdc7bf9
SO		 857
858 mcspi = spi_master_get_devdata(spi->master);
ccdc7bf9 859
5e774943
SE		 860 if (spi->controller_state) {
861 /* Unlink controller state from context save list */
862 cs = spi->controller_state;
863 list_del(&cs->node);
89c05372 864
10aa5a35 865 kfree(cs);
5e774943 866 }
ccdc7bf9 867
99f1a43f
SE		 868 if (spi->chip_select < spi->master->num_chipselect) {
869 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
870
53741ed8
RK		 871 if (mcspi_dma->dma_rx) {
872 dma_release_channel(mcspi_dma->dma_rx);
873 mcspi_dma->dma_rx = NULL;
99f1a43f 874 }
53741ed8
RK		 875 if (mcspi_dma->dma_tx) {
876 dma_release_channel(mcspi_dma->dma_tx);
877 mcspi_dma->dma_tx = NULL;
99f1a43f 878 }
ccdc7bf9
SO		 879 }
880}
881
5fda88f5 882static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
ccdc7bf9 883{
ccdc7bf9
SO		 884
885 /* We only enable one channel at a time -- the one whose message is
5fda88f5 886 * -- although this controller would gladly
ccdc7bf9
SO		 887 * arbitrate among multiple channels. This corresponds to "single
888 * channel" master mode. As a side effect, we need to manage the
889 * chipselect with the FORCE bit ... CS != channel enable.
890 */
ccdc7bf9 891
5fda88f5
S		 892 struct spi_device *spi;
893 struct spi_transfer *t = NULL;
894 int cs_active = 0;
895 struct omap2_mcspi_cs *cs;
896 struct omap2_mcspi_device_config *cd;
897 int par_override = 0;
898 int status = 0;
899 u32 chconf;
ccdc7bf9 900
5fda88f5
S		 901 spi = m->spi;
902 cs = spi->controller_state;
903 cd = spi->controller_data;
ccdc7bf9 904
5fda88f5
S		 905 omap2_mcspi_set_enable(spi, 1);
906 list_for_each_entry(t, &m->transfers, transfer_list) {
907 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
908 status = -EINVAL;
909 break;
910 }
911 if (par_override || t->speed_hz || t->bits_per_word) {
912 par_override = 1;
913 status = omap2_mcspi_setup_transfer(spi, t);
914 if (status < 0)
915 break;
916 if (!t->speed_hz && !t->bits_per_word)
917 par_override = 0;
918 }
4743a0f8 919
5fda88f5
S		 920 if (!cs_active) {
921 omap2_mcspi_force_cs(spi, 1);
922 cs_active = 1;
923 }
4743a0f8 924
5fda88f5
S		 925 chconf = mcspi_cached_chconf0(spi);
926 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
927 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
ccdc7bf9 928
5fda88f5
S		 929 if (t->tx_buf == NULL)
930 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
931 else if (t->rx_buf == NULL)
932 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
ccdc7bf9 933
5fda88f5
S		 934 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
935 /* Turbo mode is for more than one word */
936 if (t->len > ((cs->word_len + 7) >> 3))
937 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
938 }
ccdc7bf9 939
5fda88f5 940 mcspi_write_chconf0(spi, chconf);
ccdc7bf9 941
5fda88f5
S		 942 if (t->len) {
943 unsigned count;
944
945 /* RX_ONLY mode needs dummy data in TX reg */
946 if (t->tx_buf == NULL)
947 __raw_writel(0, cs->base
948 + OMAP2_MCSPI_TX0);
ccdc7bf9 949
5fda88f5
S		 950 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
951 count = omap2_mcspi_txrx_dma(spi, t);
952 else
953 count = omap2_mcspi_txrx_pio(spi, t);
954 m->actual_length += count;
ccdc7bf9 955
5fda88f5
S		 956 if (count != t->len) {
957 status = -EIO;
958 break;
ccdc7bf9
SO		 959 }
960 }
961
5fda88f5
S		 962 if (t->delay_usecs)
963 udelay(t->delay_usecs);
ccdc7bf9 964
5fda88f5
S		 965 /* ignore the "leave it on after last xfer" hint */
966 if (t->cs_change) {
ccdc7bf9 967 omap2_mcspi_force_cs(spi, 0);
5fda88f5
S		 968 cs_active = 0;
969 }
970 }
971 /* Restore defaults if they were overriden */
972 if (par_override) {
973 par_override = 0;
974 status = omap2_mcspi_setup_transfer(spi, NULL);
975 }
ccdc7bf9 976
5fda88f5
S		 977 if (cs_active)
978 omap2_mcspi_force_cs(spi, 0);
ccdc7bf9 979
5fda88f5 980 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9 981
5fda88f5 982 m->status = status;
1f1a4384 983
ccdc7bf9
SO		 984}
985
5fda88f5
S		 986static int omap2_mcspi_transfer_one_message(struct spi_master *master,
987 struct spi_message *m)
ccdc7bf9
SO		 988{
989 struct omap2_mcspi *mcspi;
ccdc7bf9
SO		 990 struct spi_transfer *t;
991
5fda88f5 992 mcspi = spi_master_get_devdata(master);
ccdc7bf9
SO		 993 m->actual_length = 0;
994 m->status = 0;
995
996 /* reject invalid messages and transfers */
5fda88f5 997 if (list_empty(&m->transfers))
ccdc7bf9
SO		 998 return -EINVAL;
999 list_for_each_entry(t, &m->transfers, transfer_list) {
1000 const void *tx_buf = t->tx_buf;
1001 void *rx_buf = t->rx_buf;
1002 unsigned len = t->len;
1003
1004 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1005 || (len && !(rx_buf || tx_buf))
1006 || (t->bits_per_word &&
1007 ( t->bits_per_word < 4
1008 || t->bits_per_word > 32))) {
5fda88f5 1009 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
ccdc7bf9
SO		 1010 t->speed_hz,
1011 len,
1012 tx_buf ? "tx" : "",
1013 rx_buf ? "rx" : "",
1014 t->bits_per_word);
1015 return -EINVAL;
1016 }
57d9c10d 1017 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
5fda88f5 1018 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
57d9c10d
HH		 1019 t->speed_hz,
1020 OMAP2_MCSPI_MAX_FREQ >> 15);
ccdc7bf9
SO		 1021 return -EINVAL;
1022 }
1023
1024 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1025 continue;
1026
ccdc7bf9 1027 if (tx_buf != NULL) {
5fda88f5 1028 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
ccdc7bf9 1029 len, DMA_TO_DEVICE);
5fda88f5
S		 1030 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1031 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1032 'T', len);
1033 return -EINVAL;
1034 }
1035 }
1036 if (rx_buf != NULL) {
5fda88f5 1037 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
ccdc7bf9 1038 DMA_FROM_DEVICE);
5fda88f5
S		 1039 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1040 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
ccdc7bf9
SO		 1041 'R', len);
1042 if (tx_buf != NULL)
5fda88f5 1043 dma_unmap_single(mcspi->dev, t->tx_dma,
ccdc7bf9
SO		 1044 len, DMA_TO_DEVICE);
1045 return -EINVAL;
1046 }
1047 }
1048 }
1049
5fda88f5
S		 1050 omap2_mcspi_work(mcspi, m);
1051 spi_finalize_current_message(master);
ccdc7bf9
SO		 1052 return 0;
1053}
1054
24ab3275 1055static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
ccdc7bf9
SO		 1056{
1057 struct spi_master *master = mcspi->master;
1bd897f8 1058 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1bd897f8 1059 int ret = 0;
ccdc7bf9 1060
034d3dc9 1061 ret = pm_runtime_get_sync(mcspi->dev);
1f1a4384
G		 1062 if (ret < 0)
1063 return ret;
ddb22195 1064
39f8052d
S		 1065 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1066 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1067 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
ccdc7bf9
SO		 1068
1069 omap2_mcspi_set_master_mode(master);
034d3dc9
S		 1070 pm_runtime_mark_last_busy(mcspi->dev);
1071 pm_runtime_put_autosuspend(mcspi->dev);
ccdc7bf9
SO		 1072 return 0;
1073}
1074
1f1a4384
G		 1075static int omap_mcspi_runtime_resume(struct device *dev)
1076{
1077 struct omap2_mcspi *mcspi;
1078 struct spi_master *master;
1079
1080 master = dev_get_drvdata(dev);
1081 mcspi = spi_master_get_devdata(master);
1082 omap2_mcspi_restore_ctx(mcspi);
1083
1084 return 0;
1085}
1086
d5a80031
BC		 1087static struct omap2_mcspi_platform_config omap2_pdata = {
1088 .regs_offset = 0,
1089};
1090
1091static struct omap2_mcspi_platform_config omap4_pdata = {
1092 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1093};
1094
1095static const struct of_device_id omap_mcspi_of_match[] = {
1096 {
1097 .compatible = "ti,omap2-mcspi",
1098 .data = &omap2_pdata,
1099 },
1100 {
1101 .compatible = "ti,omap4-mcspi",
1102 .data = &omap4_pdata,
1103 },
1104 { },
1105};
1106MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
ccc7baed 1107
7d6b6d83 1108static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
ccdc7bf9
SO		 1109{
1110 struct spi_master *master;
d5a80031 1111 struct omap2_mcspi_platform_config *pdata;
ccdc7bf9
SO		 1112 struct omap2_mcspi *mcspi;
1113 struct resource *r;
1114 int status = 0, i;
d5a80031
BC		 1115 u32 regs_offset = 0;
1116 static int bus_num = 1;
1117 struct device_node *node = pdev->dev.of_node;
1118 const struct of_device_id *match;
ccdc7bf9
SO		 1119
1120 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1121 if (master == NULL) {
1122 dev_dbg(&pdev->dev, "master allocation failed\n");
1123 return -ENOMEM;
1124 }
1125
e7db06b5
DB		 1126 /* the spi->mode bits understood by this driver: */
1127 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1128
ccdc7bf9 1129 master->setup = omap2_mcspi_setup;
5fda88f5
S		 1130 master->prepare_transfer_hardware = omap2_prepare_transfer;
1131 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1132 master->transfer_one_message = omap2_mcspi_transfer_one_message;
ccdc7bf9 1133 master->cleanup = omap2_mcspi_cleanup;
d5a80031
BC		 1134 master->dev.of_node = node;
1135
1136 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1137 if (match) {
1138 u32 num_cs = 1; /* default number of chipselect */
1139 pdata = match->data;
1140
1141 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1142 master->num_chipselect = num_cs;
1143 master->bus_num = bus_num++;
1144 } else {
1145 pdata = pdev->dev.platform_data;
1146 master->num_chipselect = pdata->num_cs;
1147 if (pdev->id != -1)
1148 master->bus_num = pdev->id;
1149 }
1150 regs_offset = pdata->regs_offset;
ccdc7bf9
SO		 1151
1152 dev_set_drvdata(&pdev->dev, master);
1153
1154 mcspi = spi_master_get_devdata(master);
1155 mcspi->master = master;
1156
1157 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1158 if (r == NULL) {
1159 status = -ENODEV;
39f1b565 1160 goto free_master;
ccdc7bf9 1161 }
1458d160 1162
d5a80031
BC		 1163 r->start += regs_offset;
1164 r->end += regs_offset;
1458d160 1165 mcspi->phys = r->start;
ccdc7bf9 1166
1a77b127 1167 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
55c381e4
RK		 1168 if (!mcspi->base) {
1169 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1170 status = -ENOMEM;
1a77b127 1171 goto free_master;
55c381e4 1172 }
ccdc7bf9 1173
1f1a4384 1174 mcspi->dev = &pdev->dev;
ccdc7bf9 1175
1bd897f8 1176 INIT_LIST_HEAD(&mcspi->ctx.cs);
ccdc7bf9 1177
ccdc7bf9
SO		 1178 mcspi->dma_channels = kcalloc(master->num_chipselect,
1179 sizeof(struct omap2_mcspi_dma),
1180 GFP_KERNEL);
1181
1182 if (mcspi->dma_channels == NULL)
1a77b127 1183 goto free_master;
ccdc7bf9 1184
1a5d8190
C		 1185 for (i = 0; i < master->num_chipselect; i++) {
1186 char dma_ch_name[14];
1187 struct resource *dma_res;
1188
1189 sprintf(dma_ch_name, "rx%d", i);
1190 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1191 dma_ch_name);
1192 if (!dma_res) {
1193 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1194 status = -ENODEV;
1195 break;
1196 }
1197
1a5d8190
C		 1198 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1199 sprintf(dma_ch_name, "tx%d", i);
1200 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1201 dma_ch_name);
1202 if (!dma_res) {
1203 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1204 status = -ENODEV;
1205 break;
1206 }
1207
1a5d8190 1208 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
ccdc7bf9
SO		 1209 }
1210
39f1b565
S		 1211 if (status < 0)
1212 goto dma_chnl_free;
1213
27b5284c
S		 1214 pm_runtime_use_autosuspend(&pdev->dev);
1215 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1f1a4384
G		 1216 pm_runtime_enable(&pdev->dev);
1217
1218 if (status || omap2_mcspi_master_setup(mcspi) < 0)
39f1b565 1219 goto disable_pm;
ccdc7bf9
SO		 1220
1221 status = spi_register_master(master);
1222 if (status < 0)
39f1b565 1223 goto err_spi_register;
ccdc7bf9
SO		 1224
1225 return status;
1226
39f1b565 1227err_spi_register:
1f1a4384 1228 spi_master_put(master);
39f1b565 1229disable_pm:
751c925c 1230 pm_runtime_disable(&pdev->dev);
39f1b565 1231dma_chnl_free:
1f1a4384 1232 kfree(mcspi->dma_channels);
39f1b565
S		 1233free_master:
1234 kfree(master);
ccdc7bf9
SO		 1235 return status;
1236}
1237
7d6b6d83 1238static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
ccdc7bf9
SO		 1239{
1240 struct spi_master *master;
1241 struct omap2_mcspi *mcspi;
1242 struct omap2_mcspi_dma *dma_channels;
ccdc7bf9
SO		 1243
1244 master = dev_get_drvdata(&pdev->dev);
1245 mcspi = spi_master_get_devdata(master);
1246 dma_channels = mcspi->dma_channels;
1247
a93a2029 1248 pm_runtime_put_sync(mcspi->dev);
751c925c 1249 pm_runtime_disable(&pdev->dev);
ccdc7bf9
SO		 1250
1251 spi_unregister_master(master);
1252 kfree(dma_channels);
1253
1254 return 0;
1255}
1256
7e38c3c4
KS		 1257/* work with hotplug and coldplug */
1258MODULE_ALIAS("platform:omap2_mcspi");
1259
42ce7fd6
GC		 1260#ifdef CONFIG_SUSPEND
1261/*
1262 * When SPI wake up from off-mode, CS is in activate state. If it was in
1263 * unactive state when driver was suspend, then force it to unactive state at
1264 * wake up.
1265 */
1266static int omap2_mcspi_resume(struct device *dev)
1267{
1268 struct spi_master *master = dev_get_drvdata(dev);
1269 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1bd897f8
BC		 1270 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1271 struct omap2_mcspi_cs *cs;
42ce7fd6 1272
034d3dc9 1273 pm_runtime_get_sync(mcspi->dev);
1bd897f8 1274 list_for_each_entry(cs, &ctx->cs, node) {
42ce7fd6 1275 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
42ce7fd6
GC		 1276 /*
1277 * We need to toggle CS state for OMAP take this
1278 * change in account.
1279 */
af4e944d 1280 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6 1281 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
af4e944d 1282 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
42ce7fd6
GC		 1283 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1284 }
1285 }
034d3dc9
S		 1286 pm_runtime_mark_last_busy(mcspi->dev);
1287 pm_runtime_put_autosuspend(mcspi->dev);
42ce7fd6
GC		 1288 return 0;
1289}
1290#else
1291#define omap2_mcspi_resume NULL
1292#endif
1293
1294static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1295 .resume = omap2_mcspi_resume,
1f1a4384 1296 .runtime_resume = omap_mcspi_runtime_resume,
42ce7fd6
GC		 1297};
1298
ccdc7bf9
SO		 1299static struct platform_driver omap2_mcspi_driver = {
1300 .driver = {
1301 .name = "omap2_mcspi",
1302 .owner = THIS_MODULE,
d5a80031
BC		 1303 .pm = &omap2_mcspi_pm_ops,
1304 .of_match_table = omap_mcspi_of_match,
ccdc7bf9 1305 },
7d6b6d83
FB		 1306 .probe = omap2_mcspi_probe,
1307 .remove = __devexit_p(omap2_mcspi_remove),
ccdc7bf9
SO		 1308};
1309
9fdca9df 1310module_platform_driver(omap2_mcspi_driver);
ccdc7bf9 1311MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)