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Merge branch 'spi' of git://gitorious.org/linus-tree/linus-tree into spi/next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-omap2-mcspi.c
CommitLineData
ccdc7bf9
SO		 1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
1a5d8190 6 * Juha Yrj�l� <juha.yrjola@nokia.com>
ccdc7bf9
SO		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/io.h>
5a0e3ad6 35#include <linux/slab.h>
1f1a4384 36#include <linux/pm_runtime.h>
d5a80031
BC		 37#include <linux/of.h>
38#include <linux/of_device.h>
ccdc7bf9
SO		 39
40#include <linux/spi/spi.h>
41
ce491cf8
TL		 42#include <plat/dma.h>
43#include <plat/clock.h>
4743a0f8 44#include <plat/mcspi.h>
ccdc7bf9
SO		 45
46#define OMAP2_MCSPI_MAX_FREQ 48000000
47
a41ae1ad
H		 48/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
49#define OMAP2_MCSPI_MAX_CTRL 4
50
ccdc7bf9 51#define OMAP2_MCSPI_REVISION 0x00
ccdc7bf9
SO		 52#define OMAP2_MCSPI_SYSSTATUS 0x14
53#define OMAP2_MCSPI_IRQSTATUS 0x18
54#define OMAP2_MCSPI_IRQENABLE 0x1c
55#define OMAP2_MCSPI_WAKEUPENABLE 0x20
56#define OMAP2_MCSPI_SYST 0x24
57#define OMAP2_MCSPI_MODULCTRL 0x28
58
59/* per-channel banks, 0x14 bytes each, first is: */
60#define OMAP2_MCSPI_CHCONF0 0x2c
61#define OMAP2_MCSPI_CHSTAT0 0x30
62#define OMAP2_MCSPI_CHCTRL0 0x34
63#define OMAP2_MCSPI_TX0 0x38
64#define OMAP2_MCSPI_RX0 0x3c
65
66/* per-register bitmasks: */
67
7a8fa725
JH		 68#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
69#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
70#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
ccdc7bf9 71
7a8fa725
JH		 72#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
73#define OMAP2_MCSPI_CHCONF_POL BIT(1)
ccdc7bf9 74#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
7a8fa725 75#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
ccdc7bf9 76#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
7a8fa725
JH		 77#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
78#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
ccdc7bf9 79#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
7a8fa725
JH		 80#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
81#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
82#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
83#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
84#define OMAP2_MCSPI_CHCONF_IS BIT(18)
85#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
86#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
ccdc7bf9 87
7a8fa725
JH		 88#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
89#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
90#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
ccdc7bf9 91
7a8fa725 92#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
ccdc7bf9 93
7a8fa725 94#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
ccdc7bf9
SO		 95
96/* We have 2 DMA channels per CS, one for RX and one for TX */
97struct omap2_mcspi_dma {
98 int dma_tx_channel;
99 int dma_rx_channel;
100
101 int dma_tx_sync_dev;
102 int dma_rx_sync_dev;
103
104 struct completion dma_tx_completion;
105 struct completion dma_rx_completion;
106};
107
108/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
109 * cache operations; better heuristics consider wordsize and bitrate.
110 */
8b66c134 111#define DMA_MIN_BYTES 160
ccdc7bf9
SO		 112
113
114struct omap2_mcspi {
115 struct work_struct work;
116 /* lock protects queue and registers */
117 spinlock_t lock;
118 struct list_head msg_queue;
119 struct spi_master *master;
ccdc7bf9
SO		 120 /* Virtual base address of the controller */
121 void __iomem *base;
e5480b73 122 unsigned long phys;
ccdc7bf9
SO		 123 /* SPI1 has 4 channels, while SPI2 has 2 */
124 struct omap2_mcspi_dma *dma_channels;
1f1a4384 125 struct device *dev;
2856ac13 126 struct workqueue_struct *wq;
ccdc7bf9
SO		 127};
128
129struct omap2_mcspi_cs {
130 void __iomem *base;
e5480b73 131 unsigned long phys;
ccdc7bf9 132 int word_len;
89c05372 133 struct list_head node;
a41ae1ad
H		 134 /* Context save and restore shadow register */
135 u32 chconf0;
136};
137
138/* used for context save and restore, structure members to be updated whenever
139 * corresponding registers are modified.
140 */
141struct omap2_mcspi_regs {
a41ae1ad
H		 142 u32 modulctrl;
143 u32 wakeupenable;
89c05372 144 struct list_head cs;
ccdc7bf9
SO		 145};
146
a41ae1ad
H		 147static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
148
ccdc7bf9
SO		 149#define MOD_REG_BIT(val, mask, set) do { \
150 if (set) \
151 val |= mask; \
152 else \
153 val &= ~mask; \
154} while (0)
155
156static inline void mcspi_write_reg(struct spi_master *master,
157 int idx, u32 val)
158{
159 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
160
161 __raw_writel(val, mcspi->base + idx);
162}
163
164static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
165{
166 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
167
168 return __raw_readl(mcspi->base + idx);
169}
170
171static inline void mcspi_write_cs_reg(const struct spi_device *spi,
172 int idx, u32 val)
173{
174 struct omap2_mcspi_cs *cs = spi->controller_state;
175
176 __raw_writel(val, cs->base + idx);
177}
178
179static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
180{
181 struct omap2_mcspi_cs *cs = spi->controller_state;
182
183 return __raw_readl(cs->base + idx);
184}
185
a41ae1ad
H		 186static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
187{
188 struct omap2_mcspi_cs *cs = spi->controller_state;
189
190 return cs->chconf0;
191}
192
193static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
194{
195 struct omap2_mcspi_cs *cs = spi->controller_state;
196
197 cs->chconf0 = val;
198 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
a330ce20 199 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
a41ae1ad
H		 200}
201
ccdc7bf9
SO		 202static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
203 int is_read, int enable)
204{
205 u32 l, rw;
206
a41ae1ad 207 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 208
209 if (is_read) /* 1 is read, 0 write */
210 rw = OMAP2_MCSPI_CHCONF_DMAR;
211 else
212 rw = OMAP2_MCSPI_CHCONF_DMAW;
213
214 MOD_REG_BIT(l, rw, enable);
a41ae1ad 215 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 216}
217
218static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
219{
220 u32 l;
221
222 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
223 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
4743a0f8
RT		 224 /* Flash post-writes */
225 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
ccdc7bf9
SO		 226}
227
228static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
229{
230 u32 l;
231
a41ae1ad 232 l = mcspi_cached_chconf0(spi);
ccdc7bf9 233 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
a41ae1ad 234 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 235}
236
237static void omap2_mcspi_set_master_mode(struct spi_master *master)
238{
239 u32 l;
240
241 /* setup when switching from (reset default) slave mode
242 * to single-channel master mode
243 */
244 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
245 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
246 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
247 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
248 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
a41ae1ad
H		 249
250 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
251}
252
253static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
254{
255 struct spi_master *spi_cntrl;
89c05372 256 struct omap2_mcspi_cs *cs;
a41ae1ad
H		 257 spi_cntrl = mcspi->master;
258
259 /* McSPI: context restore */
260 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
261 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
262
a41ae1ad
H		 263 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
264 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
89c05372
TK		 265
266 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
267 node)
268 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
a41ae1ad
H		 269}
270static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
271{
1f1a4384 272 pm_runtime_put_sync(mcspi->dev);
a41ae1ad
H		 273}
274
275static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
276{
1f1a4384 277 return pm_runtime_get_sync(mcspi->dev);
ccdc7bf9
SO		 278}
279
2764c500
IK		 280static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
281{
282 unsigned long timeout;
283
284 timeout = jiffies + msecs_to_jiffies(1000);
285 while (!(__raw_readl(reg) & bit)) {
286 if (time_after(jiffies, timeout))
287 return -1;
288 cpu_relax();
289 }
290 return 0;
291}
292
ccdc7bf9
SO		 293static unsigned
294omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
295{
296 struct omap2_mcspi *mcspi;
297 struct omap2_mcspi_cs *cs = spi->controller_state;
298 struct omap2_mcspi_dma *mcspi_dma;
299 unsigned int count, c;
300 unsigned long base, tx_reg, rx_reg;
301 int word_len, data_type, element_count;
8b20c8cb 302 int elements = 0;
4743a0f8 303 u32 l;
ccdc7bf9
SO		 304 u8 * rx;
305 const u8 * tx;
2764c500 306 void __iomem *chstat_reg;
ccdc7bf9
SO		 307
308 mcspi = spi_master_get_devdata(spi->master);
309 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
4743a0f8 310 l = mcspi_cached_chconf0(spi);
ccdc7bf9 311
2764c500
IK		 312 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
313
ccdc7bf9
SO		 314 count = xfer->len;
315 c = count;
316 word_len = cs->word_len;
317
e5480b73 318 base = cs->phys;
ccdc7bf9
SO		 319 tx_reg = base + OMAP2_MCSPI_TX0;
320 rx_reg = base + OMAP2_MCSPI_RX0;
321 rx = xfer->rx_buf;
322 tx = xfer->tx_buf;
323
324 if (word_len <= 8) {
325 data_type = OMAP_DMA_DATA_TYPE_S8;
326 element_count = count;
327 } else if (word_len <= 16) {
328 data_type = OMAP_DMA_DATA_TYPE_S16;
329 element_count = count >> 1;
330 } else /* word_len <= 32 */ {
331 data_type = OMAP_DMA_DATA_TYPE_S32;
332 element_count = count >> 2;
333 }
334
335 if (tx != NULL) {
336 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
337 data_type, element_count, 1,
338 OMAP_DMA_SYNC_ELEMENT,
339 mcspi_dma->dma_tx_sync_dev, 0);
340
341 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
342 OMAP_DMA_AMODE_CONSTANT,
343 tx_reg, 0, 0);
344
345 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
346 OMAP_DMA_AMODE_POST_INC,
347 xfer->tx_dma, 0, 0);
348 }
349
350 if (rx != NULL) {
4743a0f8
RT		 351 elements = element_count - 1;
352 if (l & OMAP2_MCSPI_CHCONF_TURBO)
353 elements--;
354
ccdc7bf9 355 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
4743a0f8 356 data_type, elements, 1,
ccdc7bf9
SO		 357 OMAP_DMA_SYNC_ELEMENT,
358 mcspi_dma->dma_rx_sync_dev, 1);
359
360 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
361 OMAP_DMA_AMODE_CONSTANT,
362 rx_reg, 0, 0);
363
364 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
365 OMAP_DMA_AMODE_POST_INC,
366 xfer->rx_dma, 0, 0);
367 }
368
369 if (tx != NULL) {
370 omap_start_dma(mcspi_dma->dma_tx_channel);
371 omap2_mcspi_set_dma_req(spi, 0, 1);
372 }
373
374 if (rx != NULL) {
375 omap_start_dma(mcspi_dma->dma_rx_channel);
376 omap2_mcspi_set_dma_req(spi, 1, 1);
377 }
378
379 if (tx != NULL) {
380 wait_for_completion(&mcspi_dma->dma_tx_completion);
07fe0351 381 dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
2764c500
IK		 382
383 /* for TX_ONLY mode, be sure all words have shifted out */
384 if (rx == NULL) {
385 if (mcspi_wait_for_reg_bit(chstat_reg,
386 OMAP2_MCSPI_CHSTAT_TXS) < 0)
387 dev_err(&spi->dev, "TXS timed out\n");
388 else if (mcspi_wait_for_reg_bit(chstat_reg,
389 OMAP2_MCSPI_CHSTAT_EOT) < 0)
390 dev_err(&spi->dev, "EOT timed out\n");
391 }
ccdc7bf9
SO		 392 }
393
394 if (rx != NULL) {
395 wait_for_completion(&mcspi_dma->dma_rx_completion);
07fe0351 396 dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
57c5c28d 397 omap2_mcspi_set_enable(spi, 0);
4743a0f8
RT		 398
399 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
400
401 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
402 & OMAP2_MCSPI_CHSTAT_RXS)) {
403 u32 w;
404
405 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
406 if (word_len <= 8)
407 ((u8 *)xfer->rx_buf)[elements++] = w;
408 else if (word_len <= 16)
409 ((u16 *)xfer->rx_buf)[elements++] = w;
410 else /* word_len <= 32 */
411 ((u32 *)xfer->rx_buf)[elements++] = w;
412 } else {
413 dev_err(&spi->dev,
414 "DMA RX penultimate word empty");
415 count -= (word_len <= 8) ? 2 :
416 (word_len <= 16) ? 4 :
417 /* word_len <= 32 */ 8;
418 omap2_mcspi_set_enable(spi, 1);
419 return count;
420 }
421 }
422
57c5c28d
EN		 423 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
424 & OMAP2_MCSPI_CHSTAT_RXS)) {
425 u32 w;
426
427 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
428 if (word_len <= 8)
4743a0f8 429 ((u8 *)xfer->rx_buf)[elements] = w;
57c5c28d 430 else if (word_len <= 16)
4743a0f8 431 ((u16 *)xfer->rx_buf)[elements] = w;
57c5c28d 432 else /* word_len <= 32 */
4743a0f8 433 ((u32 *)xfer->rx_buf)[elements] = w;
57c5c28d
EN		 434 } else {
435 dev_err(&spi->dev, "DMA RX last word empty");
436 count -= (word_len <= 8) ? 1 :
437 (word_len <= 16) ? 2 :
438 /* word_len <= 32 */ 4;
439 }
440 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 441 }
442 return count;
443}
444
ccdc7bf9
SO		 445static unsigned
446omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
447{
448 struct omap2_mcspi *mcspi;
449 struct omap2_mcspi_cs *cs = spi->controller_state;
450 unsigned int count, c;
451 u32 l;
452 void __iomem *base = cs->base;
453 void __iomem *tx_reg;
454 void __iomem *rx_reg;
455 void __iomem *chstat_reg;
456 int word_len;
457
458 mcspi = spi_master_get_devdata(spi->master);
459 count = xfer->len;
460 c = count;
461 word_len = cs->word_len;
462
a41ae1ad 463 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 464
465 /* We store the pre-calculated register addresses on stack to speed
466 * up the transfer loop. */
467 tx_reg = base + OMAP2_MCSPI_TX0;
468 rx_reg = base + OMAP2_MCSPI_RX0;
469 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
470
adef658d
MJ		 471 if (c < (word_len>>3))
472 return 0;
473
ccdc7bf9
SO		 474 if (word_len <= 8) {
475 u8 *rx;
476 const u8 *tx;
477
478 rx = xfer->rx_buf;
479 tx = xfer->tx_buf;
480
481 do {
feed9bab 482 c -= 1;
ccdc7bf9
SO		 483 if (tx != NULL) {
484 if (mcspi_wait_for_reg_bit(chstat_reg,
485 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
486 dev_err(&spi->dev, "TXS timed out\n");
487 goto out;
488 }
079a176d 489 dev_vdbg(&spi->dev, "write-%d %02x\n",
ccdc7bf9 490 word_len, *tx);
ccdc7bf9
SO		 491 __raw_writel(*tx++, tx_reg);
492 }
493 if (rx != NULL) {
494 if (mcspi_wait_for_reg_bit(chstat_reg,
495 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
496 dev_err(&spi->dev, "RXS timed out\n");
497 goto out;
498 }
4743a0f8
RT		 499
500 if (c == 1 && tx == NULL &&
501 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
502 omap2_mcspi_set_enable(spi, 0);
503 *rx++ = __raw_readl(rx_reg);
079a176d 504 dev_vdbg(&spi->dev, "read-%d %02x\n",
4743a0f8 505 word_len, *(rx - 1));
4743a0f8
RT		 506 if (mcspi_wait_for_reg_bit(chstat_reg,
507 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
508 dev_err(&spi->dev,
509 "RXS timed out\n");
510 goto out;
511 }
512 c = 0;
513 } else if (c == 0 && tx == NULL) {
514 omap2_mcspi_set_enable(spi, 0);
515 }
516
ccdc7bf9 517 *rx++ = __raw_readl(rx_reg);
079a176d 518 dev_vdbg(&spi->dev, "read-%d %02x\n",
ccdc7bf9 519 word_len, *(rx - 1));
ccdc7bf9 520 }
95c5c3ab 521 } while (c);
ccdc7bf9
SO		 522 } else if (word_len <= 16) {
523 u16 *rx;
524 const u16 *tx;
525
526 rx = xfer->rx_buf;
527 tx = xfer->tx_buf;
528 do {
feed9bab 529 c -= 2;
ccdc7bf9
SO		 530 if (tx != NULL) {
531 if (mcspi_wait_for_reg_bit(chstat_reg,
532 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
533 dev_err(&spi->dev, "TXS timed out\n");
534 goto out;
535 }
079a176d 536 dev_vdbg(&spi->dev, "write-%d %04x\n",
ccdc7bf9 537 word_len, *tx);
ccdc7bf9
SO		 538 __raw_writel(*tx++, tx_reg);
539 }
540 if (rx != NULL) {
541 if (mcspi_wait_for_reg_bit(chstat_reg,
542 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
543 dev_err(&spi->dev, "RXS timed out\n");
544 goto out;
545 }
4743a0f8
RT		 546
547 if (c == 2 && tx == NULL &&
548 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
549 omap2_mcspi_set_enable(spi, 0);
550 *rx++ = __raw_readl(rx_reg);
079a176d 551 dev_vdbg(&spi->dev, "read-%d %04x\n",
4743a0f8 552 word_len, *(rx - 1));
4743a0f8
RT		 553 if (mcspi_wait_for_reg_bit(chstat_reg,
554 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
555 dev_err(&spi->dev,
556 "RXS timed out\n");
557 goto out;
558 }
559 c = 0;
560 } else if (c == 0 && tx == NULL) {
561 omap2_mcspi_set_enable(spi, 0);
562 }
563
ccdc7bf9 564 *rx++ = __raw_readl(rx_reg);
079a176d 565 dev_vdbg(&spi->dev, "read-%d %04x\n",
ccdc7bf9 566 word_len, *(rx - 1));
ccdc7bf9 567 }
95c5c3ab 568 } while (c >= 2);
ccdc7bf9
SO		 569 } else if (word_len <= 32) {
570 u32 *rx;
571 const u32 *tx;
572
573 rx = xfer->rx_buf;
574 tx = xfer->tx_buf;
575 do {
feed9bab 576 c -= 4;
ccdc7bf9
SO		 577 if (tx != NULL) {
578 if (mcspi_wait_for_reg_bit(chstat_reg,
579 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
580 dev_err(&spi->dev, "TXS timed out\n");
581 goto out;
582 }
079a176d 583 dev_vdbg(&spi->dev, "write-%d %08x\n",
ccdc7bf9 584 word_len, *tx);
ccdc7bf9
SO		 585 __raw_writel(*tx++, tx_reg);
586 }
587 if (rx != NULL) {
588 if (mcspi_wait_for_reg_bit(chstat_reg,
589 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
590 dev_err(&spi->dev, "RXS timed out\n");
591 goto out;
592 }
4743a0f8
RT		 593
594 if (c == 4 && tx == NULL &&
595 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
596 omap2_mcspi_set_enable(spi, 0);
597 *rx++ = __raw_readl(rx_reg);
079a176d 598 dev_vdbg(&spi->dev, "read-%d %08x\n",
4743a0f8 599 word_len, *(rx - 1));
4743a0f8
RT		 600 if (mcspi_wait_for_reg_bit(chstat_reg,
601 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
602 dev_err(&spi->dev,
603 "RXS timed out\n");
604 goto out;
605 }
606 c = 0;
607 } else if (c == 0 && tx == NULL) {
608 omap2_mcspi_set_enable(spi, 0);
609 }
610
ccdc7bf9 611 *rx++ = __raw_readl(rx_reg);
079a176d 612 dev_vdbg(&spi->dev, "read-%d %08x\n",
ccdc7bf9 613 word_len, *(rx - 1));
ccdc7bf9 614 }
95c5c3ab 615 } while (c >= 4);
ccdc7bf9
SO		 616 }
617
618 /* for TX_ONLY mode, be sure all words have shifted out */
619 if (xfer->rx_buf == NULL) {
620 if (mcspi_wait_for_reg_bit(chstat_reg,
621 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
622 dev_err(&spi->dev, "TXS timed out\n");
623 } else if (mcspi_wait_for_reg_bit(chstat_reg,
624 OMAP2_MCSPI_CHSTAT_EOT) < 0)
625 dev_err(&spi->dev, "EOT timed out\n");
e1993ed6
JW		 626
627 /* disable chan to purge rx datas received in TX_ONLY transfer,
628 * otherwise these rx datas will affect the direct following
629 * RX_ONLY transfer.
630 */
631 omap2_mcspi_set_enable(spi, 0);
ccdc7bf9
SO		 632 }
633out:
4743a0f8 634 omap2_mcspi_set_enable(spi, 1);
ccdc7bf9
SO		 635 return count - c;
636}
637
57d9c10d
HH		 638static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
639{
640 u32 div;
641
642 for (div = 0; div < 15; div++)
643 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
644 return div;
645
646 return 15;
647}
648
ccdc7bf9
SO		 649/* called only when no transfer is active to this device */
650static int omap2_mcspi_setup_transfer(struct spi_device *spi,
651 struct spi_transfer *t)
652{
653 struct omap2_mcspi_cs *cs = spi->controller_state;
654 struct omap2_mcspi *mcspi;
a41ae1ad 655 struct spi_master *spi_cntrl;
ccdc7bf9
SO		 656 u32 l = 0, div = 0;
657 u8 word_len = spi->bits_per_word;
9bd4517d 658 u32 speed_hz = spi->max_speed_hz;
ccdc7bf9
SO		 659
660 mcspi = spi_master_get_devdata(spi->master);
a41ae1ad 661 spi_cntrl = mcspi->master;
ccdc7bf9
SO		 662
663 if (t != NULL && t->bits_per_word)
664 word_len = t->bits_per_word;
665
666 cs->word_len = word_len;
667
9bd4517d
SE		 668 if (t && t->speed_hz)
669 speed_hz = t->speed_hz;
670
57d9c10d
HH		 671 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
672 div = omap2_mcspi_calc_divisor(speed_hz);
ccdc7bf9 673
a41ae1ad 674 l = mcspi_cached_chconf0(spi);
ccdc7bf9
SO		 675
676 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
677 * REVISIT: this controller could support SPI_3WIRE mode.
678 */
679 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
680 l |= OMAP2_MCSPI_CHCONF_DPE0;
681
682 /* wordlength */
683 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
684 l |= (word_len - 1) << 7;
685
686 /* set chipselect polarity; manage with FORCE */
687 if (!(spi->mode & SPI_CS_HIGH))
688 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
689 else
690 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
691
692 /* set clock divisor */
693 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
694 l |= div << 2;
695
696 /* set SPI mode 0..3 */
697 if (spi->mode & SPI_CPOL)
698 l |= OMAP2_MCSPI_CHCONF_POL;
699 else
700 l &= ~OMAP2_MCSPI_CHCONF_POL;
701 if (spi->mode & SPI_CPHA)
702 l |= OMAP2_MCSPI_CHCONF_PHA;
703 else
704 l &= ~OMAP2_MCSPI_CHCONF_PHA;
705
a41ae1ad 706 mcspi_write_chconf0(spi, l);
ccdc7bf9
SO		 707
708 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
57d9c10d 709 OMAP2_MCSPI_MAX_FREQ >> div,
ccdc7bf9
SO		 710 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
711 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
712
713 return 0;
714}
715
716static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
717{
718 struct spi_device *spi = data;
719 struct omap2_mcspi *mcspi;
720 struct omap2_mcspi_dma *mcspi_dma;
721
722 mcspi = spi_master_get_devdata(spi->master);
723 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
724
725 complete(&mcspi_dma->dma_rx_completion);
726
727 /* We must disable the DMA RX request */
728 omap2_mcspi_set_dma_req(spi, 1, 0);
729}
730
731static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
732{
733 struct spi_device *spi = data;
734 struct omap2_mcspi *mcspi;
735 struct omap2_mcspi_dma *mcspi_dma;
736
737 mcspi = spi_master_get_devdata(spi->master);
738 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
739
740 complete(&mcspi_dma->dma_tx_completion);
741
742 /* We must disable the DMA TX request */
743 omap2_mcspi_set_dma_req(spi, 0, 0);
744}
745
746static int omap2_mcspi_request_dma(struct spi_device *spi)
747{
748 struct spi_master *master = spi->master;
749 struct omap2_mcspi *mcspi;
750 struct omap2_mcspi_dma *mcspi_dma;
751
752 mcspi = spi_master_get_devdata(master);
753 mcspi_dma = mcspi->dma_channels + spi->chip_select;
754
755 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
756 omap2_mcspi_dma_rx_callback, spi,
757 &mcspi_dma->dma_rx_channel)) {
758 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
759 return -EAGAIN;
760 }
761
762 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
763 omap2_mcspi_dma_tx_callback, spi,
764 &mcspi_dma->dma_tx_channel)) {
765 omap_free_dma(mcspi_dma->dma_rx_channel);
766 mcspi_dma->dma_rx_channel = -1;
767 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
768 return -EAGAIN;
769 }
770
771 init_completion(&mcspi_dma->dma_rx_completion);
772 init_completion(&mcspi_dma->dma_tx_completion);
773
774 return 0;
775}
776
ccdc7bf9
SO		 777static int omap2_mcspi_setup(struct spi_device *spi)
778{
779 int ret;
780 struct omap2_mcspi *mcspi;
781 struct omap2_mcspi_dma *mcspi_dma;
782 struct omap2_mcspi_cs *cs = spi->controller_state;
783
7d077197 784 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
ccdc7bf9
SO		 785 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
786 spi->bits_per_word);
787 return -EINVAL;
788 }
789
790 mcspi = spi_master_get_devdata(spi->master);
791 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
792
793 if (!cs) {
1a77b127 794 cs = devm_kzalloc(&spi->dev , sizeof *cs, GFP_KERNEL);
ccdc7bf9
SO		 795 if (!cs)
796 return -ENOMEM;
797 cs->base = mcspi->base + spi->chip_select * 0x14;
e5480b73 798 cs->phys = mcspi->phys + spi->chip_select * 0x14;
a41ae1ad 799 cs->chconf0 = 0;
ccdc7bf9 800 spi->controller_state = cs;
89c05372
TK		 801 /* Link this to context save list */
802 list_add_tail(&cs->node,
803 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
ccdc7bf9
SO		 804 }
805
806 if (mcspi_dma->dma_rx_channel == -1
807 || mcspi_dma->dma_tx_channel == -1) {
808 ret = omap2_mcspi_request_dma(spi);
809 if (ret < 0)
810 return ret;
811 }
812
1f1a4384
G		 813 ret = omap2_mcspi_enable_clocks(mcspi);
814 if (ret < 0)
815 return ret;
a41ae1ad 816
86eeb6fe 817 ret = omap2_mcspi_setup_transfer(spi, NULL);
a41ae1ad 818 omap2_mcspi_disable_clocks(mcspi);
ccdc7bf9
SO		 819
820 return ret;
821}
822
823static void omap2_mcspi_cleanup(struct spi_device *spi)
824{
825 struct omap2_mcspi *mcspi;
826 struct omap2_mcspi_dma *mcspi_dma;
89c05372 827 struct omap2_mcspi_cs *cs;
ccdc7bf9
SO		 828
829 mcspi = spi_master_get_devdata(spi->master);
ccdc7bf9 830
5e774943
SE		 831 if (spi->controller_state) {
832 /* Unlink controller state from context save list */
833 cs = spi->controller_state;
834 list_del(&cs->node);
89c05372 835
5e774943 836 }
ccdc7bf9 837
99f1a43f
SE		 838 if (spi->chip_select < spi->master->num_chipselect) {
839 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
840
841 if (mcspi_dma->dma_rx_channel != -1) {
842 omap_free_dma(mcspi_dma->dma_rx_channel);
843 mcspi_dma->dma_rx_channel = -1;
844 }
845 if (mcspi_dma->dma_tx_channel != -1) {
846 omap_free_dma(mcspi_dma->dma_tx_channel);
847 mcspi_dma->dma_tx_channel = -1;
848 }
ccdc7bf9
SO		 849 }
850}
851
852static void omap2_mcspi_work(struct work_struct *work)
853{
854 struct omap2_mcspi *mcspi;
855
856 mcspi = container_of(work, struct omap2_mcspi, work);
ccdc7bf9 857
1f1a4384
G		 858 if (omap2_mcspi_enable_clocks(mcspi) < 0)
859 return;
860
861 spin_lock_irq(&mcspi->lock);
ccdc7bf9
SO		 862
863 /* We only enable one channel at a time -- the one whose message is
864 * at the head of the queue -- although this controller would gladly
865 * arbitrate among multiple channels. This corresponds to "single
866 * channel" master mode. As a side effect, we need to manage the
867 * chipselect with the FORCE bit ... CS != channel enable.
868 */
869 while (!list_empty(&mcspi->msg_queue)) {
870 struct spi_message *m;
871 struct spi_device *spi;
872 struct spi_transfer *t = NULL;
873 int cs_active = 0;
ccdc7bf9 874 struct omap2_mcspi_cs *cs;
4743a0f8 875 struct omap2_mcspi_device_config *cd;
ccdc7bf9
SO		 876 int par_override = 0;
877 int status = 0;
878 u32 chconf;
879
880 m = container_of(mcspi->msg_queue.next, struct spi_message,
881 queue);
882
883 list_del_init(&m->queue);
884 spin_unlock_irq(&mcspi->lock);
885
886 spi = m->spi;
ccdc7bf9 887 cs = spi->controller_state;
4743a0f8 888 cd = spi->controller_data;
ccdc7bf9
SO		 889
890 omap2_mcspi_set_enable(spi, 1);
891 list_for_each_entry(t, &m->transfers, transfer_list) {
892 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
893 status = -EINVAL;
894 break;
895 }
896 if (par_override || t->speed_hz || t->bits_per_word) {
897 par_override = 1;
898 status = omap2_mcspi_setup_transfer(spi, t);
899 if (status < 0)
900 break;
901 if (!t->speed_hz && !t->bits_per_word)
902 par_override = 0;
903 }
904
905 if (!cs_active) {
906 omap2_mcspi_force_cs(spi, 1);
907 cs_active = 1;
908 }
909
a41ae1ad 910 chconf = mcspi_cached_chconf0(spi);
ccdc7bf9 911 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
4743a0f8
RT		 912 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
913
ccdc7bf9
SO		 914 if (t->tx_buf == NULL)
915 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
916 else if (t->rx_buf == NULL)
917 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
4743a0f8
RT		 918
919 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
920 /* Turbo mode is for more than one word */
921 if (t->len > ((cs->word_len + 7) >> 3))
922 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
923 }
924
a41ae1ad 925 mcspi_write_chconf0(spi, chconf);
ccdc7bf9
SO		 926
927 if (t->len) {
928 unsigned count;
929
930 /* RX_ONLY mode needs dummy data in TX reg */
931 if (t->tx_buf == NULL)
932 __raw_writel(0, cs->base
933 + OMAP2_MCSPI_TX0);
934
935 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
936 count = omap2_mcspi_txrx_dma(spi, t);
937 else
938 count = omap2_mcspi_txrx_pio(spi, t);
939 m->actual_length += count;
940
941 if (count != t->len) {
942 status = -EIO;
943 break;
944 }
945 }
946
947 if (t->delay_usecs)
948 udelay(t->delay_usecs);
949
950 /* ignore the "leave it on after last xfer" hint */
951 if (t->cs_change) {
952 omap2_mcspi_force_cs(spi, 0);
953 cs_active = 0;
954 }
955 }
956
957 /* Restore defaults if they were overriden */
958 if (par_override) {
959 par_override = 0;
960 status = omap2_mcspi_setup_transfer(spi, NULL);
961 }
962
963 if (cs_active)
964 omap2_mcspi_force_cs(spi, 0);
965
966 omap2_mcspi_set_enable(spi, 0);
967
968 m->status = status;
969 m->complete(m->context);
970
971 spin_lock_irq(&mcspi->lock);
972 }
973
ccdc7bf9 974 spin_unlock_irq(&mcspi->lock);
1f1a4384
G		 975
976 omap2_mcspi_disable_clocks(mcspi);
ccdc7bf9
SO		 977}
978
979static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
980{
981 struct omap2_mcspi *mcspi;
982 unsigned long flags;
983 struct spi_transfer *t;
984
985 m->actual_length = 0;
986 m->status = 0;
987
988 /* reject invalid messages and transfers */
989 if (list_empty(&m->transfers) || !m->complete)
990 return -EINVAL;
991 list_for_each_entry(t, &m->transfers, transfer_list) {
992 const void *tx_buf = t->tx_buf;
993 void *rx_buf = t->rx_buf;
994 unsigned len = t->len;
995
996 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
997 || (len && !(rx_buf || tx_buf))
998 || (t->bits_per_word &&
999 ( t->bits_per_word < 4
1000 || t->bits_per_word > 32))) {
1001 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1002 t->speed_hz,
1003 len,
1004 tx_buf ? "tx" : "",
1005 rx_buf ? "rx" : "",
1006 t->bits_per_word);
1007 return -EINVAL;
1008 }
57d9c10d
HH		 1009 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1010 dev_dbg(&spi->dev, "speed_hz %d below minimum %d Hz\n",
1011 t->speed_hz,
1012 OMAP2_MCSPI_MAX_FREQ >> 15);
ccdc7bf9
SO		 1013 return -EINVAL;
1014 }
1015
1016 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1017 continue;
1018
ccdc7bf9
SO		 1019 if (tx_buf != NULL) {
1020 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
1021 len, DMA_TO_DEVICE);
8d8bb39b 1022 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
ccdc7bf9
SO		 1023 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1024 'T', len);
1025 return -EINVAL;
1026 }
1027 }
1028 if (rx_buf != NULL) {
1029 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
1030 DMA_FROM_DEVICE);
8d8bb39b 1031 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
ccdc7bf9
SO		 1032 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1033 'R', len);
1034 if (tx_buf != NULL)
07fe0351 1035 dma_unmap_single(&spi->dev, t->tx_dma,
ccdc7bf9
SO		 1036 len, DMA_TO_DEVICE);
1037 return -EINVAL;
1038 }
1039 }
1040 }
1041
1042 mcspi = spi_master_get_devdata(spi->master);
1043
1044 spin_lock_irqsave(&mcspi->lock, flags);
1045 list_add_tail(&m->queue, &mcspi->msg_queue);
2856ac13 1046 queue_work(mcspi->wq, &mcspi->work);
ccdc7bf9
SO		 1047 spin_unlock_irqrestore(&mcspi->lock, flags);
1048
1049 return 0;
1050}
1051
1f1a4384 1052static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
ccdc7bf9
SO		 1053{
1054 struct spi_master *master = mcspi->master;
1055 u32 tmp;
1f1a4384 1056 int ret = 0;
ccdc7bf9 1057
1f1a4384
G		 1058 ret = omap2_mcspi_enable_clocks(mcspi);
1059 if (ret < 0)
1060 return ret;
ddb22195 1061
a41ae1ad
H		 1062 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1063 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1064 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
ccdc7bf9
SO		 1065
1066 omap2_mcspi_set_master_mode(master);
a41ae1ad 1067 omap2_mcspi_disable_clocks(mcspi);
ccdc7bf9
SO		 1068 return 0;
1069}
1070
1f1a4384
G		 1071static int omap_mcspi_runtime_resume(struct device *dev)
1072{
1073 struct omap2_mcspi *mcspi;
1074 struct spi_master *master;
1075
1076 master = dev_get_drvdata(dev);
1077 mcspi = spi_master_get_devdata(master);
1078 omap2_mcspi_restore_ctx(mcspi);
1079
1080 return 0;
1081}
1082
d5a80031
BC		 1083static struct omap2_mcspi_platform_config omap2_pdata = {
1084 .regs_offset = 0,
1085};
1086
1087static struct omap2_mcspi_platform_config omap4_pdata = {
1088 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1089};
1090
1091static const struct of_device_id omap_mcspi_of_match[] = {
1092 {
1093 .compatible = "ti,omap2-mcspi",
1094 .data = &omap2_pdata,
1095 },
1096 {
1097 .compatible = "ti,omap4-mcspi",
1098 .data = &omap4_pdata,
1099 },
1100 { },
1101};
1102MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
ccc7baed 1103
7d6b6d83 1104static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
ccdc7bf9
SO		 1105{
1106 struct spi_master *master;
d5a80031 1107 struct omap2_mcspi_platform_config *pdata;
ccdc7bf9
SO		 1108 struct omap2_mcspi *mcspi;
1109 struct resource *r;
1110 int status = 0, i;
2856ac13 1111 char wq_name[20];
d5a80031
BC		 1112 u32 regs_offset = 0;
1113 static int bus_num = 1;
1114 struct device_node *node = pdev->dev.of_node;
1115 const struct of_device_id *match;
ccdc7bf9
SO		 1116
1117 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1118 if (master == NULL) {
1119 dev_dbg(&pdev->dev, "master allocation failed\n");
1120 return -ENOMEM;
1121 }
1122
e7db06b5
DB		 1123 /* the spi->mode bits understood by this driver: */
1124 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1125
ccdc7bf9
SO		 1126 master->setup = omap2_mcspi_setup;
1127 master->transfer = omap2_mcspi_transfer;
1128 master->cleanup = omap2_mcspi_cleanup;
d5a80031
BC		 1129 master->dev.of_node = node;
1130
1131 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1132 if (match) {
1133 u32 num_cs = 1; /* default number of chipselect */
1134 pdata = match->data;
1135
1136 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1137 master->num_chipselect = num_cs;
1138 master->bus_num = bus_num++;
1139 } else {
1140 pdata = pdev->dev.platform_data;
1141 master->num_chipselect = pdata->num_cs;
1142 if (pdev->id != -1)
1143 master->bus_num = pdev->id;
1144 }
1145 regs_offset = pdata->regs_offset;
ccdc7bf9
SO		 1146
1147 dev_set_drvdata(&pdev->dev, master);
1148
1149 mcspi = spi_master_get_devdata(master);
1150 mcspi->master = master;
1151
2856ac13
S		 1152 sprintf(wq_name, "omap2_mcspi/%d", master->bus_num);
1153 mcspi->wq = alloc_workqueue(wq_name, WQ_MEM_RECLAIM, 1);
1154 if (mcspi->wq == NULL) {
1155 status = -ENOMEM;
39f1b565 1156 goto free_master;
2856ac13
S		 1157 }
1158
ccdc7bf9
SO		 1159 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1160 if (r == NULL) {
1161 status = -ENODEV;
39f1b565 1162 goto free_master;
ccdc7bf9 1163 }
1458d160 1164
d5a80031
BC		 1165 r->start += regs_offset;
1166 r->end += regs_offset;
1458d160 1167 mcspi->phys = r->start;
ccdc7bf9 1168
1a77b127 1169 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
55c381e4
RK		 1170 if (!mcspi->base) {
1171 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1172 status = -ENOMEM;
1a77b127 1173 goto free_master;
55c381e4 1174 }
ccdc7bf9 1175
1f1a4384 1176 mcspi->dev = &pdev->dev;
ccdc7bf9
SO		 1177 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1178
1179 spin_lock_init(&mcspi->lock);
1180 INIT_LIST_HEAD(&mcspi->msg_queue);
89c05372 1181 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
ccdc7bf9 1182
ccdc7bf9
SO		 1183 mcspi->dma_channels = kcalloc(master->num_chipselect,
1184 sizeof(struct omap2_mcspi_dma),
1185 GFP_KERNEL);
1186
1187 if (mcspi->dma_channels == NULL)
1a77b127 1188 goto free_master;
ccdc7bf9 1189
1a5d8190
C		 1190 for (i = 0; i < master->num_chipselect; i++) {
1191 char dma_ch_name[14];
1192 struct resource *dma_res;
1193
1194 sprintf(dma_ch_name, "rx%d", i);
1195 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1196 dma_ch_name);
1197 if (!dma_res) {
1198 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1199 status = -ENODEV;
1200 break;
1201 }
1202
ccdc7bf9 1203 mcspi->dma_channels[i].dma_rx_channel = -1;
1a5d8190
C		 1204 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1205 sprintf(dma_ch_name, "tx%d", i);
1206 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1207 dma_ch_name);
1208 if (!dma_res) {
1209 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1210 status = -ENODEV;
1211 break;
1212 }
1213
ccdc7bf9 1214 mcspi->dma_channels[i].dma_tx_channel = -1;
1a5d8190 1215 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
ccdc7bf9
SO		 1216 }
1217
39f1b565
S		 1218 if (status < 0)
1219 goto dma_chnl_free;
1220
1f1a4384
G		 1221 pm_runtime_enable(&pdev->dev);
1222
1223 if (status || omap2_mcspi_master_setup(mcspi) < 0)
39f1b565 1224 goto disable_pm;
ccdc7bf9
SO		 1225
1226 status = spi_register_master(master);
1227 if (status < 0)
39f1b565 1228 goto err_spi_register;
ccdc7bf9
SO		 1229
1230 return status;
1231
39f1b565 1232err_spi_register:
1f1a4384 1233 spi_master_put(master);
39f1b565 1234disable_pm:
751c925c 1235 pm_runtime_disable(&pdev->dev);
39f1b565 1236dma_chnl_free:
1f1a4384 1237 kfree(mcspi->dma_channels);
39f1b565
S		 1238free_master:
1239 kfree(master);
1240 platform_set_drvdata(pdev, NULL);
ccdc7bf9
SO		 1241 return status;
1242}
1243
7d6b6d83 1244static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
ccdc7bf9
SO		 1245{
1246 struct spi_master *master;
1247 struct omap2_mcspi *mcspi;
1248 struct omap2_mcspi_dma *dma_channels;
ccdc7bf9
SO		 1249
1250 master = dev_get_drvdata(&pdev->dev);
1251 mcspi = spi_master_get_devdata(master);
1252 dma_channels = mcspi->dma_channels;
1253
1f1a4384 1254 omap2_mcspi_disable_clocks(mcspi);
751c925c 1255 pm_runtime_disable(&pdev->dev);
ccdc7bf9
SO		 1256
1257 spi_unregister_master(master);
1258 kfree(dma_channels);
2856ac13 1259 destroy_workqueue(mcspi->wq);
39f1b565 1260 platform_set_drvdata(pdev, NULL);
ccdc7bf9
SO		 1261
1262 return 0;
1263}
1264
7e38c3c4
KS		 1265/* work with hotplug and coldplug */
1266MODULE_ALIAS("platform:omap2_mcspi");
1267
42ce7fd6
GC		 1268#ifdef CONFIG_SUSPEND
1269/*
1270 * When SPI wake up from off-mode, CS is in activate state. If it was in
1271 * unactive state when driver was suspend, then force it to unactive state at
1272 * wake up.
1273 */
1274static int omap2_mcspi_resume(struct device *dev)
1275{
1276 struct spi_master *master = dev_get_drvdata(dev);
1277 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1278 struct omap2_mcspi_cs *cs;
1279
1280 omap2_mcspi_enable_clocks(mcspi);
1281 list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
1282 node) {
1283 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1284
1285 /*
1286 * We need to toggle CS state for OMAP take this
1287 * change in account.
1288 */
1289 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
1290 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1291 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
1292 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1293 }
1294 }
1295 omap2_mcspi_disable_clocks(mcspi);
1296 return 0;
1297}
1298#else
1299#define omap2_mcspi_resume NULL
1300#endif
1301
1302static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1303 .resume = omap2_mcspi_resume,
1f1a4384 1304 .runtime_resume = omap_mcspi_runtime_resume,
42ce7fd6
GC		 1305};
1306
ccdc7bf9
SO		 1307static struct platform_driver omap2_mcspi_driver = {
1308 .driver = {
1309 .name = "omap2_mcspi",
1310 .owner = THIS_MODULE,
d5a80031
BC		 1311 .pm = &omap2_mcspi_pm_ops,
1312 .of_match_table = omap_mcspi_of_match,
ccdc7bf9 1313 },
7d6b6d83
FB		 1314 .probe = omap2_mcspi_probe,
1315 .remove = __devexit_p(omap2_mcspi_remove),
ccdc7bf9
SO		 1316};
1317
9fdca9df 1318module_platform_driver(omap2_mcspi_driver);
ccdc7bf9 1319MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)